JP2003051198A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that even in a state in which a selected transistor does not allow a current to flow, as a non-selection cell transistor of excessive cancellation allow a current to flow, data 0 and 1 are erroneously determined. SOLUTION: This device is provided with a plurality of word lines WL, a plurality of bit lines, and a memory cell array having a plurality of memory cell transistors provided at intersections of each word line and each bit line, and batch erasure can be performed by discharging simultaneously electric charges from floating gates of a plurality of memory transistors. The device is further provided with a first power source circuit 5021 in which normal voltage is applied to a selected word line at read and a memory cell transistor connected to the selected word line is selected, and a second power source circuit 5025 in which non-selection word lines at read are made non-selection comprising memory cell transistors made in an excessive erasure state by the batch erasure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically batch erasable non-volatile semiconductor memory device such as a flash memory.

Conventionally, EPROM has been used as a nonvolatile semiconductor memory device that can be erased by ultraviolet rays and is electrically writable.
In recent years, a flash memory has attracted attention as an electrically rewritable nonvolatile semiconductor memory device. There is a demand for improvements in redundant circuits and write circuits in these non-volatile semiconductor memory devices, or improvements in measures against excessive erasing.

[0003]

2. Description of the Related Art FIG. 11 shows a memory cell (MC) used in a semiconductor memory device to which the first embodiment of the present invention is applied, and is a cell transistor in an electrically batch erasable non-volatile semiconductor memory device (flash memory). (Memory cell M
It is a figure for demonstrating operation | movement of C). As shown in the figure, the cell transistor is configured such that a floating gate FG insulated from any region is provided between a source and a drain, and a control gate CG is formed on the floating gate FG.

At the time of writing, the drain voltage Vd applied to the drain region DD is substantially the power supply voltage Vcc, and the gate voltage Vg applied to the control gate CG is a positive high voltage (about +10 V) and applied to the source region SS. Drain terminal (DD) with source voltage Vs at zero volt
To inject electrons into the floating gate (FG) and write data “0”. Here, if the power supply voltage Vpp for writing exists, the drain voltage Vd can be used. Further, as the high voltage applied to the gate voltage Vg, the above writing voltage Vpp may be used.
A voltage generated by boosting the power supply voltage Vcc may be used.

At the time of erasing, the gate voltage Vg is set to a negative high voltage (about -10 V), the drain voltage Vd is opened (the drain region DD is in a floating state), and the source voltage Vs is set to the power supply voltage Vcc and floated. Erasing (writing data "1") is performed by drawing electrons from the gate (FG) to the source terminal (SS). At the time of reading, the gate voltage Vg is set to the power supply voltage Vcc, the drain voltage Vd is set to about 1 volt, the source voltage Vs is set to 0 volt, and the data written in the cell transistor depending on whether or not the drain current flows. Is “1”
Or "0".

FIG. 2 shows a first semiconductor memory device according to the present invention.
Is a block circuit diagram showing an example of a semiconductor memory device of a related technique corresponding to the above mode. In the figure, reference numeral 111
Is a row address buffer, 112 is a row decoder, 113 is a column address buffer, 114 is a column decoder, and 115 is data.
I / O buffer, 116 is write circuit, 117 is sense amplifier, 1
Reference numeral 18 is a negative voltage generation circuit, and 119 is a source power supply circuit. Further, reference numeral BL indicates a bit line, WL indicates a word line, W indicates a write control signal which becomes a high level "H" at the time of writing, and E indicates an erase control signal which becomes a high level "H" at the time of erasing. There is.

In the semiconductor memory device shown in FIG. 2, at the time of reading, one word line WL and one bit line BL are selected by a row address and a column address, and a memory cell MC (cell transistor) selected by the sense amplifier 117 is selected. ) Determines whether the content written in the selected cell transistor is data "1" or data "0" depending on whether or not a current flows.

At the time of data writing, the write control signal W is set to the high level "H" to supply the write voltage from the write circuit 116 to the bus line BUS, and the column decoder 114 connects the bus line BUS to a predetermined bit line BL. The row decoder 112 supplies a write voltage to the word line WL. Further, at the time of erasing, the erasing control signal E is set to the high level “H” to apply the erasing voltage to the source line of the cell transistor MC by the source power supply circuit 119, and the bit line BL is unselected by the column address buffer 113. . In addition, row address buffer 11
A predetermined number of word lines WL are simultaneously selected by 1 and a low level “L” is applied to the word line WL selected by the row decoder 112, and WL is selected for the non-selected word lines.
To the negative voltage generating circuit 118.
Thus, the low level "L" level word line WL is set to a negative voltage.

FIG. 3 is a circuit diagram showing an example of the column address buffer 113 in the semiconductor memory device of FIG. 2, FIG. 4 is a circuit diagram showing an example of the row address buffer 111, and FIG. 5 is a circuit diagram showing an example of the row decoder 112. And, FIG. 6 is a circuit diagram showing an example of the column decoder 114.

First, since the erase control signal E is at the low level "L" during reading, the column address buffer 113 shown in FIG. 3 and the row address buffer 111 shown in FIG. 4 are positive and negative with respect to the input address. It will output logic. In the row decoder 112 shown in FIG. 5, reference symbol φ is a signal that oscillates at a predetermined frequency at the time of erasing and writing, and φ _R is a signal that becomes a high level “H” for a while during address input.

The row decoder 112 shown in FIG.
At this time, the write control signal W is at the low level "L".
Therefore, the transistor T₁, T₂ The power supply voltage Vcc
Address input (row address buffer
Output from 111) selects a predetermined decoder (for example,
For example, node N in FIG.₃ Becomes a high level "H"). This
, The signal φ_R A high level “H” pulse signal
Once obtained, node N ₂, N_Four Is reset to zero volts
Signal φ_R Is returned to the low level “L”.
Node N₂ Is charged to the power supply voltage Vcc. further,
Transistor T ₆, T₇ The self-bootstrap effect of
From node N_Four Is also charged to the power supply voltage Vcc level.
Here, the operation in the column decoder 114 is also described above.
The operation is similar to that of the row decoder 112, and after all
The power supply voltage Vcc is applied to the ground line WL, and
The bit line BL is connected to the sense amplifier 117.
ing.

FIG. 7 is a circuit diagram showing an example of write circuit 116 in the semiconductor memory device of FIG. 2, and FIG. 8 is a circuit diagram showing an example of source power supply circuit 119.

In the write circuit 116 shown in FIG. 7, when the write control signal W is at the high level "H" and the data is at the low level "L" (the inverted level signal / DATA is at the high level "H"), the bus line BUS. Is supplied with a high voltage obtained by boosting the power supply voltage Vcc, so that a writing process can be performed on a predetermined cell transistor. Here, / DATA is a signal transferred from the data I / O buffer 115 to the writing circuit 116 as a writing signal.

At the time of erasing, the erasing control signal E is at a high level "H" level, and in the column address buffer 113 of FIG. 3, both outputs A and / A are at a low level "L". These outputs A and / A are input to the column decoder 114, the column (bit line BL) is in a non-selected state, and the bit line BL is electrically disconnected from any node. In addition, the row address buffer 11
In the case of 1, the erase control signal E is applied to m of n in total. This allows
It is possible to simultaneously select 2 ^m word lines by the row decoder 112 in FIG. Incidentally, in the row decoder 112, the erase control signal E is for a high level "H", the node N ₂ becomes zero volts, the high level "H" is applied to the node N _5. As a result, the low level "L" can be applied to the selected word line WL, and the high level "H" can be applied to the non-selected word line WL.

Here, the low level "L" word line WL
Is set to an erase voltage by the negative voltage generation circuit 118, and the potential of the output N ₆ of the NOR gate in FIG. Since it is not transmitted to the capacitive element connected to the node N ₆ , it keeps the high level “H”. At this time,
The power supply voltage Vcc is applied to the source SS of the cell transistor MC by the source power supply circuit 119 shown in FIG. As a result, it becomes possible to simultaneously erase the data of the cell transistors in the word line block in units of 2 ^m word lines.

FIG. 9 is a circuit diagram showing an example of the sense amplifier 117 in the semiconductor memory device of FIG.

In the sense amplifier 117 shown in FIG.
Or drain current of the selected cell transistor MC is greater than the current that can flow through the transistor T _8, or by either small, the sense amplifier 117 outputs a high level "H" or low level "L". Here, the transistors T ₉ , T ₁₀ , T ₁₁ , and T ₁₂ form a bias circuit that sets the potential of the bus line BUS to about 1 volt.

At the time of writing, the write control signal W is set to the high level "H" and the signal φ is oscillated at a predetermined frequency. At this time, the node N _1, the transistor T _4,
The write voltage is supplied by T ₅ . And the signal φ _R
When a high level “H” pulse is applied as in the case of reading by the node N ₂ , the node N ₂ is charged to the write voltage, and the node N ₄ is the same as the node N ₂ due to the self bootstrap effect of the transistors T ₆ and T _7. Charged to level. The column decoder 114 operates in the same manner, and in the end, the write voltage is supplied to the predetermined word line WL and the bit line BL is connected to the write circuit 116.

[0019]

As described with reference to FIGS. 2 to 9, in the related art semiconductor memory device (flash memory), the erase cell block usually has a large capacity of about 512 kbits. Is often used as a unit, and when a defective cell exists in this block, only a redundancy system in which this large block is directly replaced with a redundant cell block having a large capacity can be used. Therefore, it is difficult to perform efficient redundancy (replace a large number of defective cells with a small number of spare cells). Specifically, for example, the memory cell MC in FIG.
_{When 11} is over-erased, current always flows through the bit line BL ₁ via the memory cell MC ₁₁ , and accurate read processing and write processing cannot be performed.

FIG. 10 is a diagram showing an example of a write characteristic curve in a semiconductor memory device (flash memory).

In the configuration of the semiconductor memory device of the related art described above, since the drain voltage for writing is used after being boosted from the power supply voltage Vcc, the bit line has a large driving capability due to the limit of the driving capability of the bit line of the writing circuit. When a current is passed, the bit line potential drops. Depending on the characteristics of the over-erased cell transistor, as shown by the solid line in FIG. 10, the writing characteristic curve of the cell transistor collides with the load curve of the writing circuit 116 in the unwritable area A, and writing cannot be performed. It may be impossible to write (writing is not possible unless the points are D to B). The word line voltage for erase and program verify is generally used by stepping down the voltage for external programming, but since the configuration does not use the voltage for external programming, the verify operation can be performed. Besides, it is difficult, and the normal operation of the device cannot be expected even if the cell transistor which is over-erased in the case of the word line redundancy is simply replaced by the spare cell (spare word line). In this case, by overwriting the cell that has been over-erased, the over-erasing can be canceled and a normal redundant operation can be realized. However, the over-erased cell has a larger current near point A in FIG. Therefore, writing may be more difficult for the above reason.

A first aspect of the present invention aims to realize a device with high yield and high performance by effectively introducing word line redundancy and enabling stable writing and each verification.

[0023]

According to the present invention, a plurality of word lines, a plurality of bit lines, and a charge injection into a floating gate provided at each word line and each intersection of the bit lines. And a memory cell array having a plurality of memory cell transistors configured by MIS transistors capable of electrically controlling the threshold voltage from the outside depending on the presence or absence of the charge, and discharging of charges from the floating gates of the memory cell transistors of the memory cell array at the same time. A semiconductor memory device capable of performing batch erasure by performing a write operation, the first power supply for applying a normal selection voltage to a selected word line at the time of reading and selecting a memory cell transistor connected to the selected word line. Circuit and memory that has been over-erased by the batch erasing for unselected word lines during reading The semiconductor memory device is provided which is characterized by comprising a second power supply circuit for the non-selected, including Le transistor.

Further, according to the present invention, a plurality of word lines, a plurality of bit lines, and an electric charge depending on whether or not charge is injected into the floating gates provided at the intersections of the word lines and the bit lines, respectively. And a memory cell array having a plurality of memory cell transistors composed of MIS transistors capable of controlling a threshold voltage from the outside, and simultaneously discharging charges from the floating gates of the plurality of memory cell transistors of the memory cell array to collectively A semiconductor memory device capable of erasing, a first row decoder that applies a normal voltage to a selected word line at the time of reading, and selects a memory cell transistor connected to the selected word line; Apply a power supply voltage of a predetermined potential to the source of the memory cell transistor connected to the word line At the same time, a second voltage is applied to the sources of all the memory cell transistors connected to the non-selected word line at the time of reading, including the memory cell transistors in the over-erased state due to the collective erasing. And a row decoder for the same.

FIG. 1 shows a first semiconductor memory device according to the present invention.
FIG. 3 is a circuit diagram showing an example of the above embodiment.

According to the first aspect of the present invention, a plurality of 2 ⁿ
A plurality of non-volatile transistors each including a plurality of word lines WL, a plurality of bit lines BL, and MIS transistors that are provided at the intersections of the word lines and the bit lines and that can electrically control the threshold voltage from the outside. Memory cell MC of
A semiconductor memory device comprising: a write circuit (106) for writing data into a memory cell located at an intersection of a selected word line and a bit line; and a sense amplifier (107) for detecting and outputting the data held in the memory cell. Te, wherein the 2 ⁿ word lines means simultaneously selected word lines in the composed word line block by the word line of 2 ^m the (n> m) of 101,102,120, constituting a word line of the 2 ^m present Means 101, 102, 120 for deselecting a word line block composed of 2 ^k (m> k) in the selected word line block
Comprising the door, the 2 ^m If this is the word line defect to the word line in the 2 ^k word lines block in the block, in 2 ^k word lines block in the 2 ^m word lines block Of the word lines in the word line block composed of 2 ^k word lines existing outside the word line block composed of 2 ⁿ lines are selected, and the word lines 101, 102, 120; 120, 130 are selected. A semiconductor memory device is provided.

According to the first embodiment of the semiconductor memory device of [0027] the present invention, if there is a defect in the word lines in the 2 ^k word lines block in 2 ^m word lines block of 2 ^m the word line The word lines in the 2 ^k word line blocks in the block are deselected, and the words in the word line blocks made up of 2 ^k word lines existing outside the word line block made up of 2 ⁿ lines It is designed to select a line. Here, regarding the writing process, the gate voltage is controlled so that the writing curve of the cell is realized so that the current value of the load curve of the writing circuit as shown by a dotted line in FIG. Good. For verification, the word line voltage is generated by raising and lowering Vcc, or the data determination current value of the sense amplifier is controlled. Further, in order to relieve an overerased cell in a redundant manner, data is rewritten to the overerased cell and then redundancy is performed.

As described above, according to the first embodiment of the semiconductor memory device of the present invention, efficient word line redundancy becomes possible, and when the external write power supply is eliminated (for example,
Even if it is set to a 5V single power supply), writing can be effectively performed. Furthermore, according to the first embodiment of the semiconductor memory device of the present invention, it becomes possible to write into an overerased cell, redundancy of the overerased cell becomes possible, and good verification can be performed well.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.

First, a first mode of a semiconductor memory device according to the present invention will be described with reference to FIGS. 1 and 11 to 19.

FIG. 1 is a block circuit diagram showing an embodiment of a first form of a semiconductor memory device (flash memory) according to the present invention. As is apparent from FIG. 1, the semiconductor memory device of the present embodiment is different from the semiconductor memory device of the related art shown in FIG. 2 in that a matching circuit 120 for comparing an input address with a defective address and a redundant row decoder 130 are provided. It has been added configuration. Here, the row address buffer 101, the row decoder 102, the column address buffer 103, the column decoder 104, and the data I / O in the semiconductor memory device of the present embodiment.
The buffer 105, write circuit 106, sense amplifier 107, negative voltage generation circuit 108, and source power supply circuit 109 are row address buffers in the semiconductor memory device of the related art of FIG.
111, row decoder 112, column address buffer 113, column decoder 114, data I / O buffer 115, write circuit 11
6, which corresponds to the sense amplifier 117, the negative voltage generation circuit 118, and the source power supply circuit 119.

The operation of this embodiment will be described. First, the matching circuit is used at the time of reading and writing.
When the defective address stored in 120 and the input address match, the output signal from the matching circuit 120 is input to the row address buffer 101 and the redundant row decoder 130, and the row decoder 102 is deselected. The redundant row decoder 130 is set to the selected state. This allows the redundant cell to be accessed instead of the defective cell. At the time of erasing, the erasing control signal E becomes the high level "H" and is input to the column address buffer 103, the row address buffer 101, the row decoder 102, the matching circuit 120, and the redundant row decoder 130.

First, when there is no defective cell transistor (defective cell) in the cell array (when there is no redundancy), the same operation as described above is performed. That is, the redundancy control signal RED from the coincidence circuit 120 has a logic that does not cause any circuit to operate redundantly.

Next, consider the case where a defective cell exists on a certain lead wire and the address of the defective cell is stored in the coincidence circuit 120. In the present embodiment, the total number of word lines is 2 ⁿ , the size of the erase block is 2 ^m word lines, and 2 ^k spare word lines are provided as an example. . Considering writing and reading, the required number of bits of the defective address storing memory element in the coincidence circuit 120 is nk, and the number of word lines in the erase block is 2 ^m , so that the erase block is The number of bits of nm addresses is required for selection. At the time of erasing, nm word line block selection addresses are input in order to select a word line block composed of a certain 2 ^m lines. This input address is compared with the n-m higher-order addresses of the n-k address bits stored in the matching circuit 120, and if this input address is stored with the n-m address stored. Are coincident with each other, it means that 2 ^k word line blocks including a defect are present in the erase block.

2 above^m Word line block composed of books
2 with defects^k Word line block composed of books
The address information indicating the lock is stored in the matching circuit 120.
Of the remaining address information indicated by mk
Will be indicated by. That is, the semiconductor memory of this embodiment is
The storage device is designated by m−k addresses 2^m Book wa
2 in the line block^k Word line block made up of books
Are deselected by the row decoder 102, and n
-Redundant when erasing when m addresses match.
Select row decoder 130 to 2^m Erasing book composed of books
2 of the locks ^k Of the word line block configured by this unit
Erase redundancy can be performed.

FIG. 12 is a circuit diagram showing an example of the row address buffer 101 in the semiconductor memory device of FIG. 1, FIG. 13 is a circuit diagram showing an essential part of an example of the row decoder 102, and
FIG. 14 is a circuit diagram showing an example of the coincidence circuit 120.

As shown in FIG. 12, the erase control signal E is input to the lower m of the n row address buffers 101 as a whole, so that 2 ^m word lines are completely erased at the time of erasing. Will be selected. Here, the redundancy control signal R is added to any one of the m address buffers.
ED is input, so that the word line WL is not selected when the redundancy control signal RED is at the high level "H" (when the defective address and the input address match) during writing and reading. There is.

Here, the redundancy control signal RED is an output signal of the matching circuit 120 shown in FIG.
Includes a fuse for address storage necessary for selecting 2 ^k word line blocks from 2 ⁿ word lines, and a fuse (RUSE) for storing a redundant use signal. Since the erase control signal E is at the low level "L" except at the time of erasing, the redundancy control signal RED does not become the high level "H" unless the information of all fuses and the input address match, but at the time of erasing, , Address A _RBm + 1 to A
_The redundancy control signal RED becomes the high level "H" only when _RBn (that is, the upper n-m addresses) match. Also, the addresses A _{RBk + 1} to A _RBm (m−k addresses)
The data of the fuse is directly taken out and input to the NAND gate shown in FIG. As a result, it is possible to deselect a block composed of 2 ^k word lines out of 2 ^m word lines. At the same time, the redundancy control signal RED is input to the redundancy row decoder to select a spare word line, and any word line block composed of 2 ^{k of} erase blocks composed of 2 ^m word lines is selected. Can be made redundant.

By the way, in the flash memory,
Yield is often reduced due to defects caused by excessive erasing.
In the configuration of the semiconductor memory device described above, since the bit line is shared by the spare cell and the real cell, redundancy replacement cannot be performed only by replacing the overerased cell with the spare cell. Specifically, for example, in FIG. 11, assuming that the memory cell (cell transistor) MC ₁₁ is an overerased cell, when the overerased cell MC ₁₁ is replaced with a redundant cell MCR ₁₁ , the word line WL ₁ is at a low level “L”. However, since the over-erased cell MC ₁₁ carries a current, this bit line B
This is because the cell data (data “0”) existing on L ₁ cannot be read normally. However,
This problem can be easily solved by writing data "0" to the overerased cell before making it redundant, that is, injecting electrons into the floating gate, and then making redundancy.

In the over-erased cell, since the floating gate is positively charged, the current at the point A in the write characteristic curve of the cell shown in FIG. 10 further increases, and writing cannot be performed. become.
To solve this, the gate level is controlled at the time of writing and the current of the cell transistor near the point A is set to the writing circuit.
It is necessary to control so as not to exceed the load curve of 106. This can be easily achieved by operating the word line WL in a continuous pulse shape at the time of writing. That is, when the word line WL is operated in a continuous pulse manner, in the write characteristic curve of FIG. 10, the word line WL changes from the low level “L” to the high level “H” or from the high level “H” to the low level. Level "L"
The curve C (characteristic curve of the broken line in FIG. 10) can be realized without fail during the transition to, and writing is possible regardless of the state of the floating gate.

FIG. 15 is a circuit diagram showing an essential part of an example of the row decoder 102 in the semiconductor memory device of FIG.
FIG. 9 is a diagram showing a circuit configuration corresponding to an input portion B in the row decoder 112 of the semiconductor memory device of the related art described with reference to FIG. Here, the signal φW supplied to the input of the NOR gate shown in FIG. 15 has a pulse-like waveform shown in FIG. As a result, the potential of the node N ₂ in FIG. 5 can be continuously oscillated between 0 volt and the write potential, and continuous pulses can be applied to the word line WL. Here, the writing process and the erasing process are generally executed while performing verification, and these verifications are generally executed by applying a verify voltage to the word line and reading the data. Is. Further, it is desirable that the verify voltage is constant even if the ambient environment of the device changes (the power supply voltage or the like changes). For that purpose, it is created by boosting with reference to the reference potential (Vss) of the device. Is effective. A circuit that generates an intermediate voltage for the word line may be used instead of applying a pulse.

FIG. 17 is a circuit diagram showing an example of the verify voltage generating circuit 150 in the semiconductor memory device of FIG.
It is a circuit for generating a verify voltage applied to the node N ₁ in the row decoder circuit 112 (102) shown in FIG.

As shown in FIG. 17, the verify voltage generating circuit 150 is composed of a clamp circuit 151, an oscillating circuit 152, and a boosting circuit 153. Clamp circuit 15
In 1, the transistors T ₁₃ and T ₁₄ are circuits that determine the clamp voltage, and P-channel and N-channel MOS transistors are diode-connected in series. Here, in the CMOS process, since the respective channel regions are formed in the same step, the shift of the threshold value of each transistor is canceled out complementarily, and as a result, a stable clamp voltage is obtained.

The transistor T ₁₅ is an N-channel type MOS transistor having a threshold value of about 0 volt, and is an oscillating circuit.
The clamp voltage is supplied to the 152. The booster circuit 153 has a low power supply voltage (ground voltage) V
It operates based on ss, and as a result, the verify voltage (potential of the node N ₁ ) can have a stable value without being affected by the power supply voltage. Furthermore, erase verify and write verify have different voltage values.
The number of transistor stages of the clamp circuit 151 (T ₁₃ , T ₁₄ ;
..) can be changed to easily generate a clamp voltage having a predetermined potential. Here, the reference symbol V _R is a signal that becomes a high level “H” during verification. Each verification can also be realized by changing the determination current of the sense amplifier.

FIG. 18 is a circuit diagram showing an example of the sense amplifier 107 in the semiconductor memory device of FIG. As shown in the figure, the sense amplifier 107 includes P-channel transistors T _L1 and T _L2 as load transistors. Here, the current supply capacity of each transistor is T _L1
> T _L2 . The read mode of the flash memory has three modes of erase verify, normal read, and write verify. The size of the load transistor (total) in these three modes needs to satisfy the relationship of erase verify> normal read> write verify. Note that FIG.
The above relationship in the above circuit is as follows: Erase verify: V _R1
= _VR2 = "L", during normal read: _VR1 = "L", _VR2 =
"H", during write verification: _VR1 = "H", _VR2 =
It can be realized as "L".

FIG. 19 is a circuit diagram showing an example of a logic circuit for generating the control signals V _R1 and V _R2 supplied to the sense amplifier of FIG. In the figure, reference symbol Wv indicates a write verify signal and Ev indicates an erase verify signal. When this configuration is adopted, there is an advantage that the power supply circuit of the row decoder necessary for generating the verify voltage can be simplified. Thus, according to this configuration,
By adding a logic circuit for load control, it becomes possible to apply to erase verify in a flash memory.

Next, a second mode of the semiconductor memory device according to the present invention will be described with reference to FIGS.

FIG. 20 is a block circuit diagram showing an example of the redundant circuit 210 in the conventional semiconductor memory device corresponding to the second form of the semiconductor memory device according to the present invention. In the figure, reference numeral 211 indicates a fuse, which is an element (defective address designating means) for storing a defective address, and which is at a high level "H" of the address depending on whether or not the fuse is cut.
Alternatively, the low level "L" is stored.
Further, reference numeral 214 indicates an address comparison circuit for comparing and judging whether or not the information of the fuse 211 and the external input address match. When they match, for example, the address match signal is set to a high level "H". It is like this.

FIG. 21 is a diagram showing an example of the configuration of the conventional redundant circuit shown in FIG. In the configuration example of the redundant circuit 2100 shown in the figure, a plurality of redundant circuits 210 shown in FIG.
Redundant signals are created by outputting those outputs through a NAND gate and an inverter. Only when each input address matches the information of the fuses (211) in all the redundant circuits 210, the redundant signal is set to the high level "H" and the data of the redundant cell is read out.

FIG. 22 shows a conventional redundant circuit 2100 shown in FIG.
It is a block diagram which shows an example of the semiconductor memory device which used. In the overall configuration diagram of the semiconductor memory device shown in FIG.
When a redundancy signal is output from the redundancy circuit 2100, the real cell selection circuit 217 prohibits reading of the real cell 218, and instead, the redundancy cell selection circuit 215 reads the redundancy cell 216. As a result, the defective real cell portion is replaced with the redundant cell. Here, in FIG. 22, reference numeral 219 indicates a data read circuit for reading the data of the selected cell transistor (memory cell) of the redundant cell 216 or the real cell 218.

In the above-mentioned conventional method, one address comparison circuit is required for one fuse, and therefore, in order to replace a large number of defective portions, as many fuses and address comparison circuits as the replacement number are required. . as a result,
In the conventional redundant circuit, the chip area is increased and the cost is increased.

As described above, in the conventional redundancy system in the semiconductor memory device, there is a problem to be solved that the chip area increases and the cost increases when the number of replacements increases due to the increase in the number of circuits. .

FIG. 23 is a block circuit diagram showing an embodiment of the redundant circuit in the second mode of the semiconductor memory device according to the present invention. As is apparent from the figure, in the redundant circuit 200 of this embodiment, the transistor T _A and the fuse 20 are used as the fuse 211 in the redundant circuit 210 of FIG.
And 1A, a transistor T _B and the fuse 201B provided,
External input address An (/ An: Inverted signal of address An)
The fuses 201A and 201B are selected according to the logic of. Here, the address An (/ An) indicates an upper address indicating a block selection address for selecting a real cell divided into a plurality of blocks. in this way,
According to the redundancy circuit 200 of this embodiment, one address comparison circuit 214 is shared by the two fuses 201A and 201B, so that the number of address comparison circuits 214 as a whole is reduced, and the chip area and cost are increased. It is designed to suppress.

FIG. 24 is a diagram showing configurations of the real cell 208 and the redundant cell 206 in the semiconductor memory device to which the redundant circuit of the present invention shown in FIG. 23 is applied. As shown in the figure, the real cell 208 includes, for example, a first real cell block 208A whose block selection address An is selected at a low level "L" and a block selection address An which is selected at a high level "H" (/ An is constituted by the second real cell block 208B selected at the low level "L"). The redundant cell 206 also includes, for example, a first redundant cell block 206A for redundancy of the first real cell block 208A,
And, it is constituted by a second redundant cell block 206B for making the second real cell block 208B redundant.
As a result, the divided real cell blocks 206A, 206
If an address common to B (eg, A _n-1 , A _n-2 , ...) Includes a defective cell, in the block designated by the logic of the block address An, a predetermined range of real cells including the defect is present. Are replaced with redundant cells.

FIG. 25 is a block diagram showing an example of a semiconductor memory device using the redundant circuit of the present invention shown in FIG. In the overall configuration diagram of the semiconductor memory device shown in FIG.
When the redundant signal is output from the redundant circuit 200, the real cell selection circuit 207 prohibits the reading of the real cell 208, and the redundant cell selection circuit 205 instead reads the redundant cell 206. Here, as is clear from comparison of the block diagrams of the semiconductor memory devices of FIGS. 22 and 24, in the semiconductor memory device of this embodiment, the address input (block selection address An) is also supplied to the redundant cell selection circuit 205. Redundant cell 206 corresponding to fuses 201A and 201B selected by the logic of address An in redundant circuit 200
It is designed to select A, 206B. That is, the block address An is input to the redundant cell selection circuit 205, and the redundant cells 206A and 206B corresponding to the real cell blocks 208A and 208B selected by the block address An are selected to perform the redundancy processing. ing. Incidentally, FIG.
In the figure, reference numeral 209 indicates a data read circuit for reading the data of the selected cell (memory cell) of the redundant cell 206 or the real cell 208.

As described above, the address comparison circuit 204 is commonly used for a plurality of redundant cells 206A and 20B, and the defective real cell portion is used as a redundancy cell as in the conventional semiconductor memory device shown in FIG. Can be replaced. Here, in the above description, the 1-bit block selection address An is configured to select one of the real cells divided into two. However, for example, the 2-bit block selection address An, A _n-1 The configuration may be such that one of the divided real cells is selected and one of the redundant cells divided into four is selected.

FIG. 26 is a block circuit diagram showing another embodiment 200 'of the redundant circuit in the second form of the semiconductor memory device according to the present invention. In the figure, reference numeral 220 is a cell selection circuit, 221, 223 are redundant information storage cell arrays, 222, 224.
Indicates a read circuit.

As shown in FIG. 26, the redundant circuit 200 'of this embodiment has two sets of redundant information storage cell arrays 221, 22.
3 and read circuits 222 and 224.

The redundant information storage cell arrays 221 and 223 are composed of, for example, a plurality of nonvolatile memory cell transistors such as EPROMs, and are used for writing data to a defective address in an input address from the outside. The cell selection circuit 220 is a cell array for storing redundant information.
221,223 can be selected by inputting an address. The outputs of the read circuits 222 and 224 are AND gates 225.
The signals are output as four redundant signals via A, 225B, 225C, 225D and inverters 226A, 226B. Here, in this embodiment, data is read out in parallel from the two redundant information storage cell arrays 221 and 223 in 2 bits, and the defective cells at four locations can be replaced with redundant cells. However, it goes without saying that the data of 3 bits or more can be read in parallel.

FIG. 27 is a block circuit diagram showing another embodiment 200 "of the redundant circuit in the second form of the semiconductor memory device according to the present invention. FIG. 28 shows the redundant circuit of the present invention shown in FIG. It is a block diagram which shows an example of the used semiconductor memory device.

In the redundant circuit 200 'shown in FIG. 26, a method of reading a plurality of bits (2 bits) in parallel has been shown, but only a single bit is read and a plurality of defective portions in the real cell 208 are replaced by the redundant cell 206. You can also

In the redundant circuit 200 "shown in FIG. 27, a single bit is read by the address input and the redundant signal is output by the logic. And, FIG. 28 is shown.
27 shows a configuration of a semiconductor memory device using the redundant circuit 200 "shown in FIG. 27. Here, the redundant signal is supplied from the redundant circuit 200" to the redundant cell selection circuit 205 'and the real cell selection circuit 207'. A part of the address input (real cell block selection address An) is supplied. As a result, which of the plurality of redundant cells is to be used for redundancy of the real cell is determined.

Next, a third mode of the semiconductor memory device according to the present invention will be described with reference to FIGS.

By the way, in recent years, a nonvolatile semiconductor memory device capable of electrically writing / erasing information, in particular, a so-called flash memory has been proposed which has a mode in which writing or erasing is automatically performed by an internal algorithm. Has been done.

In such a flash memory,
For writing (or erasing), first, a write pulse is applied, then a read process (verify) is performed, and if the read depth does not reach a sufficient write depth, the write pulse is applied again. The method of doing is applied. The maximum number of times the write pulse is applied (the number of times of verification) is specified in the specifications, and all this control is controlled from the outside.

In recent flash memories, it has been proposed that this algorithm is provided internally to automatically perform writing or erasing. In this automatic writing and erasing method, the maximum writing (erasing) time is presented to the user.

However, for example, in a semiconductor memory device (flash memory) shipping test, it is not possible to guarantee deterioration of the number of rewritings due to an increase in the number of rewritings only with the maximum time, and a semiconductor memory device that has passed the shipping test cannot be guaranteed on the user side. It may become defective.

Therefore, in the third embodiment of the semiconductor memory device according to the present invention, in addition to the maximum number of times on the user side, the rewriting time due to deterioration is expected to increase during a test on the manufacturing side (for example, a shipping test). By testing with the maximum number of times, the purpose is to guarantee the maximum number of times on the user side.

FIG. 29 is a flow chart showing an example of the internal write algorithm which is the basis of the third embodiment of the semiconductor memory device according to the present invention.

First, when the writing process is started, a writing pulse is applied in step S301, and the process proceeds to step S302 to perform verification. That is, in step S302, reading is performed,
It is determined whether the sufficient writing depth has been reached. If it is determined in this step S302 that the sufficient writing depth has been reached, the writing process ends,
If it is determined that the sufficient writing depth has not been reached, the process proceeds to step S303 and it is determined whether or not the number of pulses has reached N. That is, in step S303, it is determined whether or not the number of verification times has reached a predetermined N, and if it has not reached N, step 30
The process of 1 and step S302 is repeated, and if N is reached, writing fails. That is, even if the write pulse is applied N times, sufficient write processing cannot be performed on the cell transistor.

In the third aspect of the present invention, for example,
The shipping test is performed with the maximum number of write pulse application times being n, which is smaller than the normal N, and the shipping test is performed under more severe conditions than usual. As described above, according to the third aspect of the present invention, the maximum number of times N is guaranteed on the user side by performing the shipping test with the maximum number of times n (n <N) that is expected to increase the rewriting time due to deterioration. be able to.

FIG. 30 is a block diagram showing an embodiment of the third mode of the semiconductor memory device of the present invention. In the figure, reference numeral 311 is a write control circuit, 312 is a write pulse generation circuit, 313 is a cell array, 314 is a pulse counter, 3
Reference numeral 15 is a switch unit, 316 is a stop signal generation circuit, and 317 is a high voltage detection circuit.

The write control circuit 311 receives an external control signal and a write stop signal, controls the write pulse generation circuit 312, and performs a write process to each cell transistor of the cell array 313. The output (write pulse) of the write pulse generation circuit 312 is supplied to the cell array 313 and also to the pulse counter 314 to count the number of applied write pulses (the number of verifications). The pulse counter 314 has a wiring for directly inputting to the input of the NAND circuit and a wiring for the output of the inverter in advance so that the count number can be easily added. The wiring may be selectively connected.

The switch unit 315 has a normal maximum pulse application number N and, for example, the maximum pulse application number n in the shipping test.
(N> N), and the stop signal generation circuit 316 supplies the write stop signal WS to the write control circuit 311 according to the selected maximum pulse application number N or n. Here, the switching operation of the switch unit 315 is performed according to the switch control signal SC which is output by detecting whether or not the external high voltage is applied from the high voltage detection circuit 317.

FIG. 31 is a diagram showing an example of a circuit of a main part in the semiconductor memory device of FIG. 30, and FIG. 32 is a timing chart for explaining the operation of the circuit of FIG. Here, in FIGS. 31 and 32, reference numeral QC0i represents each stage number output of pulse count.

As shown in FIGS. 31 and 32, the stop signal WS corresponding to the normal maximum pulse application number N
(N) is created from the pulse count outputs QCO2, QCO3, QCO4, and, for example, the maximum number of pulse application times n in the shipping test.
The stop signal WS (n) corresponding to is generated from the pulse count outputs QCO0, QCO1, QCO2. Here, when the output (switch control signal) SC of the high voltage detection circuit (EWCMGN) 317 is at the low level “L”, that is, when the high voltage is not applied, the stop corresponding to the normal maximum pulse application number N The signal WS (N) is output at the 21st timing of the pulse signal QCO0. On the contrary, when the output SC of the high voltage detection circuit 317 is at the high level “H”, that is, when the high voltage is applied to the predetermined terminal,
For example, the stop signal WS (n) corresponding to the maximum pulse application number n in the shipping test is output at the fourth timing of the pulse signal QCO0.

In the above description, for example, the stop signal W
The number of application of the write pulse until S is output is changed between the normal time (when used by the user) and the shipping test. However, instead of the number of application of the write pulse,
The writing pulse width may be changed. That is, for example, in the shipping test, the pulse width of the write pulse may be shortened so that the condition becomes stricter than usual. Also in this case, for example, the pulse width of the write pulse in the shipping test may be shortened by detecting application of a high voltage to a predetermined terminal. Furthermore, although the above description has been given of the writing process, the same applies to the erasing process.

As described above, according to the third embodiment of the semiconductor memory device of the present invention, the allowable value for writing or erasing information in the memory cell in the internal algorithm is made variable so that, for example, the shipping test is passed. It is possible to prevent the semiconductor memory device from becoming defective on the user side.

Next, a fourth mode of the semiconductor memory device according to the present invention will be described with reference to FIGS. 33 to 36.

FIG. 33 shows a semiconductor memory device according to the present invention.
Memory cell (MC ₀) Indicates the electrical
Bulk erase type nonvolatile semiconductor memory device (flash memory)
Cell transistor (memory cell MC₀)
It is a figure for explaining. As shown in the figure, the cell
The transistor is isolated from any area between the source and drain.
An edged floating gate FG is provided to
Control gate CG on top of starting gate FG
Formed and configured.

First, at the time of reading, the gate voltage Vg is set to the power supply voltage Vcc, the drain voltage Vd is set to about 1 volt, and the source voltage Vs is set to the ground level Vss.
As a result, it is determined whether the data written in the cell transistor is "1" or "0" depending on whether or not the drain current flows.

At the time of writing, the drain region DD
A drain voltage Vd applied to the source is a high voltage (normally Vcc <high voltage <Vpp), a gate voltage Vg applied to the control gate CG is a writing voltage Vpp (about +10 V), and a source applied to the source region SS. With the voltage Vs set to the ground level Vss, electrons are injected from the drain terminal (DD) to the floating gate (FG) to write data "0". Here, with the recent decrease in the voltage for writing, it is becoming more and more necessary to efficiently apply the voltage for writing to the drain terminal.

FIG. 34 is a block circuit diagram showing an example of a semiconductor memory device (flash memory) as a related technique corresponding to the fourth embodiment of the semiconductor memory device of the present invention. In the figure, reference numeral 411 is a row address buffer, and 412.
Is a row decoder, 413 is a column address buffer, 414 is a column decoder, 415 is a buffer circuit, 416 is a write voltage supply transistor, 417 is a sense amplifier, and 418 is a bus line. Reference numeral BL is a bit line,
WL indicates a word line, / WD indicates write data (inversion level), and W indicates a write control signal.

In the semiconductor memory device shown in FIG. 34, at the time of reading, one word line WL and one bit line BL are selected by the row address and column address, and the selected memory cell MC ₀ (cell Whether or not the content written in the selected cell transistor is data "1" or data "0" is determined and output depending on whether or not a current flows through the transistor.

At the time of data writing, the write control signal W causes the selection signal of each word line and bit line to be the write voltage Vpp. At this time, write data /
When WD is input, the transistor 416 is turned on, and the write voltage Vpp (voltage lower by the threshold voltage of the transistor 416) is applied to the bus line 418 (drain terminal of the cell transistor MC ₀ ). Here, in the flash memory (semiconductor memory device) shown in FIG. 34, for example,
Since it was possible to use a sufficiently high voltage as the write voltage Vpp, the write voltage supply transistor
416 could be composed of N-channel MOS transistors. That is, when an N-channel MOS transistor is used as the write voltage supply transistor 416, the write voltage Vpp is lowered by the threshold voltage of the N-channel MOS transistor and applied to the drain of the cell transistor MC _0. Become.

By the way, in recent years, even when a flash memory is used, it is necessary to lower the write voltage in response to the demand for a single 5 volt power supply. Thus, for example, when the flash memory is driven by a single 5 volt power supply, the threshold voltage of the write voltage supply transistor 416 causes the supply voltage to be lower than the write voltage Vpp, so that an efficient write voltage can be obtained. Supply to the drain terminal becomes difficult.

According to a fourth aspect of the semiconductor memory device of the present invention, by preventing the write drain voltage from decreasing due to the threshold voltage of the write voltage supply transistor, good data can be obtained even when the write voltage is lowered. The purpose is to realize the writing of.

FIG. 35 is a block circuit diagram showing an embodiment of the fourth mode of the semiconductor memory device of the present invention. As is clear from comparison with the semiconductor memory device as the related art shown in FIG. 34, in the semiconductor memory device of the present embodiment, the write voltage supply transistor is constituted by the P-channel type MOS transistor 406 and the buffer circuit 405 is provided. The write data supplied is a positive logic signal WD. Here, the row address buffer 401 of the present embodiment shown in FIG.
The row decoder 402, the column address buffer 403, the column decoder 404, and the buffer circuit 405 include a row address buffer 411, a row decoder 412,
It corresponds to the column address buffer 413, the column decoder 414, and the buffer circuit 415. Incidentally, reference numeral B
L is a bit line, WL is a word line, and W is a write control signal.

In the semiconductor memory device shown in FIG. 35, at the time of reading, one word line WL and one bit line BL are selected by a row address and a column address, and sense amplifier 407 selects the selected memory cell MC ₀ (cell Whether or not the content written in the selected cell transistor is data "1" or data "0" is determined and output depending on whether or not a current flows through the transistor.

At the time of data writing, the write control signal W causes the selection signal of each word line and bit line to be the write voltage Vpp. At this time, write data W
The buffer circuit 405 converts D into a signal at the level of the write voltage Vpp. When the gate signal of the write voltage supply transistor 406 becomes low level "L", the transistor 406 turns on and the write voltage Vpp is reached.
Are supplied to the bus line 408. Here, in the flash memory (semiconductor memory device) of the present embodiment shown in FIG. 35, since the write voltage supply transistor 406 is composed of a P-channel type MOS transistor, a write applied to the source of the transistor 406. Voltage Vpp
Can raise the potential of the bus line 408 to the vicinity of the write voltage Vpp without being dropped by the threshold voltage of the transistor 406, and efficiently write the voltage to the drain terminal of the cell transistor MC _0. Vpp can be applied. Therefore, for example, even when the flash memory is used with a single 5 volt power supply, it is possible to effectively perform the data writing process by using the lowered writing voltage Vpp.

FIG. 36 is a circuit diagram showing an essential part of another embodiment of the fourth mode of the semiconductor memory device of the present invention. The write voltage supplying transistor and the buffer in the semiconductor memory device of the related art shown in FIG. It is a circuit diagram which shows the part corresponding to a circuit.

As shown in FIG. 36, in this embodiment, the write voltage supply transistor 426 is replaced by the one shown in FIG.
Like the semiconductor memory device of the related art shown in, it is composed of N-channel type MOS transistors. However, in FIG.
Circuit for semiconductor memory device of related art shown in
417 is an N channel type MOS transistor 4251,4252,42
53, inverters 4255, 4256, 4257, and a bootstrap circuit with a capacity 4253.
Here, in the bootstrap circuit shown in FIG. 36, when the write data WD changes from the high level “H” to the low level “L”, the gate of the transistor 4251 is at the high level “H”.
Then, the gate of the transistor 4252 becomes low level “L”, and the potential of the node N ₄₀ rises.
At this time, the gate of the transistor 4251 is further boosted by the capacitance 4253, and finally rises to a level of about Vpp + Vcc. If this potential is applied to the gate of the write voltage supply transistor 426, the bus line (418)
Will rise to almost the writing voltage Vpp.

As a result, the data signal boosted to the write voltage Vpp or higher is applied to the gate of the write voltage supply transistor 426 composed of the N-channel type MOS transistor, and the write voltage Vpp is applied to the bus line.
It becomes possible to effectively perform the data write process by using the write voltage Vpp that has been lowered by supplying a voltage equivalent to pp.

As described above, according to the fourth embodiment of the semiconductor memory device of the present invention, the write drain voltage is lowered by preventing the write drain voltage from decreasing due to the threshold voltage in the write voltage supply transistor. Even in the case of writing, good data writing can be realized.

Next, a fifth mode of the semiconductor memory device according to the present invention will be described with reference to FIGS. 37 to 45.

FIG. 37 is a block circuit diagram showing an example of a conventional semiconductor memory device (flash memory) corresponding to the fifth mode of the semiconductor memory device according to the present invention. In the figure, reference numeral 512 is a row decoder, 514 is a column decoder, 517 is a sense amplifier, and 519 is a source power supply circuit. Reference numeral MC is an N channel MIS.
Memory cell composed of transistors Transistor (memory cell), WL is word line, BL is bit line, and
SL indicates a source line. Where source power circuit
The reference numeral 519 is connected to the source of each memory cell transistor in the memory cell array via the source line SL so that it can be electrically erased collectively. The memory cell MC is similar to that shown in FIG.

FIG. 38 is a circuit diagram showing the configuration of the row decoder 512 in the semiconductor memory device of FIG. 37, FIG. 39 is a circuit diagram showing the configuration of the column decoder 514, and FIG. 40 is a bit line transfer gate 5145 in the column decoder 514. 3 is a circuit diagram showing the configuration of FIG.

As shown in FIG. 38, the row decoder 51
Reference numeral 2 denotes a power supply circuit 5121, gates RG _{1 to} RGn to which a row address is supplied, the gates RG _{1 to} RGn and a power supply circuit 5121.
A transistor 5122 provided between the power supply circuit 5121 and the low potential power supply Vss (ground level GND: 0 volt), and an inverter (transistors 5123, 5124) for controlling the level of the word line WL. I have it. Thus, for example, all the row address input is high level "H" and turned in response to the address gate RG ₁ to Rgn are turned on word lines (selected word line) WL,
Output (Vcc) of power supply circuit 5121 via transistor 5123
Is applied to the other non-selected word lines WL,
A low potential voltage (Vss: 0 volt) is applied via 5124.

As shown in FIG. 39, the column decoder
Reference numeral 514 denotes a power supply circuit 5141, gates CG _{1 to} CGm to which a column address is supplied, the gates CG _{1 to} CGm and a power supply circuit.
A transistor 5142 provided between the power supply circuit 5121 and the low potential power supply Vss, and a transistor 5142 provided between the power supply circuit 5121 and the low potential power supply Vss to control the bit line transfer gate 5145 (transistors 5143, 514).
4) is equipped. As a result, for example, all of the input column addresses become high level "H", and the gate CG ₁
The bit line (selected bit line) BL corresponding to the address at which .about.CGm is turned on is connected to the sense amplifier 517.

Here, as shown in FIG. 40, a plurality of bit line transfer gates 51451 to 5145m are connected to the bus line.
It is connected to one sense amplifier 517 via (BUS), and only one selected bit line (selected bit line) in the bit line transfer gates 51451 to 5145m is connected to the sense amplifier 517. Then, the contents of the memory cell MC located at the intersection of the selected word line and the selected bit line are output via the sense amplifier 517.

By the way, the flash memory is capable of electrically erasing all bits collectively, and when performing the erasing collectively, generally all cell transistors (memory cells MC) are erased because of the simplicity of the circuit technology. At the same time, the same erase operation is performed. Then, this erase operation is repeated until all cell transistors are erased. However, in the cell array, cell transistors that are relatively easy to erase and cell transistors that are relatively difficult to erase are mixed for statistical reasons. Therefore, if all bits are collectively erased by the method described above, if the characteristic difference between the cell transistor that is easy to erase and the cell transistor that is difficult to erase is very large, the erase operation for the cell transistor that is easy to erase is performed. Will be done more than necessary. Here, the characteristic difference of the cell transistors can be relatively easily appeared due to fluctuations in a wafer process, stress due to repeated writing / erasing for a long time, and the like.

Writing and erasing operations for the cell transistor of the flash memory are usually performed by injecting and releasing charges to and from the floating gate of the cell transistor. Therefore, in the memory cell MC on which the erase operation is performed more than necessary as described above, the charge having the polarity opposite to that at the time of writing is apparently injected into the floating gate (the floating gate is positively charged). become. Such a state is called an overerased state.

In the case of a non-volatile semiconductor memory device (flash memory), the cell array generally has a structure called NOR type. In this NOR type nonvolatile semiconductor memory device, the drains of the cell transistors (N-channel type MIS transistors) are commonly connected to each bit line, and are uniformly biased, and only to the gates of the selected cell transistors. Bias (positive voltage)
And a gate of an unselected cell transistor is not biased (0 volt) so that a predetermined cell transistor (memory cell) is selected. The sources of all cell transistors are grounded via the source power supply circuit 519. Here, since the enhancement type MIS transistor (N-channel type MIS transistor) is used as the cell transistor, no current flows through the non-selected cell transistor, and only the selected cell transistor responds to the amount of charge in the floating gate. Current may or may not be applied.
Data "0" and data "1" are assigned according to the current flowing through the selected cell transistor.

In the flash memory, when the above-mentioned over-erasure occurs in the enhancement type cell transistor, the characteristics of the cell transistor are apparently changed to the depletion type. When a NOR-type cell array is used, the non-selected cell transistors do not flow a current when the gate is not biased, but the cell transistors that have been over-erased have apparently depletion-type characteristics. For the sake of illustration, current flows even in a non-selected cell transistor. Therefore, for example, even if the selected cell transistor does not pass the current, the unerased unselected cell transistor passes the current, so that the data “0” and the data “1” are erroneously determined. There is a problem that it may occur.

A fifth form of the semiconductor memory device according to the present invention aims to accurately read data even if there is a cell transistor in which overerasure has occurred.

FIG. 41 is a block circuit diagram showing an embodiment of the fifth mode of the semiconductor memory device (flash memory) according to the present invention. In the figure, reference numeral 502 is a row decoder, 504 is a column decoder, 507 is a sense amplifier, and 509 is a source power supply circuit. Here, the semiconductor memory device of this embodiment is basically the same as the semiconductor memory device described with reference to FIG. 37, and the description thereof is omitted, but the configuration of the row decoder 502 is different.

FIG. 42 is a circuit diagram showing a structure of row decoder 502 in the semiconductor memory device of FIG. As shown in the figure, the row decoder 502 of the present embodiment, the positive power source circuit 5021 for generating a predetermined positive voltage, the gate RG ₁ to Rgn the row address is supplied, the gate RG ₁ to Rgn and positive power supply A transistor 5022 provided between the circuit 5021 and
Negative power supply circuit 5025, and positive power supply circuit 5021 and negative power supply circuit
Inverters (transistors 5023 and 5024) provided between the inverters 5050 and 5025 for controlling the level of the word line WL are provided. Thus, for example, all the row address input is high level "H" and turned in response to the address gate RG ₁ to Rgn are turned on word lines (selected word line) WL,
The output of the positive power supply circuit 5021 (Vc
c) is applied, and the output (negative voltage) of the negative power supply circuit 5025 is applied to the other unselected word lines WL via the transistor 5024. As a concrete circuit of the negative power supply circuit 5025, it is needless to say that the negative voltage generation circuit 118 in the semiconductor memory device as a related technique shown in FIG. 5 can be applied and configured.

Here, when the output of the negative power supply circuit 5025 is applied to the gate of the depletion type cell transistor MC which causes overerasure, the overerased cell transistor MC is deselected. It has a voltage that prevents current from flowing. That is, the negative power supply circuit 50
The output of 25 is a negative voltage such that the gate voltage of the depletion type N-channel MIS transistor (over-erased cell transistor) becomes equal to or lower than the threshold voltage. As a result, even if there is an over-erased cell transistor in the selected bit line, the contents written in the cell transistor selected by the word line can be accurately output via the sense amplifier 507. Become.

FIG. 43 is a block circuit diagram showing another embodiment of the fifth mode of the semiconductor memory device according to the present invention. In the figure, reference numeral 5221 is a first row decoder corresponding to the row decoder 502 in FIG. 41, and 5222 is a row decoder in FIG.
The second row decoder for applying a voltage higher than the level of the selected bit line to the source line SL corresponding to the function of the source power supply circuit 509 and the unselected word line WL in FIG. Here, the configurations of the column decoder 524, the sense amplifier 527 and the like are similar to those shown in FIG.

In the semiconductor memory device of this embodiment, the first
Row decoder 5221 of the selected word line WL at the time of reading
A normal voltage Vcc is applied to the selected word line WL
The memory cell (cell transistor) MC connected to is selected. The second row decoder 5222 applies a low-potential power supply voltage Vss: 0 volt to the source (SWL) of the cell transistor connected to the selected word line, and also applies to the unselected word line at the time of reading. A voltage higher than the level (drain voltage) of the selected bit line is applied to the sources of all the connected cell transistors. As a result, when the cell transistors are in the non-selected state, the gate voltage becomes lower than the source voltage even for the cell transistors that are in the over-erased state due to the batch erasing, so that they can be cut off (non-selected state).
Here, the voltage applied to the source of the memory cell connected to the non-selected word line at the time of reading may be set to the same voltage as the level of the selected bit line. That is, even if a channel is generated by over-erasing, current does not flow unless there is a potential difference between the drain and the source, so the unselected over-erasing cell transistor does not affect the read operation. .

FIG. 44 is a first row decoder 5221 and a second row decoder 5222 in the semiconductor memory device of FIG.
45 is a circuit diagram showing an example, and FIG. 45 is a circuit diagram showing a part of the second row decoder of FIG. 44.

As shown in FIG. 44, the first row decoder 5221 includes a power supply circuit (Vcc) 52211, a NAND gate 52212 to which a row address is supplied, and an inverter 52213.
The second row decoder 5222 includes a power supply circuit (Vcc) 52221, a NAND gate 52222 to which a row address is supplied, inverters 52223 and 52224, and a power supply circuit 5225.
It is composed of. Here, the power supply circuit 52225 is for supplying a voltage higher than the level (drain voltage) of the selected bit line applied to the source of the cell transistor connected to the non-selected word line at the time of reading. FIG. 45 shows an example of the circuit.

As described above, according to the fifth embodiment of the semiconductor memory device of the present invention, even if, for example, an overerased memory cell occurs due to batch erasing in a flash memory, data is normally written. "0" or data "1" can be read accurately, and even if there is fluctuation in the wafer process or excessive erasure due to repeated writing / erasing over a long period of time, the data can be accurately read to improve yield. And improvement of device reliability can be expected.

Next, a sixth mode of the semiconductor memory device according to the present invention will be described with reference to FIGS. First, also in the sixth embodiment, as in the fifth embodiment of the semiconductor memory device of the present invention described above, accurate data can be read even when an overerased memory cell occurs due to batch erasing in a flash memory. It is the one.

That is, as described with reference to FIGS. 37 to 40, the flash memory is capable of electrically erasing all bits collectively, and when performing the erasing collectively, the circuit technology is simple. Generally, the same erase operation is simultaneously performed on all the cell transistors (memory cells MC), and this erase operation is repeated until all the cell transistors are erased. However, since cell transistors that are relatively easy to erase and cell transistors that are relatively difficult to erase are mixed in the cell array, erasing operation for the cell transistors that are easy to erase will occur if all bits are erased collectively. It will be over-erased by being done more than necessary. Further, the characteristic difference of the cell transistors can appear relatively easily due to wafer process fluctuations, stress due to repeated writing / erasing for a long time, and the like, so that overerased cells also appear relatively frequently. It has become. Here, the write and erase operations for the cell transistors of the flash memory are as described with reference to FIGS.

In the case of a flash memory, generally, the cell array has a structure called NOR type, and the drains of the N-channel type MIS transistors (cell transistors) are commonly connected for each bit line and uniformly arranged. With the bias applied, a positive bias voltage is applied only to the gate of the selected cell transistor, and no bias is applied to the gate of the non-selected cell transistor (0
Therefore, a predetermined cell transistor can be selected. Here, since the enhancement type N-channel type MIS transistor is used as the cell transistor, no current flows in the non-selected cell transistor,
Only selected cell transistors may or may not carry current depending on the amount of charge in the floating gate. Data "0" and data "1" are assigned according to the current flowing through the selected cell transistor.

In the flash memory, when the above-mentioned over-erasure occurs in the enhancement type cell transistor, the characteristics of the cell transistor apparently change to the depletion type. When a NOR-type cell array is used, the non-selected cell transistors do not flow a current when the gate is not biased, but the cell transistors that have been over-erased have apparently depletion-type characteristics. For the sake of illustration, current flows even in a non-selected cell transistor. Therefore, for example, even if the selected cell transistor does not pass the current, the unerased unselected cell transistor passes the current, so that the data “0” and the data “1” are erroneously determined. There is a problem that it may occur.

According to a sixth aspect of the semiconductor memory device of the present invention, when a cell transistor which is over-erased occurs,
The purpose is to repair the over-erased cells and read accurate data.

FIG. 46 is a circuit diagram showing an essential part of a sixth form of the semiconductor memory device according to the present invention. In the figure, reference numeral 602 is a row decoder, 604 is a column decoder, and 607 is a sense amplifier. Further, reference numeral M
C is a memory cell transistor (memory cell) composed of an N channel type MIS transistor, WL ₁ and WL ₂ are word lines, and BL is a bit line. here,
The memory cell MC is similar to that shown in FIG.

FIG. 47 is a circuit diagram showing an example of the sense amplifier 607 of the semiconductor memory device in FIG. 46, which is an N channel type MOS transistor 6071, 6072, 6073, 6074, 6075, 607.
7 and P channel type MOS transistors 6076 and 6078.

In the sixth embodiment, for example, in order to detect a cell transistor (over-erased cell) that has been over-erased by batch erasing, first the row decoder is applied to the memory cell array subjected to the batch erasing process. 602 sets all the word lines WL ₁ , WL ₂ , ... To low level “L”, and then the column decoder 604 sets the column gates G 601 and G 60.
2, ... are sequentially selected and the bit lines BL ₁ , BL ₂ , ... Are sequentially connected to the sense amplifier 607. At this time, the sense amplifier 607
Output becomes low level "L" when the bit line to which the over-erased cell is connected is selected. Therefore, the bit line in which the output of the sense amplifier 607 becomes low level "L" is selected and its state is selected. At, the transistor 6077 of the sense amplifier 607 is turned on to increase the drive current of the sense amplifier 607 so that the overerased cell does not carry the current. Further, the row decoder 602 causes the word lines WL ₁ , WL ₂ , ...
Are scanned, and the cell transistor in which the output of the sense amplifier 607 is at the high level “H” is detected as an overerased cell.

FIG. 48 is a block diagram schematically showing an example of a system to which the sixth form of the semiconductor memory device according to the present invention is applied. In the figure, reference numeral 610 is a flash memory, 620 is a read only memory (ROM), and 630 is a central processing unit (CPU).

In the system shown in FIG. 48, the system shown in FIG.
The algorithm shown in 9 is stored in the ROM 620, and C
The PU 630 uses the flash memory 61 according to the algorithm.
It is designed to control 0. That is, CPU630
According to an algorithm stored in the ROM 620, the over-erased cells in the flash memory 610 are relieved.

FIG. 49 is a flow chart for explaining an example of processing in the sixth embodiment of the semiconductor memory device according to the present invention. As shown in the figure, when the erase process of the flash memory is started, a pre-erase write process is performed in step S611. This pre-erase write process is a process of writing data "0" to all the cell transistors of the memory cell array before collectively erasing the memory cell array of the flash memory.

Next, in step S612, the batch erase is performed, and in step S613, the erase verify is performed. That is, all the cell transistors of the memory cell array are made to collectively and gradually emit electrons from the floating gate, and the erasing process is executed. Further, in step S614, an overerase check is performed to see if there are overerase cells.
Here, in step S614, if it is determined that there is no over-erased cell (passes the over-erase check), the erase process ends, and if it is determined that there is an over-erased cell (fail in the over-erase check). Then, the process proceeds to step S615. The over-erase check in step S614 detects only one cell transistor that is over-erased, as described with reference to FIGS. 46 and 47.

In step S615, step S614
The write process is performed on one over-erased cell (over-erased bit) detected in step S6, and the process proceeds to step S616.
Excessive erasure check similar to step S614 is performed. Here, if the over-erased state of one over-erased cell detected in step S614 disappears and the normal erasing state is lost by the writing process in step S615, if there is no other over-erased cell, the process proceeds to step S617. so,
Erase verify similar to step S613 is performed. If the erase verify in step S617 is passed, the erase process ends, and if the erase verify in step S617 produces a file, the erase and erase verify are performed in steps S618 and S619.

On the other hand, by the writing process in step S615, the overerased state of one overerased cell detected in step S614 disappears and the erased state becomes normal, but if there is another overerased cell, Step S61
At 6, another overerased cell different from the overerased cell detected at step S614 is detected, and the process returns to step S615 to perform the writing process. In this way, the writing process is performed one by one on all the overerased cells in the memory cell array to bring all the overerased cells into the normal erased state.

Here, the erasing process shown in FIG. 49 is, for example, the ROM 620 of the system shown in FIG. 48, as described above.
The CPU 630 can read the data and process it, but the flash memory itself can also be configured as a hardware by incorporating a logic circuit or the like for realizing the erasing process shown in FIG. is there.

As described above, according to the sixth embodiment of the semiconductor memory device of the present invention, it is possible to repair the cell transistor in which over-erasure has occurred and read out accurate data. Fluctuation, and even if excessive erasure due to repeated writing / erasing for a long time is present, the yield can be improved and the device reliability can be greatly improved by accurately reading the data.

Next, a seventh mode of the semiconductor memory device according to the present invention will be described with reference to FIGS.

FIG. 50 shows a memory cell (MC) used in the seventh embodiment of the semiconductor memory device of the present invention, which is a cell transistor (memory cell MC) in an electrically batch erasable non-volatile semiconductor memory device (flash memory). 6 is a diagram for explaining the operation of FIG. As shown in the figure, the cell transistor is configured such that a floating gate FG insulated from any region is provided between a source and a drain, and a control gate CG is formed on the floating gate FG.

At the time of writing, the drain voltage Vd applied to the drain region DD is set to, for example, 6 volts, the gate voltage Vg applied to the control gate CG is set to the writing voltage (erasing voltage) Vpp, and applied to the source region SS. With the source voltage Vs at zero volts, the drain terminal
Electrons are injected from (DD) to the floating gate (FG) to write data "0".

At the time of erasing, the gate voltage Vg and the drain voltage Vd are set to open (floating state), the source voltage Vs is set to the erasing voltage Vpp, and electrons are drawn from the floating gate (FG) to the source terminal (SS) to erase (data). Write "1"). At the time of reading, the gate voltage Vg is set to the power supply voltage Vcc, the drain voltage Vd is set to about 1 volt, the source voltage Vs is set to 0 volt, and the data written in the cell transistor depends on whether or not the drain current flows. "1" or "0"
Determine whether.

FIG. 51 is a block circuit diagram showing an example of a related art semiconductor memory device corresponding to the seventh mode of the semiconductor memory device according to the present invention. In the figure, reference numeral 71
0 is a block address buffer, 7101 and 7102 are block selection gates, 711 is a row address buffer, 712 is a row decoder, 713 is a column address buffer, 714 is a column decoder, 715 is a data I / O buffer, 716 is a write circuit, 717 Is a sense amplifier, and 7191 and 7192 are source power supply circuits. Further, reference numeral BL indicates a bit line, WL indicates a word line, MC indicates a memory cell, W is a write control signal which becomes a high level "H" at the time of writing, and E is an erase which becomes a high level "H" at the time of erasing. The control signal is shown.

The operation of the semiconductor memory device shown in FIG. 51 is basically the same as, for example, the semiconductor memory device of the related art shown in FIG. 2 described above, but in the semiconductor memory device shown in FIG. Further provided are 710 and block select gates 7101 and 7102. That is, in the semiconductor memory device shown in FIG. 51, a plurality of blocks B1 and B2 are provided, and the block selection gates 7101 and 7102 are selected by the block selection signal from the block address buffer 710 to write one block to the write circuit. It is designed to be connected to the 716 or sense amplifier 717. Here, the memory cell array is composed of two blocks B1 and B2 having a common source, and the source power supply circuits 7191 and 7192 provided in the blocks B1 and B2 enable erase (block erase) for each block. Has become.

In the semiconductor memory device of FIG. 51, at the time of erasing, the erasing signal E which becomes the high level "H" is inputted to the row address buffer 711 and the column address buffer 713,
The outputs of the row address buffer 711 and the column address buffer 713 are set to non-select logic (for example, complementary outputs are both at low level “L”), and all word lines WL and bit lines BL are non-selected. Further, the erase signal E is input to the source power supply circuits 7191 and 7192 together with the block selection signal from the block address buffer 710, and for example, one predetermined source power supply circuit where the block selection signal becomes the high level “H” is used for erasing. Erase of a predetermined block is executed with the voltage Vpp.

Further, at the time of writing, the write control signal W which becomes the high level “H” is inputted to the row address buffer 711 and the column address buffer 713, and the row decoder 71
2 and column decoder 714, which causes
The word line WL is set to the write level Vpp, and the bit line BL is tangentially connected to the write circuit 716 via the block selection gates 7101 and 7102 selected by the block selection signal. Here, the write voltage (for example, 6 V) is supplied to the predetermined bit line BL of the block selected by the write circuit 716, and the write is executed.

In the semiconductor memory device of the related art shown in FIG. 51 described above, block erasing can be executed, but both blocks (plural blocks) cannot be simultaneously erased. That is, in the semiconductor memory device of FIG. 51, erasing of each block is performed sequentially to erase a plurality of blocks. Further, as for the verification after erasure, the verification for each erased block is performed sequentially. Therefore, when erasing a plurality of blocks, it takes a long time and the verify process is complicated.

A seventh form of the semiconductor memory device according to the present invention aims to erase a plurality of blocks at the same time, and to easily perform verification even when a plurality of blocks are simultaneously erased.

FIG. 52 is a block circuit diagram showing an embodiment of the seventh mode of the semiconductor memory device according to the present invention. In the figure, reference numeral 701 is a block address buffer, 7
021,7022 is an expected value data storage circuit, 7031,7032 is a matching circuit, 704 is a logic circuit (nand gate), 721 is a row address buffer, 722 is a row decoder, 723 is a column address buffer, 724 is a column decoder, and 725 is data. I / O buffer, 7
261,7262 are write circuits, 7721,7272 are sense amplifiers, and 7091,7092 are source power supply circuits. Also,
Reference symbol BL indicates a bit line, WL indicates a word line, MC indicates a memory cell, and W indicates a high level "H" at the time of writing.
Is a high level "H" during erase.
The erase control signal is as follows. That is, the embodiment shown in FIG. 52 is different from the semiconductor memory device of the related art of FIG. 51 in that expected value data storage circuits 7021 and 7022 and matching circuits 7031 and 7
032, multiplexer (data I / O buffer) 725, and NAND gate 704 are added.

First, at the time of erasing, one of the source power supply circuits 7091 and 7092 selected by the output signal from the block address buffer 701 is made to latch the selection signal by setting the latch control signal LT as the high level "H". After that, the erase control signal E is set to the high level "H" to operate all the source power supply circuits in which the selection signal is latched, and thereby the erase processes of a plurality of blocks are simultaneously executed.

FIG. 53 is a circuit diagram showing an example of a source power supply circuit in the semiconductor memory device of FIG. 52, FIG. 54 is a circuit diagram showing an example of an expected value data storage circuit, and FIG.
5 is a circuit diagram showing an example of a matching circuit.

As shown in FIG. 53, the source power supply circuit
The 7091 (7092) is a NAND gate 73 to which the block address signal (block selection signal) and latch control signal are input.
1, a NAND gate 732 and an inverter 733 that form a latch circuit, a NAND gate 734 to which the output of the latch circuit and an erase control signal E are input, and an erase power supply (Vp
p-channel MOS transistor 736,7 to which p) is applied
37 and an N-channel type MOS transistor 738. Further, as shown in FIG. 54, the expected value data storage circuit 7021 (7022) includes inverters 741, 744,
745,746,750 and Nandgate 742,743,747,748,74
Configured with 9. Where nand gate 743
The inverter 744 constitutes a latch circuit, and the output of the latch circuit is controlled according to the inversion control signal INV. Further, as shown in FIG. 55, the matching circuit 7031 (7032) includes an inverter 753, NAND gates 751, 75.
It is configured with 2,755 and exclusive OR gates 754. Here, the NAND gate 752 and the inverter 753 form a latch circuit, and the sense amplifier 7721
A determination is made as to whether or not the output (sense amplifier data) of (7272) and the output (reference data) of the expected value data storage circuit 7021 (7022) match.

In the erase operation performed by latching the block address signal by each of the circuits described above, only the latched erase circuit is operated by the erase control signal "E". In writing, similarly, the latch control signal LT is set to the high level “H” to set the write data “0” to the expected value data storage circuit 7021.
It is designed to latch to (7022). In this case, the data “0” is transferred from the data I / O buffer 725 to the expected value data storage circuit 7021 (7022) selected by the block address signal, and the data “0” is latched by the latch control signal LT.
Is set to a high level "H" for latching. Here, the output of the coincidence circuit 7031 (7032) is forcibly output at a high level "H" except in the selected block. As described above, the write control signal W
When writing is executed with the high level "H", writing is simultaneously executed in a plurality of selected blocks.

Next, at the time of verification, the expected value data stored in the expected value data storage circuit 7021 (7022) and the output of the sense amplifier 7721 (7272) are compared, and the NAND gate 704 is compared.
The outputs of the matching circuits 7031 and 7032 are sent to. If writing is sufficiently performed, the output of the sense amplifier becomes low level "L", so that the coincidence signal output becomes high level "H" and data is written in all the cell blocks.
The verify output VER of the NAND gate 704 becomes the low level "L", and it can be confirmed that the writing is completed at the predetermined address of all blocks. Here, at the time of erase verify, if the expected value data is inverted and verified by the inversion signal INV, if the predetermined address data in all the selected blocks becomes data “1”, it is the same as the write. It can be detected that the verify output VER becomes low level "L" and data is erased. Thus, according to the semiconductor memory device of the present embodiment, the matching circuit 70
Only when all outputs of 31 (7032) are high level "H", the output of the NAND gate 704 becomes low level "L", and if there is a matching circuit in which even one output becomes low level "L", it is defective. It will be confirmed that the bit is present.

FIG. 56 is a block circuit diagram showing another embodiment of the seventh mode of the semiconductor memory device according to the present invention. The semiconductor memory device shown in FIG. 56 has the expected value data storage circuit 7021 (7022) in the semiconductor memory device of FIG.
The expected value data generating circuit 7041 (7042) is replaced.

In the semiconductor memory device shown in FIG. 52,
Since the reference data necessary for writing and erasing before erasing are data "0" or data "1" for all bits, they can be realized without using a means for storing random data. However, FIG.
In the present embodiment shown in FIG. 5, the expected value data generation circuit 7041 (7042) selected by the block address signal is latched by setting the latch control signal LT at the high level "H". . Then, the latched expected value data generation circuit 7041 (7042) forcibly generates data "0". Further, at the time of erasing, if the expected value data is inverted by the inversion control signal INV, the same erase verify as described above can be performed.

FIG. 57 is a circuit diagram showing an example of an expected value data generation circuit in the semiconductor memory device of FIG. As shown in the figure, the expected value data generation circuit 7041 (7042)
Is an inverter 763,764,767,768, NAND gate 761,762,
It is composed of 766, 769, 770 and NOR gate 765. Where NAND gate 762 and inverter 76
3 constitutes a latch circuit. In the expected value data generation circuit 7041 (7042) shown in FIG. 57, when the address data signal (block selection signal) is latched by the latch circuit (762,763), the reference data is forcibly set to the low level "L".
Further, when the inversion control signal INV is set to the high level "H", the reference data becomes the high level "H".

FIG. 58 is a block circuit diagram showing still another embodiment of the seventh mode of the semiconductor memory device according to the present invention. In the embodiment shown in FIG. 58, the expected value data storage circuit 7021 (7022), the write circuit 7261 (7262) and the coincidence circuit 7031 (7032) of FIG. 52 are connected to the block selection signal storage circuit 70.
51 (7052), write circuit 7161 (7162) and data inversion circuit 7061 (7062) are replaced. That is, in this embodiment, the block selection signal storage circuit 7051 (705
The selection signal stored in 2) controls programming before erasure and its verification and erase verification.

In the semiconductor memory device shown in FIG. 58, at the time of programming before erasing, programming is performed in cells of a predetermined block by a block selection signal (block dress signal). Here, the data inversion circuit 7061 (7062) has a function of inverting the data of the sense amplifier 7721 (7272) between erase verify and write verify, and when writing and erasing are sufficiently performed, the output becomes high level H ”
It is designed to be. At this time, in the non-selected block, the block selection signal storage circuit 7051 (7052)
Is always set to a high level "H". As a result, the pre-erase writing and erasing as described above can be realized.

FIG. 59 is a circuit diagram showing an example of a block selection signal storage circuit in the semiconductor memory device of FIG. 58, FIG.
Is a circuit diagram showing an example of a write circuit, and FIG. 61 is a circuit diagram showing an example of a data inversion circuit.

As shown in FIG. 59, the block selection signal storage circuit 7051 (7052) includes a NAND gate 771 to which a block address signal (block selection signal) and a latch control signal are input, and a NAND gate 77 forming a latch circuit.
2 and inverter 773. In addition, FIG.
As shown in 0, the write circuit 7161 (7162) includes an inverter 781, a NOR gate 782, a NAND gate 783, and a P-channel type MOS transistor 785,786 and an N-channel type MOS transistor 787 to which a writing power source (Vpp) is applied. It is equipped with. Further, as shown in FIG. 61, the data inverting circuit 7061 (7062) is composed of inverters 792, 793 and NAND gates 791, 794, 795, 796. Then, the output of the sense amplifier 7721 (7272) is inverted according to the inverted signal INV and the NAND gate 704
To be supplied to.

Block selection signal storage circuit 70 shown in FIG.
51 (7052), the block address signal is transferred to the latch circuit (772, 77) according to the high level "H" of the latch control signal LT.
It is configured to latch to 3). Then, in the block where the selection signal is latched, the write voltage Vpp is applied to the bus line by setting the write control signal W to the high level "H" regardless of the level of the input data.

In the data inversion circuit 7061 (7062) shown in FIG. 61, when the inversion control signal INV is set to the low level "L" during the write verify, the output of the sense amplifier 7721 (7272) is set to the low level "L" (writing is performed. The output to the NAND gate 704 becomes a high level “H”. Further, at the time of erase verify, the inversion control signal INV is set to the high level “H”. Here, in the non-selected block, the block selection signal (block address signal) becomes low level "L", and the output to the NAND gate 704 is forcedly set to high level "H". As a result, it becomes possible to simultaneously erase arbitrary blocks. The multiplexer 725 supplies write data and sense amplifier data to a predetermined block according to the block selection address, and controls whether to output the data of the predetermined block.

As described above, according to the seventh embodiment of the semiconductor memory device of the present invention, the source power supply circuit of each cell block is provided with the block selection signal latch circuit.
At the same time as operating each cell source power supply circuit, each cell block is provided with a sense amplifier, an expected value data generation circuit for verifying, and a circuit for confirming the match between the sense amplifier output and the expected value, and the logic of the output of the matching circuit. By providing the circuit for taking the product, it becomes possible to simultaneously perform erasing and verifying.

[0156]

As described above in detail, according to the first embodiment of the semiconductor memory device of the present invention, the word line redundancy can be effectively introduced, and stable writing and each verification can be performed, resulting in a high yield. It is possible to realize high-performance devices.

According to the second embodiment of the semiconductor memory device of the present invention, when a plurality of defects in a real cell are replaced with redundant cells, it is possible to deal with the increase in the circuit with a small amount and to reduce the chip area. it can. Further, since a plurality of defects in the real cell can be replaced, a large capacity semiconductor memory device can be provided with high yield and low cost.

According to the third embodiment of the semiconductor memory device of the present invention, the maximum number of times N (n <N), which is expected to increase the rewriting time due to deterioration, is subjected to the shipping test. Can be guaranteed.

According to the fourth aspect of the semiconductor memory device of the present invention, by preventing the write drain voltage from decreasing due to the threshold voltage in the write voltage supply transistor, good data can be obtained even when the write voltage is lowered. Can be realized.

According to the fifth aspect of the semiconductor memory device of the present invention, data can be accurately read even if there is an overerased cell transistor.

According to the sixth aspect of the semiconductor memory device of the present invention, it is possible to relieve the cell transistor in which overerasure has occurred and read out accurate data.

According to the seventh embodiment of the semiconductor memory device of the present invention, it is possible to simultaneously erase a plurality of blocks and to easily perform verification even when a plurality of blocks are simultaneously erased.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a first form of a semiconductor memory device according to the present invention.

FIG. 2 is a block circuit diagram showing an example of a related art semiconductor memory device corresponding to the first form of the semiconductor memory device according to the present invention.

3 is a circuit diagram showing an example of a column address buffer in the semiconductor memory device of FIG.

FIG. 4 is a circuit diagram showing an example of a row address buffer in the semiconductor memory device of FIG.

5 is a circuit diagram showing an example of a row decoder in the semiconductor memory device of FIG.

FIG. 6 is a circuit diagram showing an example of a column decoder in the semiconductor memory device of FIG.

7 is a circuit diagram showing an example of a write circuit in the semiconductor memory device of FIG.

8 is a circuit diagram showing an example of a source power supply circuit in the semiconductor memory device of FIG.

9 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG.

10 is a diagram showing an example of a write characteristic curve in the semiconductor memory device of FIG.

FIG. 11 is a diagram for explaining the operation of the memory cell used in the semiconductor memory device to which the present invention is applied.

12 is a circuit diagram showing an example of a row address buffer in the semiconductor memory device of FIG.

13 is a circuit diagram showing a main part of an example of a row decoder in the semiconductor memory device of FIG.

14 is a circuit diagram showing an example of a matching circuit in the semiconductor memory device of FIG.

15 is a circuit diagram showing a main part of an example of a row decoder in the semiconductor memory device of FIG.

16 is a diagram showing waveforms of signals applied to the circuit of FIG.

17 is a circuit diagram showing an example of a verify voltage generating circuit in the semiconductor memory device of FIG.

18 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG.

19 is a circuit diagram showing an example of a logic circuit that creates a control signal to be supplied to the sense amplifier of FIG.

FIG. 20 is a block circuit diagram showing an example of a redundant circuit in a conventional semiconductor memory device corresponding to a second form of the semiconductor memory device according to the present invention.

FIG. 21 is a diagram showing a configuration example of the conventional redundant circuit shown in FIG. 20.

22 is a block diagram showing an example of a semiconductor memory device using the conventional redundant circuit shown in FIG. 20. FIG.

FIG. 23 is a block circuit diagram showing an example of a redundant circuit in the second mode of the semiconductor memory device according to the present invention.

24 is a block diagram showing configurations of a real cell and a redundant cell in the semiconductor memory device to which the redundant circuit of the present invention shown in FIG. 23 is applied.

25 is a block diagram showing an example of a semiconductor memory device using the redundancy circuit of the present invention shown in FIG.

FIG. 26 is a block circuit diagram showing another example of the redundant circuit in the second mode of the semiconductor memory device according to the present invention.

FIG. 27 is a block circuit diagram showing still another example of the redundant circuit in the second form of the semiconductor memory device according to the present invention.

28 is a block diagram showing an example of a semiconductor memory device using the redundant circuit of the present invention shown in FIG. 27. FIG.

FIG. 29 is a flowchart showing an internal write algorithm in the third form of the semiconductor memory device according to the present invention.

FIG. 30 is a block diagram showing an example of the third form of the semiconductor memory device of the present invention.

31 is a diagram showing a circuit example of a main part in the semiconductor memory device of FIG. 30. FIG.

32 is a timing diagram for explaining the operation of the circuit of FIG. 31. FIG.

FIG. 33 is a diagram for explaining the operation of the memory cell in the fourth form of the semiconductor memory device according to the present invention.

FIG. 34 is a block circuit diagram showing an example of a semiconductor memory device as a related technique corresponding to the fourth mode of the semiconductor memory device of the present invention.

FIG. 35 is a block circuit diagram showing an example of the fourth form of the semiconductor memory device of the present invention.

FIG. 36 is a circuit diagram showing an essential part of another embodiment of the fourth mode of the semiconductor memory device of the present invention.

FIG. 37 is a block circuit diagram showing an example of a conventional semiconductor memory device corresponding to a fifth mode of a semiconductor memory device according to the present invention.

38 is a circuit diagram showing a configuration of a row decoder in the semiconductor memory device of FIG. 37. FIG.

39 is a circuit diagram showing a configuration of a column decoder in the semiconductor memory device of FIG. 37. FIG.

40 is a circuit diagram showing a configuration of a bit line transfer gate in the column decoder of FIG. 39.

FIG. 41 is a block circuit diagram showing an example of a fifth mode of the semiconductor memory device according to the present invention.

42 is a circuit diagram showing a configuration of a row decoder in the semiconductor memory device of FIG. 41.

FIG. 43 is a block circuit diagram showing another embodiment of the fifth mode of the semiconductor memory device according to the present invention.

44 is a circuit diagram showing an example of first and second row decoders in the semiconductor memory device of FIG. 43. FIG.

45 is a circuit diagram showing a part of the second row decoder of FIG. 44.

FIG. 46 is a circuit diagram showing an essential part of a sixth form of a semiconductor memory device according to the present invention.

47 is a circuit diagram showing an example of a sense amplifier of the semiconductor memory device in FIG. 46. FIG.

FIG. 48 is a block diagram schematically showing an example of a system to which a sixth form of the semiconductor memory device according to the present invention is applied.

FIG. 49 is a flow chart for explaining an example of processing in the sixth form of the semiconductor memory device according to the present invention.

FIG. 50 is a diagram for explaining the operation of the memory cell used in the seventh mode of the semiconductor memory device of the present invention.

FIG. 51 is a block circuit diagram showing an example of a related art semiconductor memory device corresponding to a seventh mode of the semiconductor memory device according to the present invention.

FIG. 52 is a block circuit diagram showing an example of a seventh mode of the semiconductor memory device according to the present invention.

53 is a circuit diagram showing an example of a source power supply circuit in the semiconductor memory device of FIG. 52. FIG.

54 is a circuit diagram showing an example of an expected value data storage circuit in the semiconductor memory device of FIG. 52.

55 is a circuit diagram showing an example of a matching circuit in the semiconductor memory device of FIG. 52.

FIG. 56 is a block circuit diagram showing another embodiment of the seventh mode of the semiconductor memory device according to the present invention.

57 is a circuit diagram showing an example of an expected value data generation circuit in the semiconductor memory device of FIG. 56.

FIG. 58 is a block circuit diagram showing still another example of the seventh mode of the semiconductor memory device according to the present invention.

59 is a circuit diagram showing an example of a block selection signal storage circuit in the semiconductor memory device of FIG. 58.

FIG. 60 is a circuit diagram showing an example of a write circuit in the semiconductor memory device of FIG. 58.

61 is a circuit diagram showing an example of a data inversion circuit in the semiconductor memory device of FIG. 58. FIG.

[Explanation of symbols]

101 ... Row address buffer 102 ... Row decoder 103 ... Column address buffer 104 ... Column decoder 105 ... Data I / O buffer 106 ... Writing circuit 107 ... Sense amplifier 108 ... Negative voltage generating circuit 109 ... Source power supply circuit 120 ... Matching circuit 130 ... Redundant row decoder 140 ... Verify voltage generating circuit 200 ... Redundant circuits 201A, 201B ... Fuse 202 ... Resistor 203 ... Inverter 204 ... Address comparison circuit 205 ... Redundant cell selection circuit 206 ... Redundant cell 207 ... Real cell selection circuit 208 ... Real cell 209 ... Data read circuit 311 ... Write control circuit 312 ... Write pulse generation circuit 313 ... Cell array 314 ... Pulse counter 315 ... Switch section 316 ... Stop signal generation circuit 317 ... High voltage detection circuit 401 ... Row address buffer 402 ... Row decoder 403 ... Column address Buffer 404 ... Column decoder 405 ... Buffer circuit 406 ... Write voltage supply Transistor (P channel type MOS transistor) 407 ... Sense amplifier 408 ... Bus line 502 ... Row decoder 504 ... Column decoder 507 ... Sense amplifier 509 ... Source power supply circuit 5221 ... First row decoder 5222 ... Second row decoder 602 ... Row Decoder 604 ... Column decoder 607 ... Sense amplifier 610 ... Flash memory 620 ... ROM 630 ... CPU 704 ... Logic circuit (Nand gate) 721 ... Row address buffer 722 ... Row decoder 723 ... Column address buffer 724 ... Column decoder 725 ... Data I / O Buffer (multiplexer) 7021,7022… Expected value data storage circuit 7031,7032… Match circuit 7041,7042… Expected value data generation circuit 7051,7052… Block selection signal storage circuit 7061,7062… Data inversion circuit

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 17/00 612D 611A 639A (72) Inventor Nobuaki Takashina 1015 Kamitadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Minor Yamashita 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Yasushi Kasa, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kiyoyoshi Itano, Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Japan F-Term inside Fujitsu Limited (reference) 5B025 AA01 AD02 AD03 AD04 AD05 AD08 AD10 AD13 AE08 AF01 AF02

Claims (14)

[Claims] 1. A plurality of word lines, a plurality of bit lines,
A memory having a plurality of memory cell transistors each of which is provided at an intersection of each word line and each bit line and is configured of a MIS transistor capable of electrically controlling a threshold voltage from the outside by the presence or absence of charge injection into a floating gate. A semiconductor memory device comprising a cell array and capable of performing batch erasing by simultaneously discharging charges from the floating gates of a plurality of memory cell transistors of the memory cell array, which is normally selected for a selected word line at the time of reading. A first power supply circuit that applies a voltage to select a memory cell transistor connected to the selected word line, and a memory cell transistor that is in an over-erased state due to the collective erasure with respect to a non-selected word line at the time of reading And a second power supply circuit for deselecting Conductor memory device. 2. The memory cell transistor is formed of an enhancement type N-channel type MIS transistor, the first power supply circuit is formed as a positive voltage power supply for generating a normal positive voltage, and the second power supply is formed. The circuit is configured as a negative voltage power supply that generates a predetermined negative voltage that cuts off the N-channel type MIS transistor that functions as a depletion type by over-erasing by the batch erasing. The semiconductor memory device described. 3. A plurality of word lines and a plurality of bit lines,
A memory having a plurality of memory cell transistors each of which is provided at an intersection of each word line and each bit line and is configured of a MIS transistor capable of electrically controlling a threshold voltage from the outside by the presence or absence of charge injection into a floating gate. A semiconductor memory device comprising a cell array and capable of performing batch erase by discharging charges from the floating gates of a plurality of memory cell transistors of the memory cell array at a normal voltage for a selected word line at the time of reading. And a first row decoder that selects a memory cell transistor connected to the selected word line and a source voltage of a predetermined potential to the source of the memory cell transistor connected to the selected word line. ,
A second row for applying a voltage to the sources of all the memory cell transistors connected to the non-selected word line at the time of reading to bring them into the non-selected state including the memory cell transistors in the over-erased state due to the collective erasing A semiconductor memory device comprising: a decoder. 4. The memory cell transistor is configured by an enhancement-type N-channel type MIS transistor, and the second row decoder has a power supply voltage of a low potential with respect to a source of the memory cell transistor connected to a selected word line. 4. The semiconductor according to claim 3, wherein a voltage higher than the level of the selected bit line is applied to the sources of all the memory cell transistors connected to the non-selected word line. Storage device. 5. The second row decoder applies a voltage equal to the level of the selected bit line to the sources of all the memory cell transistors connected to the unselected word line at the time of reading. The semiconductor memory device according to claim 4, wherein 6. A semiconductor having a non-volatile memory cell capable of electrically rewriting information, and automatically writing or erasing information to or from the memory cell according to an internal algorithm provided in the semiconductor memory device. A memory device, wherein a semiconductor memory device is characterized in that a write or erase time allowable value of information in the memory cell in the internal algorithm is made variable. 7. The method according to claim 6, wherein the maximum number of times of pulse application is changed such that the number of times of maximum pulse application is reduced so that a condition severer than usual is set in a shipping test. Semiconductor memory device. 8. A plurality of word lines and a plurality of bit lines,
A MIS that is provided at each intersection of each word line and each bit line and that can electrically control the threshold voltage from the outside.
What is claimed is: 1. A semiconductor memory device comprising: a plurality of memory cells each including a transistor; and a write voltage supply transistor for applying a write voltage to a drain of the memory cell, wherein the write voltage supply transistor is a P-channel type M
A semiconductor memory device comprising an IS transistor, wherein the write voltage is effectively applied to the drain of the memory cell. 9. A plurality of word lines, a plurality of bit lines,
A MIS that is provided at each intersection of each word line and each bit line and that can electrically control the threshold voltage from the outside.
A plurality of memory cells composed of transistors; a write voltage supply transistor for applying a write voltage to the drain of the memory cell; and a write voltage supply transistor for the N-channel type M
A semiconductor memory device comprising an IS transistor, comprising a boosting means for boosting a gate electrode to a voltage equal to or higher than a sum of a write voltage and a threshold voltage of the N-channel type MIS transistor. 10. A plurality of word lines, a plurality of bit lines, and a threshold voltage electrically provided from the outside depending on the presence / absence of charge injection to the floating gates, which are provided at the intersections of the word lines and the bit lines, respectively. Control MIS
A memory cell array having a plurality of memory cell transistors each composed of a transistor, and a semiconductor memory device capable of batch erasing by simultaneously discharging charges from the floating gates of a plurality of memory cell transistors of the memory cell array A method of relieving a cell, in which a memory cell transistor that is over-erased by the batch erasing is detected, and a write process is performed on the over-erased memory cell transistor to relieve the over-erased memory cell transistor. A method for repairing an overerased cell in a semiconductor memory device, characterized in that 11. A plurality of word lines, a plurality of bit lines, and a threshold voltage electrically provided from the outside depending on the presence or absence of charge injection to the floating gates, which are respectively provided at the intersections of the word lines and the bit lines. Control MIS
A semiconductor memory device comprising a memory cell array having a plurality of memory cell transistors each including a transistor, and pre-erase write means for performing a write process on all memory cell transistors of the memory cell array before erasing, Erase means for performing erase processing and erase verify for all memory cell transistors of the memory cell array in which the pre-erase write is performed, and over-erased memory cell transistors in the memory cell array subjected to the erase processing and erase verify A semiconductor memory device comprising: an over-erased cell detecting means for detecting the above, and an over-erased cell repairing means for repairing the over-erased cell by performing a writing process on the detected over-erased cell. 12. A plurality of word lines, a plurality of bit lines, and each word line and M provided at each intersection of the bit lines and capable of electrically controlling a threshold voltage from the outside.
A semiconductor memory comprising a plurality of non-volatile memory cells formed of IS transistors, the plurality of non-volatile memory cells constituting a plurality of cell blocks selected by a block selection signal from a block address buffer. A device, wherein each of the cell blocks includes a data erasing unit, and
A semiconductor memory device comprising means for latching the block selection signal, and data erasing of the cell blocks latched with the block selection signal is performed at the same time. 13. The semiconductor memory device includes a data determination circuit that determines cell data in each of the cell blocks, and expected value data storage that stores expected value data at the time of programming and write verification and expected value data at the time of erase verification. A circuit, a match circuit that compares the output signal of the data determination circuit with the expected value data to generate a match signal, and a logic circuit that performs a logical product of the match signals for the cell blocks. Claim 12
The semiconductor memory device according to 1. 14. The semiconductor memory device includes a data determination circuit for determining cell data in each of the cell blocks, and expected value data generation for generating expected value data at the time of write and write verify and expected value data at the time of erase verify. A circuit, a match circuit that compares the output signal of the data determination circuit with the expected value data to generate a match signal, and a logic circuit that performs a logical product of the match signals for the cell blocks. Claim 12
The semiconductor memory device according to 1.