KR100538382B1 - Method for verifying cache program of nand flash memory device - Google Patents

Abstract

The present invention relates to a cache program verification method of a NAND flash memory device capable of detecting a column of a cell in which a program fail has occurred. According to the present invention, not only whether the cache program succeeds but also the failed column can be found and the test time of the device can be reduced.

Description

Method for verifying cache program of NAND flash memory device

The present invention relates to a cache program verification method of a NAND flash memory device, and more particularly, to a cache program verification method capable of detecting a column in which a program fail has occurred.

A semiconductor memory device is classified into a volatile memory device in which stored information disappears as the supply of electricity is interrupted, and a non-volatile memory device capable of maintaining information even when the supply of electricity is interrupted. do. Nonvolatile memory devices include erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory. Flash memory devices are classified into a NOR type and a NAND type according to a cell configuration.

The cache program verify algorithm used in the NAND flash memory device first inputs 80h, a cache program command to inform the cache program mode, and an address and a data input are inputted. 15h, a command to terminate the cache program mode after inputting the program, is executed to execute the cache program. Then, 80h, a program verification command for indicating the test mode, is input, and address and data input are sequentially performed. 87h, which is a command to terminate the test mode, is input after the verify operation is performed, and the cache program verification is performed by using the verify operation. At this time, the selected column is scanned according to the set test bit to check whether the program is normally executed. However, only a flag corresponding to a pass or fail is provided to provide only information on whether the program is successful. Therefore, even if a fail occurs during programming, there is a problem in which column does not know which fail occurred.

An object of the present invention is to provide a cache program verification method of a NAND flash memory device capable of detecting a column of a cell in which a program fail occurs.

The present invention provides a plurality of strings including a drain select transistor, a plurality of cell transistors, and a source select transistor, a word line connected to a gate terminal of the cell transistor, a bit line connected to a drain terminal of the drain select transistor, Providing a common source line connected to a source terminal of a source select transistor, a bit line select circuit connected to the bit line, a page buffer connected to the bit line select circuit, and applying a program voltage to the word line to provide a cell; Programming, switching to a test mode, applying a program verification command, reading and loading data of a programmed cell into the page buffer, and determining and loading data loaded into the page buffer. Or generating a fail flag, and failing A method of caching a NAND flash memory device, the method including applying a read command when one flag is generated and determining a column in which a fail occurs by detecting data loaded in the page buffer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen. Like numbers refer to like elements in the figures.

1 is a circuit diagram illustrating a cache program verification method according to a preferred embodiment of the present invention. 2 is a flowchart illustrating a cache program verification method according to a preferred embodiment of the present invention.

1 and 2, a cell array region of a NAND flash memory includes a plurality of strings 20, and 16 or 32 cells are connected to one string. Each string 20 is composed of a drain select transistor, a plurality of cell transistors, and a source select transistor. The drain region of the drain select transistor is connected to the bit lines BLe and BLo, and the source region of the source select transistor is connected to the common source line CSL. A word line W / L is connected to the gate terminal of the cell transistor. A drain select line DSL is connected to the gate terminal of the drain select transistor, and a source select line SSL is connected to the gate terminal of the source select transistor. The bit line selection circuit selects any one of the bit lines BLe and BLo in the bit line BLe and BLo, connects the selected bit line to the sensing node SO, and plots the unselected bit line. 30 is connected, and a page buffer 20 is connected to the bit line selection circuit.

The page buffer 20 performs various functions. When the data is to be read from memory cells of the selected page, the page buffer 20 detects and latches data of the selected page. This is called a 'sense operation'. In addition, when data is to be programmed from memory cells of a selected page, the page buffer temporarily stores program data provided from the outside. This is called a 'data loading operation'. When performing a verify operation to check whether the programmed / erased cell has a target threshold voltage (or whether the programmed / ereted cell is sufficiently programmed / erased), the page buffer 20 detects As in operation, the data bits of the memory cells of the selected page are sensed and latched.

Hereinafter, the page buffer 20 will be described in more detail.

The page buffer 20 is connected to a pair of bit lines BLe and BLo. The first NMOS transistor N1 is connected between the bit line BLe and the sensing node SO, and the first NMOS transistor N1 is controlled by the control signal BSLe. The second NMOS transistor N2 is connected between the bit line Blo and the sensing node SO, and the second NMOS transistor N2 is controlled by the control signal BSLo. A third NMOS transistor N3 is connected between the bit line BLe and the control signal line VIRPWR, and a fourth NMOS transistor N4 is connected between the bit line BLo and the control signal line VIRPWR. . The third NMOS transistor N3 and the fourth NMOS transistor N4 are controlled by the control signals DISe and DISo, respectively. The first to fourth NMOS transistors N1, N2, N3, and N4 select one of the bit lines BLe and BLo during a program / read operation, connect the selected bit line to the sensing node SO, and Plot the selected bit line.

The first PMOS transistor P1 is connected between the power supply voltage Vcc and the sensing node SO, and the first PMOS transistor P1 is controlled by the control signal PRECH. The page buffer 20 includes a first latch part LAT1 and a second latch part LAT2. The first latch portion LAT1 includes inverters INV1 and INV2 and has first and second latch nodes Q and / Q. The second latch portion LAT2 is composed of unverters INV3 and INV4 and has third and fourth latch nodes R and / R. The sixth and seventh NMOS transistors N6 and N7 are connected in series between the second latch node / Q and the ground voltage Vss, and the sixth and seventh NMOS transistors N6 and N7 are connected to the sensing node SO. Are controlled by the voltage level and control signal LATCH. The fifth NMOS transistor N5 is turned on / off by the control signal PGM and is connected between the sensing node SO and the first latch node Q. An eighth NMOS transistor N8 is connected between the input / output node NQ and the first latch node Q connected to the data line I / O, and the eighth NMOS transistor N8 is connected to the control signal PBDO. By turning on / off. The second PMOS transistor P2 is connected between the power supply voltage Vcc and the nWDO terminal and is turned on / turned off according to the logic state of the first latch node Q. The nWDO terminal is electrically connected to a pass / fail check circuit. The logic level of the nWDO terminal is complementary to the first latch node Q.

The ninth NMOS transistor N9 is connected between the third latch node R and the sensing node SO, and is controlled by the control signal PDUM. The tenth and eleventh NMOS transistors N10 and N11 are connected in series between the third latch node R and the ground voltage Vss. The tenth NMOS transistor N10 is controlled according to the logic state of the sensing node SO, and the eleventh NMOS transistor N11 is controlled according to the control signal CLH. A twelfth NMOS transistor N12 is connected between the input / output node NQ and the fourth latch node / R connected to the data line I / O, and the third latch node R and the input / output node NQ are connected to each other. The thirteenth NMOS transistor N13 is connected between them. The twelfth and thirteenth NMOS transistors N12 and N13 are controlled by data signals DI and nDI having complementary levels, respectively. The fourteenth NMOS transistor N14 controlled by the control signal CSET is connected between the fourth latch node / R and the ground voltage Vss.

In the cache program operation, program data is loaded into the second latch portion LAT2 according to the control signals DI and nDI. The data loaded in the second latch portion LAT2 is transferred to the first latch portion LAT1. The memory cell of the selected bit line may be programmed or program inhibited according to the program data loaded in the first latch part LAT1. The next program data is loaded into the second latch portion LAT2 while the program data loaded into the first latch portion LAT1 is stored in the memory cell. While the program operation is performed, the second latch portion LAT2 operates as a cache that temporarily stores the next program data.

In a read operation or a program verify operation, data stored in memory cells of a selected page is sensed through the first latch part LAT1. In order to perform program verification, first, the bit lines BLe and BLo and the sensing node SO are discharged. Next, the selected bit line (eg, BLe) is charged to a predetermined voltage and then floated. In this case, the bit line voltage may be reduced or maintained according to the state of the selected memory cell. A predetermined current flows to the sensing node SO through the first PMOS transistor P1 while the first NMOS transistor N1 connected between the bit line BLe and the sensing node SO of the selected cell is turned on. Supplied. If the selected memory cell is not programmed, the current supplied to the sensing node SO will be discharged through the selected memory cell. This causes the voltage of the sensing node SO to be lowered below the threshold voltage of the sixth NMOS transistor N6 so that the sixth NMOS transistor N6 is turned off. Although the seventh NMOS transistor N7 is turned on, the state of the first latch portion LAT1 is maintained. If the selected memory cell is programmed, the current supplied through the first PMOS transistor P1 is gradually charged to the sensing node SO. This causes the voltage of the sensing node SO to increase beyond the threshold voltage of the sixth NMOS transistor M6, thereby turning on the sixth NMOS transistor N6. When the seventh NMOS transistor N7 is turned on, the second latch node / Q is at ground level, and the first latch node Q has data "1" which is logic high.

To perform program verification in test mode, run the cache program and then program verification. To do this, 80h, which is a cache program command, is entered first, and address and data input are sequentially executed, so 15h, which is a command to exit the cache program mode after the program proceeds, The input program executes the cache program (S10).

Hereinafter, the program process of the cell will be described in more detail. After the program data is stored in the first latch node Q of the page buffer from the outside, the fifth NMOS transistor is turned on according to the program signal PGM to turn on the fifth NMOS transistor through the sensing node SO. It is applied to the bit lines BLe and BLo of the cell. At this time, when the program voltage is applied to the word line W / L of the cell corresponding to the input address, the program is performed on the cell where the selected bit lines BLe and BLo cross the word line W / L. . In this case, a pass voltage is applied to the word line W / L of the unselected cell. In this way, the address is input and a program voltage is applied to the word line (W / L) of the cell corresponding to the input address, the data to be input to the cell is loaded into the page buffer, and then the data is transmitted to the selected cell through the bit line. Program the data.

Subsequently, 80h, a program verification command for informing the test mode, is input, and 87h, a command for terminating the test mode, is input after the verification operation is performed by sequentially performing address and data input (S20). Perform program verification. In order to perform a program verify operation, a program verify command is applied (S30), and cell data is loaded into the page buffer 20 to read the cell data (S40). Next, the read cell data is verified (S50). At this time, if all of the cells to be programmed are successfully programmed, the data of the first latch node Q becomes “1” after the program is executed. If the cell to be programmed has not yet been programmed, the latch data (Q node) of the page buffer reading the cell maintains "0".

After program verification, the failed column can be found using only the read command 00h. When program verification is performed, cell data is loaded in the page buffer 20. At this time, the address is omitted and a read command is given (S80). Subsequently, the data can be read to find out whether the program was successfully executed by reading the program verification data loaded into the page buffer, or even the failed column.

When the data is verified as described above (S50) and all latch data is "1", a pass flag is displayed (S60), and when any latch data is "0", a fail flag is displayed ( S70). If the pass flag is generated, the program is successfully executed and the program verification ends. If a fail flag is generated, a read command is applied (S80) to detect data stored in a latch in the page buffer, and a column corresponding to data having a logic low of "0" is determined as a column having a fail (S90).

According to the present invention, not only whether the cache program succeeds but also the failed column can be found. Therefore, there is an advantage that can reduce the test time of the device.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

1 is a circuit diagram illustrating a cache program verification method according to a preferred embodiment of the present invention.

2 is a flowchart illustrating a cache program verification method according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: string 20: bit line selection circuit

30: page buffer

Claims (1)

A plurality of strings including a drain select transistor, a plurality of cell transistors, and a source select transistor; a word line connected to a gate terminal of the cell transistor; a bit line connected to a drain terminal of the drain select transistor; Providing a common source line connected to a source terminal, a bit line selection circuit connected to the bit line, and a page buffer connected to the bit line selection circuit; Programming a cell by applying a program voltage to the word line; Switching to a test mode; Authorizing a program verify command; Reading data of a programmed cell and loading the data into the page buffer; Determining a data loaded in the page buffer and generating a pass or fail flag; If a fail flag is generated, applying a read command; And And detecting the data loaded in the page buffer to determine a failed column.