JP2003046882A5 - - Google Patents
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- JP2003046882A5 JP2003046882A5 JP2001228453A JP2001228453A JP2003046882A5 JP 2003046882 A5 JP2003046882 A5 JP 2003046882A5 JP 2001228453 A JP2001228453 A JP 2001228453A JP 2001228453 A JP2001228453 A JP 2001228453A JP 2003046882 A5 JP2003046882 A5 JP 2003046882A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- intermediate frequency
- signal
- audio
- control microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002131 composite material Substances 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Description
【0003】
このようなバス制御テレビ受信機のブロック図を図5に示す。図5において、1はアンテナ、2はチューナ、3は中間周波回路、4は映像復調回路、5は表示素子、6は音声中間周波回路、7は音声処理回路、8はスピーカ、9は同期検出回路、10はシステム制御マイコンである。[0003]
A block diagram of such a bus controlled television receiver is shown in FIG. 5, 1 denotes an antenna, tuner 2, an intermediate frequency circuit 3, the video demodulation circuit 4, the display device 5, the audio intermediate frequency circuit 6, the audio processing circuit 7, 8 speakers, the synchronous 9 A detection circuit 10 is a system control microcomputer.
【0028】
図1において、1はアンテナ、2はチューナ、3は中間周波回路、4は映像復調回路、5は表示素子、6は音声中間周波回路、7は音声処理回路、8はスピーカ、9は同期検出回路、10はシステム制御マイコン、11は高周波トラップ回路である。ここに示すバス制御テレビ受信機において、アンテナ1で受信された高周波テレビ信号は、チューナ2で選局された後、中間周波回路3で増幅/検波されて複合映像信号として出力される。この複合映像信号は、映像復調回路4において色復調や信号処理が行われ、RGBの復調出力信号として出力される。このRGB信号は表示素子5に供給され、この表示素子5によって映像が再生表示される。また、複合映像信号に含まれる音声中間周波信号は、音声中間周波回路6において増幅/検波されて音声復調される。復調音声は、音声処理回路7において増幅制御され、スピーカ8で音声が再生される。更に、複合映像信号に含まれる同期信号は、同期検出回路9においてテレビ同期信号を検出し、システム制御マイコン10に供給する。システム制御マイコン10は、これを受けて、オートサーチ選局などにおいてテレビ信号の有無を判別し、有信号チャンネルの場合はサーチ動作を停止して、そのチャンネルを受信するようになっている。[0028]
In Figure 1, 1 denotes an antenna, tuner 2, an intermediate frequency circuit 3, the video demodulation circuit 4, the display device 5, the audio intermediate frequency circuit 6, the audio processing circuit 7, 8 speakers, the synchronous 9 A detection circuit, 10 is a system control microcomputer, and 11 is a high frequency trap circuit. In the bus control television receiver shown here, a high frequency television signal received by the antenna 1 is selected by the tuner 2, then amplified / detected by the intermediate frequency circuit 3 and output as a composite video signal. The composite video signal is subjected to color demodulation and signal processing in the video demodulation circuit 4 and output as an RGB demodulated output signal. The RGB signals are supplied to the display element 5, and the display element 5 reproduces and displays an image. Further, the audio intermediate frequency signal included in the composite video signal is amplified / detected in the audio intermediate frequency circuit 6 and audio-demodulated. The demodulated voice is amplified and controlled in the voice processing circuit 7 and the voice is reproduced by the speaker 8. Further, the sync signal contained in the composite video signal is detected by the sync detection circuit 9 and supplied to the system control microcomputer 10. In response to this, the system control microcomputer 10 determines the presence or absence of a television signal in auto search channel selection and the like, and in the case of a signaled channel, stops the search operation and receives that channel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001228453A JP2003046882A (en) | 2001-07-27 | 2001-07-27 | Bus control television receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001228453A JP2003046882A (en) | 2001-07-27 | 2001-07-27 | Bus control television receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2003046882A JP2003046882A (en) | 2003-02-14 |
JP2003046882A5 true JP2003046882A5 (en) | 2005-02-10 |
Family
ID=19060960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001228453A Withdrawn JP2003046882A (en) | 2001-07-27 | 2001-07-27 | Bus control television receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003046882A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4670853B2 (en) * | 2007-10-16 | 2011-04-13 | 三菱電機株式会社 | Transceiver module |
-
2001
- 2001-07-27 JP JP2001228453A patent/JP2003046882A/en not_active Withdrawn
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