JP2003046153A - Josephson junction and its manufacturing method - Google Patents
Josephson junction and its manufacturing methodInfo
- Publication number
- JP2003046153A JP2003046153A JP2001230798A JP2001230798A JP2003046153A JP 2003046153 A JP2003046153 A JP 2003046153A JP 2001230798 A JP2001230798 A JP 2001230798A JP 2001230798 A JP2001230798 A JP 2001230798A JP 2003046153 A JP2003046153 A JP 2003046153A
- Authority
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- Japan
- Prior art keywords
- polishing
- interlayer insulating
- layer
- insulating layer
- end point
- Prior art date
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 61
- 238000005498 polishing Methods 0.000 claims abstract description 46
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 238000001514 detection method Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 13
- 238000001020 plasma etching Methods 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 24
- 238000007517 polishing process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ジョセフソン接合
の効率よい作製方法、並びに、その方法によって作成さ
れるジョセフソン接合に関する。TECHNICAL FIELD The present invention relates to a method for efficiently producing a Josephson junction and a Josephson junction produced by the method.
【０００２】[0002]
【従来の技術】化学的機械研磨（Chemical Mechanical
Polishing ）技術は、Si基板の鏡面出しの一手法として
古くから実用化されている。近年では、LSIの多層配線
を実現するための平坦化技術として、半導体の製造ライ
ンに導入され始めている。一方、研究段階ではあるが、
ジョセフソン接合の作製プロセスにこのCMP技術を導入
しようという試みも行われている。なお、ジョセフソン
接合とは、超伝導体同士が、間に何らかのごく薄い障壁
を介した構造によって弱く結合したシステムの呼称であ
る。2. Description of the Related Art Chemical Mechanical Polishing
Polishing) technology has been put to practical use for a long time as a method of mirror-finishing Si substrates. In recent years, it has begun to be introduced into a semiconductor manufacturing line as a flattening technique for realizing multilayer wiring of LSI. On the other hand, at the research stage,
Attempts have also been made to introduce this CMP technology into the Josephson junction fabrication process. The Josephson junction is a name of a system in which superconductors are weakly coupled to each other by a structure having some very thin barrier between them.
【０００３】従来のジョセフソン接合の作製プロセス
（例えば、米国Hypres社や日本NECの標準作製プロセ
ス）を、図１に示す。この手法では、接合のカウンター
電極（１３）上のSiO2スパッタ膜（１４）に、コンタク
トホール（２０）を形成することにより、上部の配線層
とカウンター電極（１３）の電気的コンタクトを実現し
ている。光リソグラフィーにおけるアラインメント精度
として±0.5μｍ、最小加工寸法として1.0μｍを仮定す
ると、2.0μｍ2のカウンター電極（１３）上に1.0μｍ 2
のコンタクトホール（２０）を形成するのが、この作製
プロセスの限界である（例えば、前記NEC標準プロセス
が保証する最小接合寸法は2.0μｍ）。Conventional Josephson junction fabrication process
(For example, the standard manufacturing process of Hypres, Inc. of the United States and NEC of Japan.
Is shown in FIG. In this technique, the junction counter
SiO on the electrode (13)2Contact the sputtered film (14)
By forming the through hole (20), the upper wiring layer
And electrical contact between the counter electrode (13) and
ing. Alignment accuracy in optical lithography
Is ± 0.5 μm, and the minimum processing dimension is 1.0 μm.
2.0 μm21.0 μm on the counter electrode (13) of 2
The formation of the contact hole (20) of
Process limits (eg, NEC standard process
Guarantees a minimum joint dimension of 2.0 μm).
【０００４】しかしながら、ジョセフソン接合を用いた
集積回路の動作速度は、接合寸法が小さいほど向上する
ため、将来的には1.0μｍ以下の接合寸法が望まれてい
る。従来の作製プロセスで、1.0μｍ2の接合を実現する
場合、1.0μｍ2のカウンター電極（１４）上に1.0μｍ2
以下（好ましくは0.5μｍ2以下）のコンタクトホールを
形成することになる。しかし、このようなプロセスは、
アラインメント精度、加工精度の両面から考えて極めて
困難である。このようなことから、将来的な微小接合作
製プロセスに、CMP技術を導入しようという動きが出始
めている。However, the operating speed of the integrated circuit using the Josephson junction is improved as the junction size is smaller. Therefore, a junction size of 1.0 μm or less is desired in the future. In conventional fabrication processes, when realizing the joining of 1.0 .mu.m 2, 1.0 .mu.m on 1.0 .mu.m 2 the counter electrode (14) 2
The following (preferably 0.5 μm 2 or less) contact holes will be formed. But such a process
It is extremely difficult considering both alignment accuracy and processing accuracy. For these reasons, there is a movement to introduce CMP technology into the future micro junction fabrication process.
【０００５】図２に、ニューヨーク州立大学のBhushan
らが提案したCMPを用いたジョセフソン接合の作製プロ
セスを示す。この手法には、非常に簡潔な方法であると
いう利点の一方、プロセスの終点検出が困難であるとい
う問題点がある。研究レベルでは、エリプソメータでSi
O2層（１４）の膜厚を確認しながら少しずつ研磨してい
くことで、終点を決定する。しかし、基板材料（１０）
が透明な場合、エリプソメータによるSiO2の膜厚測定が
行えないため、終点の判定は困難となる。この場合、顕
微鏡による観察や段差計を用いて終点の判定を行うが、
多少のオーバーポリッシングは避けがたい。一方、将来
的な生産レベルでは、研磨の終点は、その研磨時間によ
って決定することになる。この場合、SiO2層（１４）の
研磨レートが少しでも変動すると、歩留まりは著しく低
下する。そのため、研磨レートを安定して一定に保つ必
要がある。しかしながら、SiO2層（１４）の研磨レート
は研磨パッドの状態や、バッキング材料、スラリーの濃
度などに非常に敏感である。特に、研磨パッドの状態は
研磨中にも変化するため、研磨レートを一定に保つこと
は困難を極める。従って、この方法では、生産レベルで
の高い歩留まりを期待することは難しい。FIG. 2 shows Bhushan of New York State University.
The fabrication process of the Josephson junction using CMP proposed by them is shown. While this method has the advantage of being a very simple method, it has a problem that it is difficult to detect the end point of the process. At the research level, the ellipsometer Si
The end point is determined by gradually polishing while confirming the film thickness of the O 2 layer (14). However, substrate material (10)
When is transparent, the SiO 2 film thickness cannot be measured by an ellipsometer, so that the determination of the end point becomes difficult. In this case, the observation of a microscope and the determination of the end point using a step gauge are performed.
Some overpolishing is inevitable. On the other hand, at a future production level, the polishing end point will be determined by the polishing time. In this case, if the polishing rate of the SiO 2 layer (14) fluctuates even a little, the yield is remarkably reduced. Therefore, it is necessary to keep the polishing rate stable and constant. However, the polishing rate of the SiO 2 layer (14) is very sensitive to the state of the polishing pad, the backing material and the concentration of the slurry. In particular, since the state of the polishing pad changes during polishing, it is extremely difficult to keep the polishing rate constant. Therefore, with this method, it is difficult to expect a high yield at the production level.
【０００６】[0006]
【発明が解決しようとする課題】そこで、本発明は、研
磨レートの変動に対して寛容であると共に、研磨プロセ
スの終点検出が確実であって、高い歩留まりが得られる
ジョセフソン接合の作製方法、並びに、その方法によっ
て作成されたジョセフソン接合を提供することを目的と
する。Therefore, the present invention is a method of manufacturing a Josephson junction that is tolerant to fluctuations in the polishing rate, that is capable of reliably detecting the end point of the polishing process, and having a high yield. Another object is to provide a Josephson junction made by the method.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明のジョセフソン接合及びその作製方法は、次
の構成を備える。すなわち、ジョセフソン接合を形成す
るカウンター電極上に積層される層間絶縁層の内部に、
その層間絶縁層を構成する物質より硬度の高い物質から
成る研磨終点検出層を設け、その研磨終点検出層が消滅
するまで、層間絶縁層に化学的機械研磨（CMP）を施
し、その後、反応性イオンエッチング（RIE）でエッチ
バックを施すことを特徴とする。In order to solve the above-mentioned problems, the Josephson junction and the manufacturing method thereof according to the present invention have the following constitutions. That is, inside the interlayer insulating layer laminated on the counter electrode forming the Josephson junction,
A polishing end point detection layer made of a material having a hardness higher than that of the material forming the interlayer insulation layer is provided, and the interlayer insulation layer is subjected to chemical mechanical polishing (CMP) until the polishing end point detection layer disappears, and then the reactivity is increased. The feature is that etching back is performed by ion etching (RIE).
【０００８】ここで、カウンター電極上の層間絶縁層及
び研磨終点検出層は、まず、カウンター電極の上に、第
１の層間絶縁層を、ベース電極とカウンター電極の厚み
の和程度設け、その第１の層間絶縁層の上に、研磨終点
検出層を薄膜状に設け、次いで、その研磨終点検出層の
上に、第２の層間絶縁層を約1μｍ以上の厚みで設ける
ことによって形成してもよい。Here, for the interlayer insulating layer and the polishing end point detecting layer on the counter electrode, firstly, the first interlayer insulating layer is provided on the counter electrode to the extent of the sum of the thicknesses of the base electrode and the counter electrode. A polishing end point detection layer may be formed in a thin film on the first interlayer insulation layer, and then a second interlayer insulation layer may be formed on the polishing end point detection layer in a thickness of about 1 μm or more. Good.
【０００９】層間絶縁層としてSiO2スパッタ膜を選定
し、研磨終点検出層としてMoを選定してもよい。A SiO 2 sputtered film may be selected as the interlayer insulating layer and Mo may be selected as the polishing end point detecting layer.
【００１０】[0010]
【発明の実施の形態】以下に、本発明の実施形態を図面
を用いて説明する。図３は、本発明によるジョセフソン
接合の作製プロセスを示す説明図である。本発明では、
化学的機械研磨（Chemical Mechanical Polishing ）
と、反応性イオンエッチング（Reactive Ion Etching)
を併用して、ジョセフソン接合を作製する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is an explanatory view showing a process for producing a Josephson junction according to the present invention. In the present invention,
Chemical Mechanical Polishing
And Reactive Ion Etching
To make a Josephson junction.
【００１１】カウンター電極（１３）上に積層されて、
ベース層と配線層の絶縁をする層間絶縁層としてのSiO2
層（１４）を成膜するまでのプロセスは、図２に示した
従来技術と同様である。ただし、SiO2層（１４）の成膜
は、２回に分けて行う。１回目のSiO2層（１４ａ）の膜
厚は平坦化終了時の厚さ程度（ベース電極とカウンター
電極の膜厚の和）とする。Laminated on the counter electrode (13),
SiO 2 as an interlayer insulating layer for insulating the base layer and the wiring layer
The process up to forming the layer (14) is similar to that of the conventional technique shown in FIG. However, the formation of the SiO 2 layer (14) is performed twice. The film thickness of the SiO 2 layer (14a) for the first time is set to about the thickness at the end of planarization (sum of the film thicknesses of the base electrode and the counter electrode).
【００１２】次に、RIEによるエッチバックの終点検出
のために、研磨終点検出層としてMo層（２１）を成膜す
る。Moを選択する理由は、RIEによるエッチバックの
際、目視でエッチングの終了を判断するのに適した金属
材料だからである。また、SiO2のエッチングに使用する
CF4系のガスでエッチング可能であることも材料選択の
重要な条件である。このような条件を満足していれば、
Mo以外の材料でもよい。Next, a Mo layer (21) is formed as a polishing end point detecting layer for detecting the end point of the etch back by RIE. The reason for selecting Mo is that it is a metal material suitable for visually determining the end of etching during RIE etchback. Also used for SiO 2 etching
It is also an important condition for material selection that it can be etched with CF 4 type gas. If you meet these conditions,
Materials other than Mo may be used.
【００１３】Mo層（２１）の成膜後、２回目のSiO2層
（１４ｂ）を1μｍ以上の厚さで成膜する。1μｍ以上と
いう膜厚は、SiO2の平坦化に要する研磨膜厚と凹凸の和
であり、CMPによる平坦化終了時点でMo層の凸部（２１
ａ）を露出させないために必要な量である。ここで、Mo
層の凸部（２１ａ）を露出させない理由は、MoとSiO2の
研磨レートが異なるために、Moの凸部が研磨中に露出す
ると、平坦化した表面に再び凸部が形成されてしまうか
らである。After forming the Mo layer (21), a second SiO 2 layer (14b) is formed to a thickness of 1 μm or more. The film thickness of 1 μm or more is the sum of the polishing film thickness and the unevenness required for the flattening of SiO 2 , and at the end of the flattening by CMP, the convex portion (21
It is an amount necessary for not exposing a). Where Mo
The reason why the convex portion (21a) of the layer is not exposed is that the polishing rate of Mo is different from that of SiO 2 , and when the convex portion of Mo is exposed during polishing, the convex portion is formed again on the flattened surface. Is.
【００１４】平坦化終了後、RIEによりエッチバックす
る。Moが削れ終わった時点でエッチングを終了すると、
自動的にカウンター電極の頭部（１３ａ）のみが表面に
露出した所望の状態を得ることができる。Moのエッチン
グ終点は、目視で検出可能であるが、プラズマ発光分析
を利用した終点検出器を用いてもよい。After the flattening is completed, etching back is performed by RIE. When etching is finished when Mo is finished,
It is possible to automatically obtain a desired state in which only the head portion (13a) of the counter electrode is exposed on the surface. Although the etching end point of Mo can be detected visually, an end point detector using plasma emission analysis may be used.
【００１５】このように、本発明によると、従来技術で
は困難であったプロセスの終点検出を、容易かつ確実に
行うことができる。また、研究レベルでの利点として、
終点検出にエリプソメータを使用しないため、透明な基
板上にもジョセフソン接合の作製が容易に行えることが
挙げられる。生産レベルでは、工程が増加するが、研磨
レートの変動に対する寛容性向上の利点が高い。なぜな
ら、２回目のSiO2層（１４ｂ）の成膜を、ある程度厚く
しておけば、研磨レートが多少変動してもMo層の凸部
（２１ａ）を露出させることなく平坦化を行え、あとは
RIEのエッチバックによりプロセスは確実に終点を迎え
るからである。このように、研磨レートの変動に対して
寛容であり、かつ、確実な研磨終点の検出が可能なの
で、高い歩留まりが得られる。As described above, according to the present invention, it is possible to easily and reliably detect the end point of the process, which has been difficult with the prior art. Also, as an advantage at the research level,
Since no ellipsometer is used to detect the end point, it is possible to easily make a Josephson junction even on a transparent substrate. At the production level, the number of steps is increased, but the advantage of improving the tolerance for fluctuations in the polishing rate is high. This is because if the second film formation of the SiO 2 layer (14b) is made to be thick to some extent, the flattening can be performed without exposing the convex portion (21a) of the Mo layer even if the polishing rate changes a little. Is
This is because the process will definitely reach the end due to the RIE etchback. As described above, since the polishing rate is tolerant and the polishing end point can be reliably detected, a high yield can be obtained.
【００１６】[0016]
【発明の効果】本発明は、上述の構成を備えることによ
って、次の効果を奏する。すなわち、カウンター電極上
に積層される層間絶縁層の内部に、その層間絶縁層を構
成する物質より硬度の高い物質から成る研磨終点検出層
を設け、CMPによる研磨平坦化とRIEによるエッチバック
を併用したので、研磨プロセスの終点を、研磨時間やエ
リプソメータによる膜厚計測により決定する従来の方法
に比べて、確実かつ容易に検出することができ、高い歩
留まりが達成できた。The present invention has the following effects by having the above-mentioned configuration. That is, a polishing end point detection layer made of a material having a hardness higher than that of the material forming the interlayer insulating layer is provided inside the interlayer insulating layer laminated on the counter electrode, and polishing flattening by CMP and etchback by RIE are used together. Therefore, the end point of the polishing process can be detected more reliably and easily, and a higher yield can be achieved, as compared with the conventional method in which the polishing time and the film thickness measurement by an ellipsometer are determined.
【図１】従来の標準的なジョセフソン接合の作製プロセ
スを示す説明図FIG. 1 is an explanatory view showing a conventional standard Josephson junction manufacturing process.
【図２】CMPを用いた従来のジョセフソン接合の作製プ
ロセスを示す説明図FIG. 2 is an explanatory diagram showing a conventional Josephson junction manufacturing process using CMP.
【図３】本発明によるジョセフソン接合の作製プロセス
を示す説明図FIG. 3 is an explanatory view showing a manufacturing process of a Josephson junction according to the present invention.
１０ 基板 １１ ベース電極 １２ バリア層 １３ カウンター電極 １３ａ 頭部 １４、１４ａ、１４ｂ 層間絶縁層 １５ フォトレジスト ２０ コンタクトホール ２１ 研磨終点検出層 ２１ａ 凸部 10 substrates 11 Base electrode 12 Barrier layer 13 counter electrode 13a head 14, 14a, 14b Interlayer insulating layer 15 photoresist 20 contact holes 21 Polishing endpoint detection layer 21a convex part
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M113 AA01 AD67 AD68 BC00 BC04 BC06 5F043 AA38 DD12 DD15 DD16 DD24 GG10 ─────────────────────────────────────────────────── ─── Continued front page F term (reference) 4M113 AA01 AD67 AD68 BC00 BC04 BC06 5F043 AA38 DD12 DD15 DD16 DD24 GG10
Claims (5)
て、 ジョセフソン接合を形成するカウンター電極上に積層さ
れる層間絶縁層の内部に、その層間絶縁層を構成する物
質より硬度の高い物質から成る研磨終点検出層を設け、 その研磨終点検出層が消滅するまで、層間絶縁層に化学
的機械研磨（CMP）を施し、 その後、反応性イオンエッチング（RIE）でエッチバッ
クを施すことを特徴とするジョセフソン接合の作製方
法。1. A method for producing a Josephson junction, wherein a material having a hardness higher than that of a material forming the interlayer insulating layer is provided inside an interlayer insulating layer laminated on a counter electrode forming the Josephson junction. Is characterized in that a chemical mechanical polishing (CMP) is performed on the interlayer insulating layer until the polishing endpoint detecting layer is eliminated, and then the etch back is performed by reactive ion etching (RIE). Method of making Josephson junction.
点検出層が、 まず、カウンター電極の上に、第１の層間絶縁層を、ベ
ース電極とカウンター電極の厚みの和程度設け、 その第１の層間絶縁層の上に、研磨終点検出層を薄膜状
に設け、 次いで、その研磨終点検出層の上に、第２の層間絶縁層
を約1μｍ以上の厚みで設けることによって形成される
請求項１に記載のジョセフソン接合の作製方法。2. An interlayer insulating layer on a counter electrode and a polishing end point detecting layer, wherein a first interlayer insulating layer is first provided on a counter electrode to a total thickness of a base electrode and a counter electrode. A thin film-shaped polishing end point detection layer is formed on the interlayer insulation layer of, and then a second interlayer insulation layer is formed on the polishing end point detection layer in a thickness of about 1 μm or more. 1. The method for producing the Josephson junction according to 1.
１または２に記載のジョセフソン接合の作製方法。3. The method for producing a Josephson junction according to claim 1, wherein the interlayer insulating layer is a SiO 2 sputtered film.
し３に記載のジョセフソン接合の作製方法。4. The method for producing a Josephson junction according to claim 1, wherein the polishing end point detection layer is made of Mo.
極上に積層される層間絶縁層の内部に、その層間絶縁層
を構成する物質より硬度の高い物質から成る研磨終点検
出層を設けられ、 その研磨終点検出層が消滅するまで、層間絶縁層に化学
的機械研磨（CMP）を施され、 その後、反応性イオンエッチング（RIE）でエッチバッ
クを施されることによって作成されたことを特徴とする
ジョセフソン接合。5. A polishing end point detection layer made of a material having a hardness higher than that of a material forming the interlayer insulating layer is provided inside the interlayer insulating layer laminated on the counter electrode forming the Josephson junction, and the polishing is performed. Joseph, characterized in that the interlayer insulating layer is subjected to chemical mechanical polishing (CMP) until the end point detection layer disappears, and then etched back by reactive ion etching (RIE). Son junction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110148664A (en) * | 2019-05-13 | 2019-08-20 | 中国科学院上海微系统与信息技术研究所 | The preparation method of Josephson junction |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110148664A (en) * | 2019-05-13 | 2019-08-20 | 中国科学院上海微系统与信息技术研究所 | The preparation method of Josephson junction |
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