JP2003046014A - Method of hermetically sealing element - Google Patents
Method of hermetically sealing elementInfo
- Publication number
- JP2003046014A JP2003046014A JP2002123474A JP2002123474A JP2003046014A JP 2003046014 A JP2003046014 A JP 2003046014A JP 2002123474 A JP2002123474 A JP 2002123474A JP 2002123474 A JP2002123474 A JP 2002123474A JP 2003046014 A JP2003046014 A JP 2003046014A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- recesses
- substrate
- hermetically sealing
- acoustic wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、素子を自由空間の
中空部に気密封止する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for hermetically sealing an element in a hollow portion of a free space.
【０００２】[0002]
【従来の技術】例えば、弾性表面波共振子，弾性表面波
フィルタ等は励振する電極側機能面に自由空間を確保
し、かつ、気密封止するため、セラミック等のパッケー
ジを用いて溶接により封止している。図３は表面実装形
パッケージに収容された従来の弾性表面波装置の断面図
である。図において、３１はセラミックパッケージ、３
２は弾性表面波素子、３３はバッケージ電極、３４はキ
ャップ、３５はボンディングワイヤ、３６は中空部であ
る。2. Description of the Related Art For example, a surface acoustic wave resonator, a surface acoustic wave filter, etc. are sealed by welding using a package of ceramic or the like in order to secure a free space on a functional surface of an electrode to be excited and hermetically seal the surface. It has stopped. FIG. 3 is a sectional view of a conventional surface acoustic wave device housed in a surface mount type package. In the figure, 31 is a ceramic package, 3
Reference numeral 2 is a surface acoustic wave element, 33 is a package electrode, 34 is a cap, 35 is a bonding wire, and 36 is a hollow portion.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上述のセラミ
ックパッケージ等は高価なため、部品としてのコストの
大きな割合を占めている。また、図３のような表面実装
パッケージの場合、１パッケージに弾性表面波素子１チ
ップを格納するため、小型化するにはパッケージ３１の
大きさにより限界があった。高さについてはボンディン
グワイヤ３５とキャップ３４と接触しないよう、中空部
３６が必要なこと、またパッケージ３１の厚さがあり、
薄型化にも制約があった。一方、チップ状の弾性表面波
素子を他のＩＣ回路等と同一基板上に搭載し同時に樹脂
封止するにはそのままでは樹脂が励振する電極表面に触
れるため、弾性表面波装置としての所望の電気的特性が
得られないという問題があった。However, since the above-mentioned ceramic package and the like are expensive, they account for a large proportion of the cost as parts. Further, in the case of the surface mount package as shown in FIG. 3, one surface acoustic wave element is stored in one package, and therefore there is a limit to the size reduction due to the size of the package 31. Regarding the height, a hollow portion 36 is required so that the bonding wire 35 and the cap 34 do not come into contact with each other, and the thickness of the package 31 is
There were also restrictions on thinning. On the other hand, when a chip-shaped surface acoustic wave element is mounted on the same substrate as other IC circuits and simultaneously resin-sealed, the electrode surface that the resin excites touches the electrode surface as it is. There was a problem that the physical characteristics could not be obtained.
【０００４】本発明の目的は、従来技術の問題点となる
高価なパッケージを使用せずに、弾性表面波素子を中空
部に気密封止して、小型，薄型化できるようにした素子
の気密封止方法を提供することにある。An object of the present invention is to hermetically seal a surface acoustic wave device in a hollow portion without using an expensive package, which is a problem of the prior art, so that the device can be made smaller and thinner. It is to provide a close-sealing method.
【０００５】[0005]
【課題を解決するための手段】上記課題の一乃至複数
は、本発明による素子の気密封止方法によれば、素子を
収容する中空部を形成するために一群の凹部を所定間隔
をおいて配設したキャップ用基部材を準備し、該キャッ
プ用基部材を前記凹部に整合した位置のそれぞれに素子
が搭載された素子搭載基板に重ね合わせて接合し、隣接
する凹部と凹部の間の位置で、前記キャップ用基板部材
と前記素子搭載基板を同一工程で切断分離することで実
現される。According to the method for hermetically sealing an element according to the present invention, one or a plurality of the above-mentioned problems are solved by forming a group of concave portions at predetermined intervals to form a hollow portion for accommodating the element. A cap base member is provided, and the cap base member is superposed on and bonded to an element mounting substrate on which an element is mounted at each position aligned with the recess, and a position between adjacent recesses and recesses. Then, it is realized by cutting and separating the cap substrate member and the element mounting substrate in the same step.
【０００６】前記中空部にはさらに半導体集積回路が複
合搭載されてもよい。A semiconductor integrated circuit may be additionally mounted in the hollow portion.
【０００７】上記課題の一乃至複数は、前記切断を前記
キャップ用基板部材と素子搭載基板が重ね合わせて接合
された位置で行うことで実現される。[0007] One or more of the above problems can be realized by performing the cutting at a position where the cap substrate member and the element mounting substrate are superposed and joined.
【０００８】上記課題の一乃至複数は、さらに、引き出
し電極に対応する部分に開口部（穴）を設け、前記切断
を開口部を横切る位置で行うことにより表現される。One or more of the above problems can be expressed by further providing an opening (hole) in a portion corresponding to the extraction electrode and performing the cutting at a position crossing the opening.
【０００９】前記キャップ用基板部材と前記素子搭載基
板の接合は、いずれか一方の面に封着剤を印刷等によっ
て付着させ、両基板を相対させ、位置合わせをして重ね
合わせ密接し加熱整合することにより行うことができ
る。The cap substrate member and the element mounting substrate are joined to each other by attaching a sealing agent to one of the surfaces by printing or the like, making the two substrates face each other, aligning and superposing, and closely heating. This can be done by
【００１０】また前記分離工程は、ダイシングにより行
うことができる。The separating step can be performed by dicing.
【００１１】さらに、前記キャップ用基板部材は石英等
のガラス基板と素子搭載用基板とを同じ材料の基板とす
ることができ、封着剤として低融点ガラスまたは絶縁性
接着剤を使用することができる。Further, as the cap substrate member, a glass substrate such as quartz and a device mounting substrate can be made of the same material, and a low melting point glass or an insulating adhesive can be used as a sealing agent. it can.
【００１２】[0012]
【発明の実施の形態】以下図面により本発明を詳細に説
明する。本発明によるの気密封止方法は、図２に基づき
図１（ａ）（ｂ）を参照して説明される。図１（ａ）は
本発明による基板貼り合わせ工程を示す分解斜視図であ
り、図１（ｂ）は本発明による封止方法によって得られ
た封止体を示す断面図である。図において、１は圧電基
板、２はすだれ状変換器電極、３は引き出し電極、４は
キャップであり、凹部５と切欠部６が設けられている。
７は気密封止するための接着剤（封着剤）である。キャ
ップ４の凹部５は、圧電基板１に設けられたすだれ状変
換器電極２の周辺部分を含む振動機能面の面積と等し
く、その機能面に対応する位置に設けられている。切欠
部６は、引き出し電極３の部分が露出してボンディング
ワイヤが付けられる大きさになっている。このようなキ
ャップ４を圧電基板１上に図１（ａ）に示した矢印のよ
うに合わせ、図１（ｂ）のように封着剤７で封止するこ
とにより、キャップ４の凹部５が気密中空部となる。The present invention will be described in detail below with reference to the drawings. The hermetic sealing method according to the present invention will be explained based on FIG. 2 and with reference to FIGS. FIG. 1A is an exploded perspective view showing a substrate bonding step according to the present invention, and FIG. 1B is a sectional view showing a sealing body obtained by a sealing method according to the present invention. In the figure, 1 is a piezoelectric substrate, 2 is a interdigital transducer electrode, 3 is an extraction electrode, 4 is a cap, and a recess 5 and a notch 6 are provided.
7 is an adhesive (sealing agent) for hermetically sealing. The concave portion 5 of the cap 4 is equal to the area of the vibration function surface including the peripheral portion of the interdigital transducer electrode 2 provided on the piezoelectric substrate 1, and is provided at a position corresponding to the function surface. The notch 6 has a size such that a portion of the extraction electrode 3 is exposed and a bonding wire can be attached. By aligning such a cap 4 on the piezoelectric substrate 1 as shown by the arrow in FIG. 1A and sealing it with the sealing agent 7 as shown in FIG. It becomes an airtight hollow part.
【００１３】図２は本発明の方法によりキャップ４を多
数作り込んだウエハ２１の平面図である。キャップ用材
料のウエハ２１に多数の凹部５、引き出し電極接続用穴
２２が設けられている。２３はダイシングライン（切断
線）であり、多数の弾性表面波素子が作り込まれたウエ
ハ状の圧電基板と貼り合わせた後このダイシングライン
でチップ状に分割される。図１（ａ）の実施例では、穴
あけ，凹状の加工が比較的容易な材料、例えば石英等を
用いてキャップ４として、ウエハ状のまま低融点ガラス
等の封着剤で封着すると、図１（ｂ）のように表面波が
励振するすだれ状変換器電極２の部分に中空部ができ、
気密封止される。FIG. 2 is a plan view of a wafer 21 having a large number of caps 4 formed by the method of the present invention. A wafer 21 made of a cap material is provided with a large number of recesses 5 and lead-out electrode connecting holes 22. Reference numeral 23 is a dicing line (cutting line), which is bonded to a wafer-shaped piezoelectric substrate on which a large number of surface acoustic wave elements are formed and then divided into chips by this dicing line. In the embodiment of FIG. 1 (a), a cap 4 is made of a material that is relatively easy to make holes and concaves, such as quartz, and is sealed with a sealing agent such as a low melting point glass in a wafer state. As shown in 1 (b), a hollow portion is formed in the portion of the interdigital transducer electrode 2 where surface waves are excited,
It is hermetically sealed.
【００１４】キャップ４の穴２２あけ、凹部５の加工は
エッチング等で行われ、また、例えばＣＯ2 レーザなど
を用いると一度に加工でき、比較的短時間で処理でき
る。また、キャップの厚さも石英などを用いれば薄型化
が可能であり、穴あけ加工や凹加工、及び貼り合わせ後
の機械的強度が保たれる厚さで薄く設定される。The holes 22 in the cap 4 and the recesses 5 are processed by etching or the like. Further, if a CO 2 laser or the like is used, the caps 4 can be processed at one time and processed in a relatively short time. Further, the thickness of the cap can be made thin by using quartz or the like, and is set to be thin so as to maintain mechanical strength after drilling, recessing, and bonding.
【００１５】封着については、低融点ガラスなどを圧電
基板１の貼り合わせ面、またはキャップ４のすだれ状変
換器電極２と接触しない面に付着させ、重ね合わせ、４
００℃前後で加熱して接合する。このように封着するこ
とで励振するすだれ状変換器電極２の周辺部を含む機能
面が中空で、かつ、気密に保たれる。上記封着剤とし
て、低融点ガラスの代わりに絶縁性接着剤を用いれば、
さらに低温で処理することができる。また、外部との電
気的接続等は、切欠部６に露出させた引き出し電極３に
ワイヤボンディングすることによって行われる。Regarding the sealing, a low melting point glass or the like is adhered to the bonding surface of the piezoelectric substrate 1 or the surface of the cap 4 which does not come into contact with the interdigital transducer electrode 2 and is then superposed.
It heats and joins at about 00 degreeC. By sealing in this way, the functional surface including the periphery of the interdigital transducer electrode 2 to be excited is kept hollow and airtight. If an insulating adhesive is used instead of the low melting point glass as the sealing agent,
It can be processed at lower temperatures. Further, electrical connection to the outside or the like is performed by wire bonding to the extraction electrode 3 exposed in the cutout portion 6.
【００１６】図２に示した多数のキャップがバッチ処理
で作り込むまれたウエハ２１の材料は、石英などが用い
られ、ウエハ形状で、多数の穴２２，凹部５をレーザ加
工またはエッチングによって設ける。それを弾性表面波
素子の電極が配置されたウエハに、低融点ガラス等の封
着剤をどちらか一方にスクリーン印刷等で付着させ、両
者を重ね合わせ加熱して接合する。ウエハを重ね合わせ
るとき、石英は透明なので位置合わせが容易である。接
合されたものをダイシングライン２３で切削すると、電
極が配置されている弾性表面波素子側のウエハとキャッ
プ材料側のウエハを同時に切断してチップ状に分離する
ことができる。The material of the wafer 21 in which a large number of caps shown in FIG. 2 are formed by batch processing is quartz or the like, and a large number of holes 22 and concave portions 5 are formed by laser processing or etching in a wafer shape. A sealing agent such as low melting point glass is attached to one of the surfaces of the wafer on which the electrodes of the surface acoustic wave element are arranged by screen printing or the like, and the both are superposed and heated to bond them. When the wafers are stacked, the quartz is transparent, so alignment is easy. When the bonded product is cut by the dicing line 23, the surface acoustic wave element side wafer on which the electrodes are arranged and the cap material side wafer can be cut at the same time to be separated into chips.
【００１７】また、多数のキャップをウエハ状でバッチ
式で製造加工することができるため、短い製作期間と低
コストで提供することができ、大きい効果がある。さら
に、キャップ材料を、例えば圧電基板材料に用いられて
いる透明なＬｉＮｂＯ3 （ニオブ酸リチウム）またはＬ
ｉＴａＯ3 （タンタル酸リチウム）等と同一材料を用い
ると熱膨張係数も同一にできるので、クラック等を防止
でき、信頼度を向上することができる。また、硬度等が
同一になるので、切削，加工が容易になる。Further, since a large number of caps can be manufactured and processed in a batch form in a wafer form, they can be provided in a short manufacturing period and at low cost, which is a great effect. Further, the cap material may be, for example, transparent LiNbO 3 (lithium niobate) or L used for a piezoelectric substrate material.
If the same material as iTaO 3 (lithium tantalate) or the like is used, the thermal expansion coefficient can be made the same, so that cracks and the like can be prevented and reliability can be improved. Further, since hardness and the like are the same, cutting and processing are easy.
【００１８】[0018]
【発明の効果】以上詳細に説明したように本発明を実施
することにより、比較的安価なキャップ材料を使用する
ことができるため、経済性に優れている。また、キャッ
プ基板と素子搭載基板を重ね合わせ接着後に両基板を同
時に切断分離し中空部を気密封止する構成なので小型化
ができ、半導体集積回路と同一基板に複合搭載して樹脂
封止することもできるので、それを組み込む機器の小型
化にはさらに有効である。As described in detail above, by carrying out the present invention, it is possible to use a relatively inexpensive cap material, which is excellent in economic efficiency. In addition, the cap substrate and the element mounting substrate are stacked and bonded together, and then both substrates are cut and separated at the same time to hermetically seal the hollow portion, which allows for miniaturization. Since it can also be used, it is more effective for downsizing the device incorporating it.
【図１】本発明の実施例を示す分解斜視図及び断面図で
ある。FIG. 1 is an exploded perspective view and a sectional view showing an embodiment of the present invention.
【図２】本発明に使用するキャップ構造の実施例の平面
図である。FIG. 2 is a plan view of an embodiment of a cap structure used in the present invention.
【図３】従来の弾性表面波装置の断面図である。FIG. 3 is a sectional view of a conventional surface acoustic wave device.
１ 圧電基板 ２ すだれ状変換器電極 ３ 引き出し電極 ４ キャップ ５ 凹部 ６ 切欠部 ７ 封着剤 ２１ ウエハ ２２ 開口部（穴） ２３ ダイシングライン ３１ パッケージ ３２ 弾性表面波素子 ３３ 電極 ３４ パッケージキャップ ３５ ワイヤ ３６ 中空部 1 Piezoelectric substrate 2 Interdigital transducer electrode 3 Extraction electrode 4 cap 5 recess 6 notches 7 Sealant 21 wafers 22 Openings (holes) 23 Dicing line 31 packages 32 Surface acoustic wave device 33 electrodes 34 Package Cap 35 wire 36 Hollow part
───────────────────────────────────────────────────── フロントページの続き (72)発明者 神田 正 東京都中野区東中野三丁目14番20号 株式 会社日立国際電気内 (72)発明者 富永 四志夫 東京都中野区東中野三丁目14番20号 株式 会社日立国際電気内 (72)発明者 小野 貴司 秋田県南秋田郡天王町天王字長沼64 アキ タ電子株式会社内 Ｆターム(参考） 5J097 AA25 AA29 GG03 GG04 HA04 HA08 KK10 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Tadashi Kanda 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Stocks Hitachi Kokusai Electric Co., Ltd. (72) Inventor Shishio Tominaga 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Stocks Hitachi Kokusai Electric Co., Ltd. (72) Inventor Takashi Ono 64 Naganuma, Tenno character, Tenno-cho, Minami-Akita-gun, Akita Prefecture Ta Denshi Co., Ltd. F-term (reference) 5J097 AA25 AA29 GG03 GG04 HA04 HA08 KK10
Claims (4)
一群の凹部を所定間隔をおいて配設したキャップ用基部
材を準備し、該キャップ用基部材を前記凹部に整合した
位置のそれぞれに素子が搭載された素子搭載基板に重ね
合わせて接合し、隣接する凹部と凹部の間の位置で、前
記キャップ用基板部材と前記素子搭載基板を同一工程で
切断分離することにより、前記中空部に素子を気密封止
する素子の気密封止方法。1. A base member for a cap, in which a group of recesses are arranged at a predetermined interval to form a hollow portion for accommodating an element, is prepared, and each of the positions where the base member for the cap is aligned with the recesses is prepared. The element is mounted on the element mounting substrate by superposing and joining, and the hollow substrate is formed by cutting and separating the cap substrate member and the element mounting substrate in the same step at a position between adjacent recesses. A method for hermetically sealing an element in which the element is hermetically sealed.
搭載されていることを特徴とする請求項１記載の素子の
気密封止方法。2. The method for hermetically sealing an element according to claim 1, wherein a semiconductor integrated circuit is further mounted in the hollow portion.
子搭載基板が重ね合わせて接合された位置で行われるこ
とを特徴とする請求項１または２記載の素子の気密封止
方法。3. The hermetically sealing method for an element according to claim 1, wherein the cutting is performed at a position where the cap substrate member and the element mounting substrate are superposed and joined to each other.
凹部と凹部の間の位置に開口部が設けられており、前記
素子に対する引き出し電極は前記素子搭載基板上に前記
開口部に対応する位置に形成されており、前記切断は開
口部を横切る位置で行われることを特徴とする請求項１
乃至３のいずれかに記載の素子の気密封止方法。4. The cap substrate member is provided with an opening at a position between adjacent recesses, and the extraction electrode for the element is located on the element mounting substrate at a position corresponding to the opening. And the cutting is performed at a position across the opening.
4. The method for hermetically sealing an element according to any one of 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002123474A JP2003046014A (en) | 2002-04-25 | 2002-04-25 | Method of hermetically sealing element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002123474A JP2003046014A (en) | 2002-04-25 | 2002-04-25 | Method of hermetically sealing element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21656895A Division JPH0951247A (en) | 1995-08-03 | 1995-08-03 | Surface acoustic wave device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003046014A true JP2003046014A (en) | 2003-02-14 |
Family
ID=19194180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002123474A Pending JP2003046014A (en) | 2002-04-25 | 2002-04-25 | Method of hermetically sealing element |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136384A (en) * | 2003-09-15 | 2005-05-26 | Rohm & Haas Electronic Materials Llc | Device package, and manufacturing method of the same and testing method therefor |
| US10319654B1 (en) | 2017-12-01 | 2019-06-11 | Cubic Corporation | Integrated chip scale packages |
-
2002
- 2002-04-25 JP JP2002123474A patent/JP2003046014A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136384A (en) * | 2003-09-15 | 2005-05-26 | Rohm & Haas Electronic Materials Llc | Device package, and manufacturing method of the same and testing method therefor |
| JP2012147007A (en) * | 2003-09-15 | 2012-08-02 | Nuvotronics Llc | Device package and methods for fabrication and test thereof |
| US8703603B2 (en) | 2003-09-15 | 2014-04-22 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
| US8993450B2 (en) | 2003-09-15 | 2015-03-31 | Nuvotronics, Llc | Device package and methods for the fabrication and testing thereof |
| US9410799B2 (en) | 2003-09-15 | 2016-08-09 | Nuvotronics, Inc. | Device package and methods for the fabrication and testing thereof |
| US9647420B2 (en) | 2003-09-15 | 2017-05-09 | Nuvotronics, Inc. | Package and methods for the fabrication and testing thereof |
| US9817199B2 (en) | 2003-09-15 | 2017-11-14 | Nuvotronics, Inc | Device package and methods for the fabrication and testing thereof |
| US10319654B1 (en) | 2017-12-01 | 2019-06-11 | Cubic Corporation | Integrated chip scale packages |
| US10553511B2 (en) | 2017-12-01 | 2020-02-04 | Cubic Corporation | Integrated chip scale packages |
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