JP2003045175A - Method of generating initializing signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of generating an initializing signal, by which layout area occupied by an initializing circuit and power consumption of the circuit at the time of power-up can be reduced. SOLUTION: The method of generating the initializing signal, that prevents the unstable initial operation of an internal circuit of a semiconductor memory device caused by applying an external power source, is provided with (a) a step where a pre-charge instruction pre-charging all banks of the semiconductor memory is received, (b) a step where the initializing signal is activated to a first level in accordance with the received pre-charge instruction, (c) a step where a refresh-instruction for refreshing the semiconductor memory is received after the pre-charge instruction is received, (d) a step where a mode setting instruction setting an operation mode of the semiconductor memory is received after the refresh-instruction is received, and (e) a step where the initializing signal is non-activated to a second level in accordance with the received mode setting instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method of generating an initialization signal for preventing unstable operation of an internal circuit due to power-up of the semiconductor memory device.

[0002]

2. Description of the Related Art Applying an external power source to use a semiconductor memory device is called power-up. The semiconductor memory device is provided with an initialization circuit in order to prevent an unstable operation inside the circuit of the semiconductor memory device during a power-up operation. Here, the unstable operation means that it is difficult to make a circuit decision on the logic high or the logic low of the data during the power-up operation period because the external power source applied from the outside is not completely stable. To do. Therefore, during the power-up period, by using an initialization signal that temporarily drops from a logic high value to a logic low value, the internal circuit is latched at a constant stable level of logic high or logic low. Prevent stable operation.

FIG. 1 is a diagram showing an initialization circuit for preventing an unstable operation of an internal circuit at the moment of power-up.

The initialization circuit 100 comprises a PMOS transistor MP1, a capacitor 300, a resistor R1 and inverters I11, I12 and I13.

The operation of the initialization circuit 100 will be described. When the external power supply EVC is applied from the outside and the voltage level of the external power supply EVC rises, the initialization signal VCCHB of the output signal of the initialization circuit 100 rises as the voltage level of the external power supply EVC rises. When the external power supply EVC becomes a certain voltage or more, the first node N11 is set to an appropriate voltage that can be recognized as a logic high level. Initialization signal VCCHB
Is output as a logic low level by the inverters I11, I12, I13 from the moment when the first node N11 is recognized as a logic high level. Therefore, the initialization signal VC
CHB shows a kind of pulse signal, and the initialization signal VCCHB in the form of such a pulse signal prevents the internal circuit of the semiconductor memory device from performing an unstable operation at the moment of power-up. Used as a signal of.

FIG. 2 is a diagram showing an example of a circuit for initializing an internal circuit using an initialization signal.

In this circuit, the input signal IN is not input at the time of power up, so that the first node N21 becomes unstable. At this time, when the initialization signal VCCHB is input as a logic high level, the inverter I21 turns on the PMOS transistor MP2,
The first node N21 is latched to a logic high level and initialized. Therefore, the fluctuation of the output signal OUT is prevented. When the initialization signal VCCHB is transited to the logic low level, the PMOS transistor MP2 is turned off and the first node N21 is maintained in the state of being latched to the logic high level. Thus, the initialization signal VCCHB functions to set the node of the internal circuit of the semiconductor memory device to a constant logic level at the moment of power up.

However, there is a problem that the initialization circuit 100 generally occupies a large layout and consumes a certain amount of power while the device is operating even after the initialization signal VCCHB is generated. Further, as the voltage level of the applied external power supply EVC decreases, the initialization signal VC
CHB also has a problem that its level becomes low and it is difficult to function as a signal for preventing unstable operation of the internal circuit.

[0009]

The present invention has been devised to solve the above problems, and an object of the present invention is to reduce the layout area occupied by the initialization circuit and the power consumption. It is to provide a method of generating a signal for activation.

[0010]

A method of generating an initialization signal according to a first aspect of the present invention for achieving the above-mentioned technical object is to provide an unstable initial state of an internal circuit of a semiconductor memory device by applying an external power source. A method of generating an initialization signal for preventing operation, comprising: (a) receiving a precharge command for precharging all banks of the semiconductor memory device; and (b) depending on the received precharge command. Activating the initialization signal to a first level, (c)
Receiving a refresh command for refreshing the semiconductor memory device after receiving the precharge command, and (d) a mode setting command for setting an operation mode of the semiconductor memory device after receiving the refresh command. And (e) deactivating the initialization signal to a second level according to the received mode setting command.

A method of generating an initialization signal according to a second aspect of the present invention for attaining the above-mentioned technical object is an initializing method for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source. In the method of generating the digitized signal,
(A) receiving a precharge command for precharging all banks of the semiconductor memory device, and (b) generating an automatic pulse according to the received precharge command and using it as the initialization signal. And a step.

A method of generating an initialization signal according to a third aspect of the present invention for achieving the above-mentioned technical object is to prevent an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source. In the method of generating the signal
(A) receiving a mode setting command for setting an operation mode of the semiconductor memory device, and (b) generating an automatic pulse according to the received mode setting command and using it as the initialization signal. It is characterized by including.

A method of generating an initialization signal according to a fourth aspect of the present invention for attaining the above-mentioned technical object is an initializing method for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source. A method of generating an initialization signal for preventing an unstable initial operation of an internal circuit of the semiconductor memory device, comprising: (a) the initialization circuit generating a preliminary initialization signal according to the external power supply; The stages that occur,
(B) receiving a mode setting command for setting an operation mode of the semiconductor memory device, and (c) generating the automatic pulse according to the preliminary initialization signal and the received mode setting command to perform the initialization. And a step of using as a signal.

The method of generating the initialization signal may further include the step of (d) turning off the initialization circuit according to the issued initialization signal.

A method of turning off an initialization circuit according to a fifth aspect of the present invention for achieving the above-mentioned technical object is to prevent an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source. In a method of turning off an initialization circuit that generates an initialization signal, (a) the initialization circuit issues an initialization signal in response to the external power supply, and (b) precharges all banks of the semiconductor memory device. Receiving a precharge command to
(C) turning off the initialization circuit in response to the precharge command.

A method of turning off an initialization circuit according to a sixth aspect of the present invention for achieving the above-mentioned technical object is to prevent an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source. In a method of turning off an initialization circuit that generates an initialization signal, (a) a step of generating the initialization signal by the initialization circuit according to the external power supply; and (b) setting an operation mode of the semiconductor memory device. The method comprises: receiving a mode setting command; and (c) turning off the initialization circuit according to the mode setting command.

A method of generating an initialization signal for initializing an internal circuit of a semiconductor memory device according to a seventh embodiment of the present invention for achieving the above-mentioned technical object is as follows: (a) The internal circuit is initialized. Receiving a mode setting command,
(B) generating a control signal according to the received mode setting command and using the control signal as the initialization signal.

The mode setting command is, for example, a signal applied to the semiconductor memory device through an external pin. The mode setting command is, for example, MRS in the synchronous DRAM and WCBR in the asynchronous DRAM.

An initialization signal generating method for initializing an internal circuit of a semiconductor memory device according to an eighth aspect of the present invention for achieving the above-mentioned technical object is (a) precharge for precharging the semiconductor memory device. Receiving a command, (b) receiving a mode setting command for initializing the internal circuit after receiving the precharge command, and (c) responding to the received mode setting command. Generating a control signal and using the control signal as the initialization signal.

The mode setting command is, for example, a signal applied to the semiconductor memory device through an external pin. The mode setting command is, for example, a synchronous DR.
AM is MRS, asynchronous DRAM is WCBR
Is.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS In order to fully understand the present invention and its operational advantages and objectives achieved by the practice of the present invention, there is shown in the accompanying drawings which show preferred embodiments of the invention and in those drawings. Must refer to content.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

When the external power supply EVC is applied, the semiconductor memory device sequentially receives a precharge command for precharging all banks, a refresh command, and a mode setting command. These commands are issued at the same time when the external power is applied to the semiconductor memory device, and the semiconductor memory device operates by receiving the commands for actually operating after receiving these commands. The first embodiment of the present invention relates to a method of issuing an initialization signal from an initialization circuit using an instruction issued initially when the external power supply EVC is applied.

Hereinafter, a method 300 of generating an initialization signal according to the first embodiment of the present invention will be described in detail with reference to FIG.

After the external power is applied to the semiconductor memory device, the semiconductor memory device receives a precharge command to precharge all the banks (step 310).
When the precharge command is applied, a signal for precharge is generated and the precharge operation is executed. However, the semiconductor memory device activates the initialization signal to the first level according to the precharge command received separately from the operation (step 320). This can be realized by configuring the circuit so that one flag, that is, a pulsed signal is emitted from the inside of the semiconductor memory device in response to the application of the precharge command. here,
The first level can be a logic high level or a logic low level.

After receiving the precharge command, the semiconductor memory device receives a refresh command for refreshing the semiconductor memory device (step 330). The semiconductor memory device is refreshed several times according to the refresh command. After receiving the refresh command, the semiconductor memory device receives a mode setting command for setting an operation mode of the semiconductor memory device (340).
The mode setting command is a command for setting the operation mode of the semiconductor memory device, and is, for example, a synchronous DRAM (Synchro
Nous DRAM) is MRS (Mode Register Set),
For asynchronous DRAM, WCBR (W
rite CAS Before RAS).

After receiving the mode setting command, the semiconductor memory device receives another command and performs an operation according to the command. Next, the semiconductor memory device is
The initialization signal is deactivated to the second level according to the received mode setting command (step 350). Here, the second level becomes a logic low level if the first level is a logic high level, and becomes a logic high level if the first level is a logic low level. According to the first and second levels, the initialization signal maintains a single pulse signal form, which serves as an initialization signal emitted from the initialization circuit. Therefore, the initialization circuit is removed to reduce the layout area occupied by the initialization circuit, and the internal circuit that operates unstable at power-up is reduced by the initialization signal issued by the instruction while reducing the power consumption of the initialization circuit. Can be converted.

A method 400 of generating an initialization signal according to a second embodiment of the present invention will be described with reference to FIG. The second embodiment of the present invention differs from the first embodiment of the present invention in that one pulse is issued in response to a precharge command. That is, after the external power is applied to the semiconductor memory device, the semiconductor memory device receives a precharge command to precharge all banks (step 410).
After receiving the precharge command, the semiconductor memory device
The refresh command and the mode setting command are sequentially received. However, instead of receiving these commands, the semiconductor memory device emits an automatic pulse according to the received precharge command and uses it as an initialization signal (step 420). This can be implemented by providing an automatic pulse generator that generates a pulse signal in response to a precharge command inside the semiconductor memory device. The pulse signal emitted from the automatic pulse generator serves as an initialization signal emitted from the initialization circuit. Therefore, the same effect as that of the first embodiment can be obtained.

A method 500 of generating an initialization signal according to a third embodiment of the present invention will be described with reference to FIG. The third embodiment of the present invention is that the first embodiment and the second embodiment of the present invention are that a single pulse is issued in response to a mode setting command.
Different from the embodiment. That is, after the external power is applied to the semiconductor memory device, a mode setting command for setting an operation mode of the semiconductor memory device is received (step 510). Then, the semiconductor memory device emits an automatic pulse according to the received mode setting command and uses it as an initialization signal (step 520). This can be implemented by providing an automatic pulse generator that generates a pulse signal according to a mode setting command inside the semiconductor memory device. Here, the mode setting command is, for example, MRS in the synchronous DRAM and WCB in the asynchronous DRAM, as in the first embodiment.
It can be R. The pulse signal emitted from the automatic pulse generator serves as an initialization signal emitted from the initialization circuit. Therefore, the same effect as that of the first and second embodiments can be obtained.

The initialization signal generating method 500 according to the third embodiment of the present invention includes a step of receiving a precharge command for precharging all banks of the semiconductor memory device before the step 510, and the precharge command. The method may further include receiving a refresh command for refreshing the semiconductor memory device after receiving the.

A method 600 of generating an initialization signal according to a fourth embodiment of the present invention will be described with reference to FIG. The fourth embodiment of the present invention is distinguished from the first, second and third embodiments of the present invention in that it has an initialization circuit for preventing an unstable initial operation of an internal circuit of a semiconductor memory device. It

That is, the initialization circuit generates a preliminary initialization signal according to the external power source (step 610). The preliminary initialization signal is the signal V output from the initialization circuit 100 of FIG.
It serves to initialize the internal circuit with the same signal as CCHB.

The semiconductor memory device receives a mode setting command (step 620). Then, the semiconductor memory device emits an automatic pulse according to the preliminary initialization signal and the received mode setting command and uses it as an initialization signal (step 630). This can be implemented by providing an automatic pulse generator, which generates a pulse signal according to a preliminary initialization signal and a mode setting command, inside the semiconductor memory device. Recently,
As the power supply voltage level decreases, the voltage level of the preliminary initialization signal also decreases. Therefore, when the external power supply is applied, the internal circuit is initialized only by the preliminary initialization signal, and if the pulse signal is issued according to the preliminary initialization signal and the mode setting command and is used as the initialization signal, the internal circuit is further improved. It can be surely initialized. Here, the mode setting command is, for example, the synchronous DR as in the first embodiment.
It can be MRS for AM and WCBR for asynchronous DRAM. The method of generating the initialization signal according to the fourth embodiment of the present invention may further include the step of turning off the initialization circuit according to the issued initialization signal. Therefore, a constant DC current flows through the initialization circuit even after power-up, and power consumption can be reduced.

The method 600 of generating an initialization signal according to the fourth embodiment of the present invention includes receiving a precharge command for precharging all banks of the semiconductor memory device between steps 610 and 620, and The method may further include receiving a refresh command for refreshing the semiconductor memory device after receiving the precharge command.

A method 700 of turning off an initialization circuit according to a fifth embodiment of the present invention will be described with reference to FIG. After the external power is applied to the semiconductor memory device, the initialization circuit generates an initialization signal according to the external power (step 710). The initialization signal serves to initialize the internal circuit as the same signal as the signal VCCHB output from the initialization circuit 100 of FIG. The semiconductor memory device receives a precharge command to precharge all the banks (step 720). Then, after receiving the precharge command, the semiconductor memory device sequentially receives the refresh command and the mode setting command. However, instead of receiving these commands, the semiconductor memory device turns off the initialization circuit according to the received precharge command (73).
0 stage). This can be implemented by configuring a circuit that can turn off the initialization circuit according to the precharge command. Therefore, it is possible to reduce power consumption due to a constant direct current flowing through the initialization circuit even after power-up.

A method 800 of turning off an initialization circuit according to a sixth embodiment of the present invention will be described with reference to FIG. The initialization circuit generates an initialization signal according to the external power supply (81
0 stage). The initialization signal serves to initialize the internal circuit as the same signal as the signal VCCHB output from the initialization circuit 100 of FIG. The semiconductor memory device receives a mode setting command (step 820). Then, the semiconductor memory device turns off the initialization circuit according to the received mode setting command (step 830). This can be implemented by configuring a circuit that can turn off the initialization circuit according to the mode setting command. Therefore, it is possible to reduce power consumption due to a constant DC current flowing through the initialization circuit even after power-up. Here, the mode setting instruction can be, for example, MRS in the synchronous DRAM and WCBR in the asynchronous DRAM, as in the first embodiment.

The initialization circuit turn-off method 800 according to the sixth embodiment of the present invention includes steps 810 and 820.
During the steps, a step of receiving a precharge command to precharge all banks of the semiconductor memory device, and a step of receiving a refresh command to refresh the semiconductor memory device after receiving the precharge command are further included. It can also be equipped.

FIG. 9 is a flow chart showing a method of generating an initialization signal according to the seventh embodiment of the present invention.

Referring to FIG. 9, in a method 900 of generating an initialization signal according to a seventh embodiment of the present invention, the semiconductor memory device first issues a mode setting command for initializing an internal circuit of the semiconductor memory device. Receive (step 910). Then, the semiconductor memory device generates a control signal according to the received mode setting command and uses the control signal as the initialization signal (step 920).

The first to sixth embodiments relate to a method of initializing an unstable operation of the internal circuit at the power-up operation of the semiconductor memory device. That is, the general initialization circuit can initialize the internal circuit at the power-up operation of the semiconductor memory device, but the semiconductor memory device is initialized during the operation of the semiconductor memory device in the power-on state. Can not. The seventh embodiment relates to a method of initializing a semiconductor memory device during operation of the semiconductor memory device.

In the initialization signal generation method 900 according to the seventh embodiment of FIG. 9, first, a mode setting command for initializing the internal circuit of the semiconductor memory device is received (step 910). Here, the mode setting command is, for example, a synchronous DR.
It can be MRS for AM and WCBR for asynchronous DRAM.

When it is necessary to initialize the semiconductor memory device during the operation of the semiconductor memory device, the MRS for generating the initialization signal is newly set. The MRS is not the existing MRS but newly set to generate the initialization signal.

The semiconductor memory device generates a control signal according to the received mode setting command and uses the control signal as the initialization signal (step 920). When the MRS for initializing the semiconductor memory device is issued, the MR
A control signal is issued according to S. The control signal is a signal having a pulse signal form. Since the initialization signal emitted from a general initialization circuit has a pulse shape, the control signal can be used as the initialization signal by forming the control signal in the form of a pulse signal.

The mode setting command may be a signal applied to the semiconductor memory device through an external pin. That is, another pin capable of applying a signal for initializing the semiconductor memory device during operation of the semiconductor memory device is mounted on the chip,
A signal can be applied through this pin if the semiconductor memory device needs to be initialized.

Here, when the semiconductor memory device is initialized by using another pin, the mode setting command is not a MRS but a pulse signal.

The initialization signal generation method 900 according to the seventh embodiment of FIG. 9 will be described in more detail with reference to FIG.

FIG. 11 is a block diagram illustrating a method of generating the initialization signal of FIG. FIG. 12 is a waveform diagram showing waveforms of the initialization signal and the control signal of FIG. Initialization circuit 100 is the conventional initialization circuit shown in FIG. 1 that generates initialization signal VCCHB. Depending on the internal configuration of the initialization circuit 100, the internal circuit 1020 can be initialized when the initialization signal VCCHB is at the high level, or the internal circuit 1020 can be initialized when the initialization signal VCCHB is at the low level.

Here, for convenience of explanation, the initialization signal VC is set.
The internal circuit 1020 is initialized when CHB is at a high level, and the initialization signal VCCHB does not affect the internal circuit 1020 when it is at a low level.

During the power-up operation, the voltage level of the external power supply rises, the initialization signal VCCCHB of the output signal of the initialization circuit 100 rises with the voltage level of the external power supply, and when it reaches a certain voltage level, it becomes low level. Is issued as. This is shown in FIG. 12 (a).

At this time, the control signal CTRLS is set to the low level. Since the control signal CTRLS is at the low level and the initialization signal VCCHB is at the high level during the power-up operation, the OR control means 1010 outputs the initialization control signal VCCHB_A as the high level. Then, the internal circuit 1020 is initialized by the initialization control signal VCCHB_A.

When the initialization signal VCCHB changes to low level, the initialization control signal VCCH_A also changes to low level. When the initialization control signal VCCHB_A is at low level, the internal circuit 1020 is not affected by the initialization signal VCCHB.

When it is necessary to initialize the semiconductor memory device during operation of the semiconductor memory device, a mode setting signal is first issued. The mode setting signal is, as described above,
It can be, for example, MRS or WCBR. When the mode setting command is issued, control signal CTRLS is issued in response to the mode setting command. The control signal CTRLS is a pulse signal.

Therefore, at the rising edge of the control signal CTRLS, the initialization control signal VCCHB_A is ORed 1
The internal circuit 102 is switched to high level by 010.
0 is initialized. At the falling edge of the control signal CTRLS, the initialization control signal VCCHB_A is changed to low level.

Control signal CTRLS and initialization control signal VC
The operation waveforms of CHB_A are shown in (b) and (c) of FIG.

In FIG. 11, it is also possible to omit the initialization circuit 100 and directly apply the control signal CTRLS to the internal circuit 1020 to initialize the internal circuit 1020. The operation of such a circuit is the same as the operation of the mode setting command and the control signal CTRLS described above, and thus detailed description thereof will be omitted.

FIG. 10 is a flow chart showing a method of generating an initialization signal according to the eighth embodiment of the present invention.

Referring to FIG. 10, in the method of generating an initialization signal 950 according to the eighth embodiment of the present invention, the semiconductor memory device first receives a precharge command for precharging the semiconductor memory device (step 960). ). After receiving the precharge command, the semiconductor memory device receives a mode setting command for initializing the internal circuit (9).
70 steps). Then, a control signal is generated according to the received mode setting command, and the control signal is used as the initialization signal (step 980).

The precharge command is issued during the power-up operation of the semiconductor memory device and then during the operation of the semiconductor memory device. Except for the precharge command issued immediately after power is turned on, the generation of the precharge command indicates that the semiconductor memory device is in a write or read operation.

Therefore, the initialization signal generating method 950 according to the eighth embodiment operates in the same manner as the initialization signal generating method 900 according to the seventh embodiment after recognizing a precharge command during operation of the semiconductor memory device. Generates an initialization signal. Initialization signal generation method 95 of the embodiment of FIG.
0 is the same as the initialization signal generation method 900 of the embodiment of FIG. 7 except that the operation state of the semiconductor memory device is determined by the precharge signal, and thus detailed description thereof will be omitted.

The optimum embodiment has been disclosed above with reference to the drawings. Although specific terms have been used herein, they are merely used to describe the present invention through specific examples, and are intended to limit the meaning and scope of the present invention as set forth in the claims. It was not used for. Therefore, those skilled in the art can adopt various modifications and equivalent other embodiments. Therefore, the true technical protection scope of the present invention should be determined based on the appended claims.

[0061]

As described above, according to the initialization signal generating method of the present invention, the layout area occupied by the initialization circuit and the power consumption of the circuit at power-up can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an initialization circuit for preventing unstable operation of an internal circuit at the moment of power-up.

FIG. 2 is a diagram showing an example of a circuit that initializes an internal circuit using an initialization signal.

FIG. 3 is a flowchart illustrating a method of generating an initialization signal according to the first exemplary embodiment of the present invention.

FIG. 4 is a flowchart illustrating a method of generating an initialization signal according to a second exemplary embodiment of the present invention.

FIG. 5 is a flowchart illustrating a method of generating an initialization signal according to a third exemplary embodiment of the present invention.

FIG. 6 is a flowchart illustrating a method of generating an initialization signal according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a flowchart illustrating a method of turning off an initialization signal according to a fifth exemplary embodiment of the present invention.

FIG. 8 is a flowchart illustrating a method of turning off an initialization signal according to a sixth exemplary embodiment of the present invention.

FIG. 9 is a flowchart illustrating a method of generating an initialization signal according to a seventh exemplary embodiment of the present invention.

FIG. 10 is a flowchart illustrating a method of generating an initialization signal according to an eighth exemplary embodiment of the present invention.

11 is a block diagram illustrating a method of generating the initialization signal of FIG.

FIG. 12 is a waveform diagram showing waveforms of the initialization signal and the control signal of FIG. 11.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Lee             222 Kumi-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, Republic of Korea             Local Mujigaemaul Kenei apartment 1002 603             issue F term (reference) 5M024 AA01 AA51 BB30 BB32 GG12                       HH09 HH11 PP02 PP03 PP10

Claims (27)

[Claims] 1. A method of generating an initialization signal for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source, comprising: (a) receiving a precharge command for precharging the semiconductor memory device. Stage
(B) activating the initialization signal to a first level according to the received precharge command, and (c) refreshing the semiconductor memory device after refreshing the precharge command. Receiving a command, (d) receiving a mode setting command for setting an operation mode of the semiconductor memory device after receiving the refresh command, and (e) responding to the received mode setting command. A step of deactivating the initialization signal to a second level. 2. The mode setting command is a synchronous DRAM.
2. The method of generating an initialization signal according to claim 1, wherein is an MRS (Mode Register Set). 3. The mode setting command is an asynchronous DRA.
In M, WCBR (Write Column Address Strobe Before)
Row Address Strobe).
The method for generating the initialization signal described in. 4. A method of generating an initialization signal for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source, comprising: (a) receiving a precharge command for precharging the semiconductor memory device. Stage
(B) generating an automatic pulse according to the received precharge command and using the pulse as the initialization signal. 5. A method for generating an initialization signal for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source, comprising: (a) a mode setting instruction for setting an operation mode of the semiconductor memory device. And the stage of receiving
(B) generating an automatic pulse according to the received mode setting command and using the pulse as the initialization signal. 6. The mode setting command is a synchronous DRAM.
6. The method for generating an initialization signal according to claim 5, wherein is an MRS. 7. The mode setting command is an asynchronous DRA.
The method for generating an initialization signal according to claim 5, wherein M is WCBR. 8. The method of generating the initialization signal comprises: (a1) receiving a precharge command for precharging the semiconductor memory device before the step (a);
The method according to claim 5, further comprising: (a2) receiving a refresh command for refreshing the semiconductor memory device after receiving the precharge command. 9. An initialization circuit for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to the application of an external power source to prevent an unstable initial operation of an internal circuit of the semiconductor memory device. In the method of generating the initialization signal,
(A) the initialization circuit generates a preliminary initialization signal in response to the external power supply; (b) receives a mode setting command for setting an operation mode of the semiconductor memory device; and (c) the above. Generating an automatic pulse according to the received initialization command and the received mode setting command and using the pulse as the initialization signal. 10. The mode setting command is a synchronous DRA.
The method for generating an internal node initialization signal according to claim 9, wherein M is MRS. 11. The mode setting command is an asynchronous DR.
The method for generating an internal node initialization signal according to claim 9, wherein the AM is WCBR. 12. The method of generating the initialization signal is (d)
The method of claim 9, further comprising turning off the initialization circuit according to the issued initialization signal. 13. The method of generating the initialization signal comprises: (b1) receiving a precharge command for precharging the semiconductor memory device between steps (a) and (b). 10. The method of generating an initialization signal according to claim 9, further comprising the step of: (b2) receiving a refresh command for refreshing the semiconductor memory device after receiving the precharge command. 14. The method of generating the initialization signal further comprises, after the step (c), a step (d) of turning off the initialization circuit according to the issued initialization signal. 14. The method of generating an internal node initialization signal according to claim 13. 15. A method of turning off an initialization circuit for generating an initialization signal for preventing an unstable initial operation of an internal circuit of a semiconductor memory device by application of an external power source, comprising: (a) responding to the external power source. The initialization circuit generates an initialization signal, (b) receives a precharge command for precharging the semiconductor memory device, and (c) turns off the initialization circuit in response to the precharge command. And a turn-off method for an initialization circuit. 16. A method of turning off an initialization circuit for generating an initialization signal for preventing an unstable initial operation of an internal circuit of a semiconductor memory device due to application of an external power source, comprising: (a) responding to the external power source; The initialization circuit generates an initialization signal, (b) receives a mode setting command for setting an operation mode of the semiconductor memory device, and (c) the initialization circuit according to the mode setting command. And a turn-off step of turning off the initialization circuit. 17. The mode setting command is a synchronous DRA.
The method for generating an internal load initialization signal according to claim 16, wherein M is MRS. 18. The mode setting command is an asynchronous DR.
17. The method of generating an internal node initialization signal according to claim 16, wherein the AM is WCBR. 19. The method of generating an initialization signal comprises: (b1) receiving a precharge command for precharging the semiconductor memory device between the steps (a) and (b). The method according to claim 16, further comprising: (b2) receiving a refresh command for refreshing the semiconductor memory device after receiving the precharge command. 20. A method of generating an initialization signal for initializing an internal circuit of a semiconductor memory device, comprising: (a) receiving a mode setting command for initializing the internal circuit; and (b) receiving the mode setting command. Generating a control signal according to the mode setting command and using the control signal as the initialization signal. 21. The method of claim 20, wherein the mode setting command is a signal applied to the semiconductor memory device through an external pin. 22. The mode setting command is a synchronous DRA.
21. The method for generating an initialization signal according to claim 20, wherein M is MRS. 23. The mode setting command is an asynchronous DR.
21. The method of generating an initialization signal according to claim 20, wherein the AM is WCBR. 24. A method of generating an initialization signal for initializing an internal circuit of a semiconductor memory device, comprising: (a) receiving a precharge command to precharge the semiconductor memory device; and (b) the precharge command. Receiving a mode setting command for initializing the internal circuit after receiving, and (c) generating a control signal according to the received mode setting command and setting the control signal to the initialization signal. The method for generating an initialization signal, comprising: 25. The method of claim 24, wherein the mode setting command is a signal applied to the semiconductor memory device through an external pin. 26. The mode setting command is a synchronous DRAM.
25. The method of generating an initialization signal according to claim 24, wherein is MRS. 27. The mode setting command is an asynchronous DR.
25. The method of generating an initialization signal according to claim 24, wherein the AM is WCBR.