JP2003044366A - Circuit and method of memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control circuit to discriminate whether or not a generated memory fault is a fixed fault and the continuous operation of which is possible without stopping the operation of the memory control circuit when the memory fault is generated in the memory control circuit to control access to an external memory. SOLUTION: The memory control circuit 10 to control the access to the external memory is provided with a fault generation history managing part 14 to discriminate whether or not the generated memory fault is the fixed fault and a faulty buffer segmentation managing part 16 to autonomously check the memory for a buffer area judged not to be the fixed fault by the fault generation history managing part 14 and to discriminate whether the buffer area is the fixed fault or an intermittent fault and in addition, a backup buffer managing part 15 to compensate a free buffer area of the external memory run short due to a memory fault by a backup buffer area when the memory fault is not the fixed fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly, in a memory control circuit for controlling access to an external memory, it is determined whether or not a memory fault has occurred and the memory fault is fixed. The present invention relates to a memory control circuit, which enables continuous operation of access to the external memory by supplementing a free buffer area of the external memory due to a memory failure with a spare buffer area when it is not a failure. .

[0002]

2. Description of the Related Art Conventionally, a memory control circuit (GA (Gate
Array) and FPGA (Field Prog)
(RAMABLE GATE ARRAY, etc.) is a write management unit that controls writing of received data, a read management unit that performs reading of transmission data and detection of a memory failure, and a buffer pointer indicating a free buffer surface (area) of the external memory. It consisted of a free buffer management unit that manages.

[0003]

However, in the above-described conventional memory control circuit, even if the memory failure that occurs is an intermittent failure due to a soft error or the like, it is determined only as a failure of the same level as the fixed failure of each external memory. Therefore, there is a problem in that when a memory failure occurs, the operation of the memory control circuit must be immediately stopped to determine the cause of the failure.

Further, in order to determine whether the generated memory failure is an intermittent failure due to a soft error or the like, or a fixed failure for each external memory, a reproduction test is repeatedly performed after the failure occurs, and an oscilloscope and logic are used. It was necessary to investigate using a measuring instrument such as an analyzer.

In order to solve the above conventional problems, a first object of the present invention is to provide a memory control circuit which can be continuously operated without stopping the operation of the memory control circuit when a memory failure occurs. .

A second object of the present invention is to provide a memory control circuit for discriminating a memory failure that has occurred into an intermittent failure and a fixed failure in order to solve the above conventional problems.

[0007]

In order to achieve the above object, the present invention determines whether or not a memory fault that has occurred is a fixed fault in a memory control circuit that controls access to an external memory. When it is not a fixed failure, the spare buffer area of the external memory, which is insufficient due to the memory failure, is supplemented with a spare buffer area, thereby enabling continuous operation of access to the external memory.

According to another aspect of the present invention, there is provided a memory control circuit including a spare buffer management section for allocating and supplementing a spare buffer area instead of the buffer area of the external memory in which the memory failure has occurred. To do.

The memory control circuit of the present invention according to claim 3 manages the number of memory failures for each buffer area detected during data transmission / reception processing, and is fixed when the number of memory failures is less than or equal to a predetermined threshold value. It is characterized by comprising a failure occurrence history management unit that determines that the memory failure of the buffer area is a fixed failure and separates the buffer area when the number of memory failures exceeds a predetermined threshold value. To do.

According to a fourth aspect of the memory control circuit of the present invention, the fault occurrence history management section is provided with a history management table for registering the number of memory failure occurrences for each buffer area.

A memory control circuit according to the present invention of claim 5 is
The failure occurrence history management unit is provided with a failure buffer isolation management unit that autonomously performs a memory check on the buffer area that is determined not to be a fixed failure and determines whether the buffer area is a fixed failure or an intermittent failure. And

According to another aspect of the memory control circuit of the present invention, the fault buffer isolation management unit registers the number of times, for each buffer area in which the fault has occurred, the number of times the memory check has determined that the fault is an intermittent fault. It is characterized by having a table.

According to a seventh aspect of the present invention, there is provided the memory control circuit according to the present invention, wherein when the fault buffer isolation management unit determines in the memory check that the number of intermittent faults exceeds a predetermined threshold value, the buffer area of the buffer region is When the memory failure is resolved, the allocation of the spare buffer is released.

According to another aspect of the memory control circuit of the present invention, the fault buffer isolation management unit performs the memory check at a timing when the data transmission / reception process is not performed.

According to a ninth aspect of the memory control method of the present invention, in the memory control method for controlling access to an external memory, it is determined whether or not the memory fault that has occurred is a fixed fault, and if the memory fault is not a fixed fault. Further, by supplementing the free buffer area of the external memory, which is insufficient due to a memory failure, with a spare buffer area, continuous operation of access to the external memory is enabled.

A memory control method according to the present invention of claim 10 is
A spare buffer management step of allocating and supplementing a spare buffer area in place of the buffer area of the external memory in which the memory failure has occurred is provided.

The memory control method according to the present invention of claim 11 is
The number of memory failures detected for each buffer area during data transmission / reception processing is managed, and when the number of memory failures is less than or equal to a predetermined threshold, it is determined that the failure is not a fixed failure, and the number of memory failures is a predetermined threshold. If the memory capacity of the buffer area is exceeded, a failure occurrence history management step of determining a memory failure in the buffer area as a fixed failure and separating the buffer area is provided.

The memory control method of the present invention according to claim 12 is:
It is characterized in that the failure occurrence history management step registers the number of memory failure occurrences in the history management table for each buffer area.

According to a thirteenth aspect of the present invention, there is provided a memory control method including:
It is provided with a failure buffer isolation management step of autonomously performing a memory check on the buffer area determined to be not a fixed failure in the failure occurrence history management step and determining whether the buffer area is a fixed failure or an intermittent failure. And

The memory control method of the present invention according to claim 14 is:
It is characterized in that the fault buffer isolation management step registers, for each buffer region in which the fault has occurred, the number of times the memory check has determined to be an intermittent fault in a management table.

According to a fifteenth aspect of the present invention, there is provided a memory control method including:
In the fault buffer isolation management step, in the memory check, when the number of times of judgment as an intermittent fault exceeds a predetermined threshold, it is determined that the memory fault in the buffer area is resolved, and the spare buffer allocation is released. It is characterized by doing.

A memory control method according to a sixteenth aspect of the present invention is
The fault buffer isolation management step is performed at a timing when the data transmission / reception processing is not performed in the memory check.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a memory control circuit according to a preferred embodiment of the present invention.

The memory control circuit 10 includes a write management unit 1
1, a read management unit 12, an empty buffer management unit 13, a failure occurrence history management unit 14, a spare buffer management unit 15, a failure buffer isolation management unit 16 and a fixed failure buffer management unit 17.

The write management unit 11 obtains the write buffer pointer to the external memory from the free buffer management unit 13, and creates the received data and the received data in the free buffer surface (area) of the external memory indicated by the buffer pointer. This is a circuit for writing check data such as parity data for received data. Further, after the writing is completed, the reading management unit 12 is notified of the writing completion buffer pointer indicating the buffer surface (area) of the external memory in which the data is written.

The read management unit 12 is the write management unit 1
It manages the write completion buffer pointer notified from 1, and reads the transmission data from the buffer surface (area) of the external memory indicated by the write completion buffer pointer in the order of write completion, and also writes the parity data, etc. by the write management unit 11. This is a circuit for checking the check data (hereinafter referred to as a parity check or the like) and detecting a memory failure.

After the completion of reading, if the memory failure is not detected by the parity check or the like, the buffer plane (area) indicated by the reading completion buffer pointer becomes an empty area, so the reading management unit 12 makes the empty buffer management unit 1
3 is notified of the read completion buffer pointer. When a memory failure is detected, the read management unit 12
Notifies the failure occurrence history management unit 14 of the failure occurrence buffer pointer indicating the buffer surface (area) of the external memory in which the failure is detected.

The free buffer management unit 13 is a circuit that manages a free buffer pointer indicating a free buffer surface (area) of the external memory, and includes a write management unit 11, a read management unit 12, and a spare buffer management unit 15. The buffer pointers described above are transmitted and received between the two.

The failure occurrence history management unit 14 stores the failure occurrence buffer pointer notified by the read management unit 12 when a memory failure is detected in the failure occurrence history management table 14
It is a circuit that is managed by 1 and determines whether or not the detected failure is a fixed failure.

FIG. 2 shows a failure occurrence history management table 141 provided in the circuit of the failure occurrence history management unit 14. Here, with respect to the buffer surface (area) of the number of areas Na surface (area), the failure occurrence buffer pointer and the number of times of occurrence of failure in the buffer surface (area) of the external memory indicated by the failure occurrence buffer pointer are managed.

The spare buffer management unit 15 is a circuit for managing a spare buffer pointer for supplementing the free buffer management unit 13 when a shortage of the free buffer pointer managed by the free buffer management unit 13 occurs. The shortage of empty buffer pointers occurs because the read completion buffer pointer returned from the read management unit 12 to the empty buffer management unit 13 when no memory failure is detected is not returned due to the occurrence of a memory failure.

FIG. 3 shows a spare buffer management table 151 provided in the circuit of the spare buffer management unit 15. Here, the spare buffer pointer is managed for the spare buffer surface (area) of the area number Nb surface (area).

The spare buffer management unit 15 is also a buffer pointer indicating the buffer surface (area) of the external memory which is judged to be an intermittent failure by the failure buffer isolation management unit 16 and is returned so as to be reused for data transmission / reception processing. Similarly, a certain intermittent failure buffer pointer is managed by the spare buffer management table 151 as a spare buffer pointer.

The fault buffer isolation management unit 16 manages the fault occurrence buffer pointer notified from the fault occurrence history management unit 14 in the fault buffer isolation management table 161, and discriminates the detected fault into an intermittent fault and a fixed fault. Circuit.

FIG. 4 shows a fault buffer isolation management table 16 provided in the circuit of the fault buffer isolation management unit 16.
1 is shown. Here, the failure occurrence buffer pointer is managed for the number of areas Nc planes (areas).

The fixed fault buffer management unit 17 includes a fault occurrence history management unit 14 and a fault buffer isolation management unit 16.
This is a circuit that manages a fixed fault buffer management table 171 that is a fixed fault buffer pointer that is a buffer pointer indicating the buffer surface (area) of the external memory that has been determined to be a fixed fault as a result of the discrimination of the memory fault.

FIG. 5 shows a fixed fault buffer management table 171 included in the circuit of the fixed fault buffer management unit 17. Here, the fixed fault occurrence buffer pointer is managed for the number Nd of areas (area).

The processing operation of the memory control circuit according to the preferred embodiment of the present invention will now be described with reference to FIGS. 6 and 7. 6 and 7 are flowcharts showing the processing operation of the memory control circuit according to the preferred embodiment of the present invention. The symbols A to D in FIG. 6 indicate that they are the same as those in FIG. 7.

If there is a data transmission / reception process in the memory control circuit 10, the process proceeds to step 602, and if there is no process, the process proceeds to step 611 (step 601).

If there is data transmission / reception processing in step 601, the read management unit 12 determines whether or not a memory failure has occurred by a parity check or the like (step 60).
2) If there is no failure, the procedure starts, and if there is a failure, the failure occurrence history management unit 14 is notified of the buffer pointer that is the failure occurrence buffer pointer, and the process proceeds to step 603.

When a memory failure is detected in step 602, the failure occurrence history management table 141 is searched to see if the failure occurrence buffer pointer notified by the read management unit 12 has been registered in the past (step 603), and registration is performed. If so, the process proceeds to step 608. If not registered, the buffer pointer is registered in the failure occurrence history management table 141 (step 604), and the failure buffer isolation management unit 16
It is registered in the failure buffer isolation management table 161 (step 605).

Next, in order to compensate for the empty buffer pointers managed by the empty buffer management unit 13 that have decreased due to the occurrence of the faulty buffer pointer, the spare buffer management table 151 of the spare buffer management unit 15 manages them. The spare buffer pointer is
By supplementing with 3, the lack of the buffer surface (area) used in the data transmission / reception processing is adjusted (step 60).
6).

In this adjustment, the number of spare buffer pointers managed by the spare buffer management table 151 is reduced, so that it is calculated whether there is a remaining spare buffer pointer (step 607), and there is a remaining spare buffer pointer. If so, go to start. If there is no remaining memory, and if the next memory failure occurs in step 602,
In step 606, the spare buffer pointer cannot be replenished in the empty buffer management unit 13, so that the buffer surface (area) used in the data transmission / reception process becomes insufficient and the process cannot be continued. Therefore, the continuous operation is stopped.

In step 603, when the failure occurrence buffer pointer notified by the read management unit 12 has been registered in the past, the failure occurrence history management table 141
In order to count the number of times the failure has occurred on the buffer surface (area) of the external memory indicated by the retrieved buffer pointer, the number of times that has already been added is registered in the failure occurrence history management table 141 (step 608). ).
Next, the registered failure occurrence count indicates the failure occurrence history management unit 1
In step 4, it is determined whether or not the preset number has been exceeded (step 609), and if not, the relevant buffer pointer is notified to the fault buffer isolation management unit 16,
Control goes to step 605.

If the number of times of failure occurrence registered in step 608 exceeds the number of times preset by the failure occurrence history management unit 14, the external memory of the external memory indicated by the failure occurrence buffer pointer notified from the reading management unit 12 will be described. The buffer plane (area) is determined to have a fixed fault, and the fixed fault buffer management unit is notified of the buffer pointer that is the fixed fault buffer pointer. Further, the failure occurrence history management table 141
Then, the buffer pointer is deleted and the number of occurrences is cleared (step 610), and the process proceeds to step 616.

When there is no data transmission / reception processing in step 601, the fault buffer isolation management unit 16 searches the fault buffer isolation management table 161 for the presence or absence of registration of the fault buffer pointer (step 61).
1) If there is no registration, move to start. If there is registration, the memory control circuit 10 performs a memory self-check on the buffer surface (area) of the external memory indicated by the buffer pointer registered in the fault buffer isolation management table 161 by hardware self-check (step 61
2) If the result of the memory self-check is not OK, the process proceeds to step 615.

For the memory self-check of the hardware autonomous, for example, a conventional method of writing a value of "0" or "1" in all bits and reading it normally can be used. .

If the result of the memory self-check is OK, it is judged whether or not the number of OKs set in advance by the fault buffer isolation management unit 16 exceeds the number of times the result is OK in step 613. (Step 613),
If not exceeded, move to start.

If it exceeds, it is determined that the buffer surface (area) of the external memory indicated by the failure buffer pointer detected in step 602 is an intermittent failure due to a soft error or the like, and the memory of the buffer surface (area) concerned. Assuming that the failure has been resolved, the buffer pointer is deleted from the failure buffer isolation management table 161 and registered in the spare buffer management table 151 so that it can be reused for data transmission / reception processing (step 614), and the process proceeds to the start. Also, in step 606, an empty buffer surface (area)
As an adjustment of the shortage, the allocation of the spare buffer pointer replenished from the spare buffer management unit 15 to the free buffer management unit 13 is released.

If the result of the memory self-check in step 612 is not OK, it is determined that the buffer surface (area) of the external memory indicated by the failure occurrence buffer pointer detected in step 602 is a fixed failure, and the failure occurrence history management table 141 and The buffer pointer is deleted from the failure buffer isolation management table 161 (step 615), and the fixed failure buffer management unit 17 is notified of the buffer pointer that is the fixed failure buffer pointer.

Subsequently, step 610 or step 6
The fixed fault buffer pointer notified from 15 is registered in the fixed fault buffer management table 171 (step 6).
16). Here, the fault occurrence buffer plane (area) preset by the fixed fault buffer management unit 17 is the step 6
It is determined whether or not the surface (area) registered in 16 is exceeded (step 617). If it is not exceeded, it is determined that the operation is started. If it is exceeded, it is determined that continuous operation is impossible, and continuous operation is stopped.

Although the present invention has been described above with reference to the preferred embodiments and examples, the present invention is not necessarily limited to the above-described embodiments and examples, and various modifications are possible within the scope of the technical idea. It can be implemented by modifying the above.

For example, in the case of a memory control circuit in which the total buffer surface (area) used for data transmission / reception processing needs to be maintained at a certain area or more, the spare buffer management section 15
Is deleted and the required buffer plane (area) is managed by the empty buffer management unit 13, which is useful for simplifying the circuit scale and lengthening the continuous operation time.

[0055]

As described above, the memory control circuit of the present invention can determine whether the memory failure that occurred is an intermittent failure due to a soft error or the like, or a fixed failure for each external memory. .

Further, since the work of discriminating between the intermittent fault and the fixed fault is carried out in the free time when the memory control circuit is hardware autonomous and does not perform the data transmission / reception processing, the memory control circuit is not affected by the performance deterioration.

Further, by reading out the fixed fault buffer pointer registered in the fixed fault buffer management table of the fixed fault buffer management unit, the fixed fault buffer plane (area) of the external memory can be searched quickly.

Further, since the spare buffer management unit is provided with the spare buffer pointer, the memory control circuit can be continuously operated even when a memory failure occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control circuit according to a preferred embodiment of the present invention.

FIG. 2 is a diagram showing a failure occurrence history management table included in a circuit of a failure occurrence history management unit.

FIG. 3 is a diagram showing a spare buffer management table included in a circuit of a spare buffer management unit.

FIG. 4 is a diagram showing a fault buffer isolation management table provided in a circuit of a fault buffer isolation management unit.

FIG. 5 is a diagram showing a fixed fault buffer management table included in a circuit of a fixed fault buffer management unit.

FIG. 6 is a flowchart showing a processing operation of the memory control circuit according to the preferred embodiment of the present invention.

FIG. 7 is a flowchart showing a processing operation of the memory control circuit according to the preferred embodiment of the present invention.

[Explanation of symbols]

10 Memory control circuit 11 Writing Management Department 12 Read management section 13 Free buffer management unit 14 Failure history management section 15 Spare buffer management unit 16 Failure buffer isolation management unit 17 Fixed fault buffer management unit 141 Fault occurrence history management table 151 Spare buffer management table 161 Fault Buffer Isolation Management Table 171 Fixed Fault Buffer Management Table

Claims (16)

[Claims] 1. In a memory control circuit for controlling access to an external memory, it is determined whether or not a memory fault that has occurred is a fixed fault, and if the memory fault is not a fixed fault, the external fault that is insufficient due to the memory fault. By supplementing the free buffer area of the memory with the spare buffer area,
A memory control circuit, which enables continuous operation of access to the external memory. 2. The memory control circuit according to claim 1, further comprising a spare buffer management unit that allocates and supplements a spare buffer area instead of the buffer area of the external memory in which the memory failure has occurred. . 3. The number of memory failures detected for each buffer area during data transmission / reception processing is managed, and when the number of memory failures is less than or equal to a predetermined threshold, it is determined that the failure is not a fixed failure. The fault occurrence history management unit is provided, which discriminates a memory fault in the buffer area as a fixed fault and separates the buffer area when the number of times exceeds a predetermined threshold value. Memory control circuit. 4. The memory control circuit according to claim 3, wherein the failure occurrence history management unit includes a history management table for registering the number of memory failure occurrences for each buffer area. 5. A failure buffer isolation management unit that autonomously performs a memory check on the buffer area determined by the failure history management unit to be not a fixed failure and determines whether the buffer area is a fixed failure or an intermittent failure. The memory control circuit according to claim 3, further comprising: 6. The fault buffer isolation management unit is provided with a management table for registering the number of times, as a result of the memory check, an intermittent fault is determined for each buffer area in which the fault has occurred. 5. The memory control circuit described in 5. 7. The fault buffer isolation management unit determines that the memory fault in the buffer area has been resolved when the number of times of judgment of an intermittent fault in the memory check exceeds a predetermined threshold value, and 7. The buffer allocation is released, as claimed in claim 5 or claim 6.
The memory control circuit described in 1. 8. The memory control according to claim 6, wherein the failure buffer isolation management unit performs the memory check at a timing when the data transmission / reception processing is not performed. circuit. 9. A memory control method for controlling access to an external memory, determining whether or not a memory failure that has occurred is a fixed failure, and if the memory failure is not a fixed failure, the external connection that is insufficient due to the memory failure. By supplementing the free buffer area of the memory with the spare buffer area,
A memory control method which enables continuous operation of access to the external memory. 10. The memory control method according to claim 9, further comprising a spare buffer management step of allocating and supplementing a spare buffer area instead of the buffer area of the external memory in which the memory failure has occurred. . 11. The number of memory failures detected for each buffer area during data transmission / reception processing is managed, and when the number of memory failures is less than or equal to a predetermined threshold, it is determined that the memory failure is not a fixed failure. 10. The method according to claim 9, further comprising: a failure occurrence history management step of discriminating a memory failure in the buffer area as a fixed failure and disconnecting the buffer area when the number of times exceeds a predetermined threshold value.
0. The memory control method described in 0. 12. The memory control method according to claim 11, wherein the failure occurrence history management step registers the number of memory failure occurrences for each buffer area in a history management table. 13. A failure buffer isolation management step of autonomously performing a memory check on the buffer area determined to be not a fixed failure in the failure occurrence history management step to determine whether the buffer area is a fixed failure or an intermittent failure. The memory control method according to claim 11, further comprising: 14. The fault buffer isolation management step registers, in a management table, the number of times that the fault is determined to be an intermittent fault for each buffer area in which the fault has occurred. The memory control method described in. 15. The fault buffer isolation management step determines that the memory fault of the buffer area is resolved when the number of times of judgment of an intermittent fault exceeds a predetermined threshold in the memory check, and the backup The memory control method according to claim 13 or 14, wherein allocation of the buffer is released. 16. The memory control according to claim 14, wherein the fault buffer isolation management step performs the memory check at a timing when the data transmission / reception processing is not performed. Method.