JP2003031794A - Compound semiconductor epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor epitaxial wafer on which an element having good electrical characteristics can be fabricated by reducing leak current between the source-drain electrodes. SOLUTION: The compound semiconductor epitaxial wafer comprises a semiconductor substrate 10, and an epitaxial layer 20 formed on the semiconductor substrate 10 wherein a single layer or multilayer insulation layer 15 is provided between the semiconductor substrate 10 and the epitaxial layer 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor epitaxial wafer used for field effect transistors, hetero bipolar transistors and the like.

[0002]

2. Description of the Related Art An epitaxial wafer for a compound semiconductor Schottky gate field effect transistor (MESFET) is manufactured by growing an epitaxial layer on a semi-insulating GaAs substrate by a metal organic chemical vapor deposition (MOVPE) method.

FIG. 2 shows a cross-sectional view of a conventional MESFET epitaxial wafer.

As shown in FIG. 2, the epitaxial layer is composed of
In order from the substrate 1 side, a buffer layer 2 made of high-resistance undoped GaAs having a thickness of 500 to 1000 nm or an epitaxial crystal having a multilayer structure of undoped GaAs and undoped AlGaAs, and having a thickness of 100 to 500 nm n.
Type GaAs (carrier concentration 1 to 5 × 10 ¹⁷ cm ⁻³ ) active layer 3 and n ⁺ type GaAs 20 to 100 nm thick
An ohmic contact layer 4 having a carrier concentration of 1 to 3 × 10 ¹⁸ cm ⁻³ is laminated.

To grow this epitaxial layer,
First, the mirror-finished semi-insulating GaAs substrate 1 is subjected to sulfuric acid etching to remove impurities on the surface of the substrate 1. Then, MOVPE is formed on the substrate 1 in the growth furnace.
The buffer layer 2, the active layer 3, and the ohmic contact layer 4 are sequentially grown by using the method.

[0006]

However, when a field effect transistor is manufactured by providing a source electrode, a drain electrode, a gate electrode, etc. on an epitaxial wafer manufactured by the epitaxial crystal growth method described in the prior art, the epitaxial wafer Since a low resistance conductive layer exists at the interface between the semi-insulating substrate 1 and the epitaxial layer of
There is a problem that a leak current flows between the source electrode and the drain electrode through the conductive layer, which deteriorates the electrical characteristics of the transistor.

The cause of the formation of the low resistance layer (conductive layer) is that selenium (Se) originally remains in the growth furnace, and this Se is taken into the crystal during the epitaxial crystal growth to cause n-type carrier. This is because Residual Se in the growth furnace cannot be completely removed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a compound semiconductor epitaxial wafer capable of reducing the leak current between the source and drain electrodes and producing an element having good electric characteristics.

[0009]

In order to solve the above problems, the invention of claim 1 provides a compound semiconductor epitaxial wafer having a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, wherein A single-layer or multi-layer insulating layer is provided between the epitaxial layer and the epitaxial layer.

According to a second aspect of the invention, the insulating layer is AlGa.
It is made of As.

According to a third aspect of the present invention, the insulating layer has a thickness of 5
It is from 0 nm to 200 nm.

That is, according to the present invention, by providing the insulating layer made of AlGaAs between the GaAs substrate and the epitaxial layer, even if a low resistance layer exists between the substrate and the epitaxial layer, the insulating layer is formed between the source electrode and the drain electrode. It eliminates the leakage current.

According to the structure of claim 1, no current flows through the low resistance layer due to the insulating layer, and the leak current between the source electrode and the drain electrode is significantly reduced.

According to the structure of the second aspect, it can be formed by the MOVPE method like the epitaxial layer.

According to the structure of claim 3, the specific resistance is 1
It becomes MΩ · cm or more, and leak current can be sufficiently prevented.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a sectional view of an MESFET epitaxial wafer according to the present invention.

As shown in FIG. 1, the epitaxial wafer according to the present invention is 2 ° OFF (100) semi-insulating Ga.
As substrate 10, epitaxial layer 20 formed on this semi-insulating GaAs substrate 10, and these semi-insulating Ga
It is composed of an insulating Al _0.5 Ga _0.5 As layer 15 provided between the As substrate 10 and the epitaxial layer 20.

The epitaxial layer 20 comprises, in order from the substrate 10 side, a buffer layer 12 made of high-resistance undoped GaAs having a thickness of 500 nm and a Si-doped n having a thickness of 200 nm.
Type GaAs (carrier concentration 1.7 × 10 ¹⁷ cm ⁻³ ) active layer 13, Si-doped n ⁺ type Ga having a thickness of 50 nm
The ohmic contact layer 14 made of As (carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) is laminated.

The insulating Al _0.5 Ga _0.5 As layer 15 is composed of
Has been formed.

Next, the method of manufacturing this epitaxial wafer will be described together with its operation.

First, a semi-insulating GaA that is mirror finished
s Substrate 10 is subjected to sulfuric acid etching to remove impurities on the surface of substrate 10.

Further, the semi-insulating GaAs substrate 10 is housed in a growth furnace, and the inside of the furnace is heated to a predetermined temperature.

Then, triethylaluminum (TEA), triethylgallium (TEG) and arsine (AsH ₃ ) are flown into the growth furnace to form the semi-insulating layer GaAs.
An insulating AlGaAs layer (50% aluminum composition) 15 is grown on the substrate 10 to a thickness of 50 nm.

As a result, the specific resistance of the insulating layer 15 becomes 1 MΩ · cm or more, which can sufficiently prevent the leak current.

Further, similarly, the buffer layer 12, the active layer 13, and the ohmic contact layer 14 are sequentially grown by the MOVPE method to manufacture an epitaxial wafer.

In the element manufactured by providing the source electrode, the drain electrode, the gate electrode, etc. on the epitaxial wafer thus formed, no current flows through the low resistance layer due to the insulating layer 15, and the source electrode and the drain electrode are formed. The leakage current between and is greatly reduced.

Thus, a field effect transistor having excellent electric characteristics can be manufactured with a high device yield.

The insulating layer 15 is replaced with the epitaxial layer 20.
Since it can be formed by the MOVPE method similarly to the above, the number of steps is hardly increased and the manufacturing cost is not increased.

Next, the effect of reducing the leak current by the insulating layer of the present invention will be described.

First, as an example, three types of epitaxial wafers having insulating AlGaAs layers with thicknesses of 50, 100, and 200 nm were prepared, and as a comparative example, insulating AlGa was formed.
An epitaxial wafer in which the As layer was not inserted was also manufactured.

Further, source, gate and drain electrodes were provided on the surface of the epitaxial layers of these epitaxial wafers to fabricate FETs.

Then, the leak current between the source and the drain when a pinch-off voltage was applied to the gate electrode of this FET was examined.

Further, in order to examine the state of the surface of the epitaxial layer in these Examples and Comparative Examples, the surface was observed by AFM.

The results are shown in Table 1.

[0036]

[Table 1]

As shown in Table 1, FE with an insulating layer inserted
The leakage current of T is 15 to 16 μA, which is a conventional FET
Was very small as compared with 200 μA. Also, good electrical characteristics were obtained even with a thin film having an insulating layer thickness of 50 nm.

Further, it was found that the unevenness of the surface of the epitaxial layer improved the flatness of the example as compared with the comparative example.

From the above, it can be seen that by forming the insulating layer, the leak current can be greatly reduced and the surface of the epitaxial wafer can be flattened.

In the present embodiment, the field effect transistor epitaxial wafer has been described, but in addition to this, the present invention can be applied to a hetero bipolar transistor epitaxial wafer and an optical element epitaxial wafer. It is possible to manufacture an epitaxial wafer having good electric characteristics.

Further, in the present embodiment, GaAs is used as the semiconductor substrate and the GaAs epitaxial layer is grown, but it is not limited to GaAs as long as it is a III-V group compound semiconductor.

Needless to say, the thickness of the epitaxial layer of this embodiment is not limited to the above-mentioned thickness.

[0043]

In summary, according to the present invention, the source
A leak current between drains can be significantly reduced, and a field effect transistor with excellent characteristics can be manufactured with a high device yield.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an FET epitaxial wafer showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional FET epitaxial wafer.

[Explanation of symbols]

10 Semi-insulating GaAs substrate 12 High-resistance GaAs (buffer layer) 13 n-type GaAs (active layer) 14 n ⁺ type GaAs (ohmic contact layer) 15 Insulating Al _0.5 Ga _0.5 As layer 20 Epitaxial layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Takeuchi             Hitachi, 1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture             Electric Wire Co., Ltd. Hidaka Factory F-term (reference) 5F045 AA04 AB17 AC09 AC19 AF04                       CA02 CA06 DA62                 5F102 GB01 GC01 GD01 GJ05 GK05                       GL05 GR01 GR09 HC01 HC15

Claims (3)

[Claims] 1. A compound semiconductor epitaxial wafer having a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, wherein an insulating layer composed of a single layer or multiple layers is provided between the semiconductor substrate and the epitaxial layer. A compound semiconductor epitaxial wafer characterized in that 2. The compound semiconductor epitaxial wafer according to claim 1, wherein the insulating layer is made of AlGaAs. 3. The insulating layer has a thickness of 50 nm to 200 n.
The compound semiconductor epitaxial wafer according to claim 1, which is m.