JP2003031759A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit package which is improved so that multiplication of pins of a semiconductor package is realized without changing a pin pitch. SOLUTION: In a semiconductor package, external leads 11 and 12 are placed around the package in the top and bottom two steps or more in vertical direction. By placing an external connecting terminal for supplying power and inputting-outputting a control signal and data signal from an IC mounted on the semiconductor package, not only in a step around the package but also in two steps or more around the package, the external connecting terminal is prepared without forming fine pin pitch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor package, and more particularly, it relates to a semiconductor package improved so as to realize a multi-pin semiconductor integrated circuit.

[0002]

2. Description of the Related Art As ICs have been highly functionalized and highly integrated in recent years, there has been an increasing demand for semiconductor packages to have a large number of pins.

Conventionally, an IC package is a Quad shown in FIG.
Like the Flat Package (QFP), the external connection terminals for supplying power to the mounted IC and for inputting / outputting signals have only one step vertically from the outer edge of the package or alternately (staggered feet). Like), it has a structure in which two layers are arranged in the upper and lower layers, or I inside the package has three or more layers.
It has a structure in which C is arranged vertically.

[0004]

In the above-mentioned conventional IC package, in response to recent demands for acceleration of high integration of IC and increase in pin count, the pin pitch is being miniaturized, There is a problem in that it is technically difficult to realize a higher number of pins from the present stage on this extension line in the soldering process at the time of mounting.

Further, the structure in which the ICs inside the package are arranged vertically has a problem that the heat generation of the ICs increases the heat generation of the entire package.

The present invention has been made in order to solve the above problems, and provides an improved semiconductor package so that the pin pitch can be maintained and the number of pins of the semiconductor package can be increased. The purpose is to

[0007]

According to the semiconductor package of the present invention, the external leads are vertically arranged in the upper and lower two stages or more at the outer periphery of the package.

According to a preferred embodiment of the present invention, a part of the external lead is used for heat dissipation or noise resistance. The internal ICs are arranged in parallel.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor integrated circuit package according to the first embodiment. Referring to FIG. 1, semiconductor integrated circuit package 10 has ICs 13 and 14 mounted thereon. The external connection terminals 11 and 12 are for supplying power to the ICs 13 and 14 and for inputting and outputting control signals and data signals. The ICs 13 and 14 in the package are arranged in parallel.

The semiconductor package according to this embodiment is
The external leads of the QFP shown in FIG. 7, which is a conventional package, are characterized by a structure in which they are vertically arranged in two steps in the vertical direction at the outer edge of the package. Here, in particular, the case where the external connection lower terminal 11 on the outer edge of the package 10 is used as a signal terminal and a ground potential terminal, and the external connection upper terminal 12 is used as a power supply terminal and a ground potential terminal will be described as an example.

Power is supplied to the semiconductor integrated circuit mounted in the semiconductor package 10 from the external connection upper terminal 12 of the package, and control signals and data signals are input and output from the external connection lower terminal 11 of the package.

FIG. 2 shows that the external connection lower terminal of the semiconductor integrated circuit package shown in FIG.
FIG. 9 is a cross-sectional view of another specific example of the present embodiment having a (LCC) structure.

Also in the case of this embodiment, as in the embodiment shown in FIG. 1, the ICs 13 and 14 mounted on the semiconductor integrated circuit package 10 are supplied with power from the external connection upper terminal 12 of the package, A control signal and a data signal are input and output from the externally connected lower terminal 11 at the outer edge of the package.

As in the embodiment shown in FIG. 1 or 2, the external connection terminals for supplying power and inputting / outputting signals to / from the IC are provided one step from the outer edge as in the conventional package shown in FIG. Not only that, by arranging the semiconductor device in upper and lower two stages, it is possible to obtain more external connection terminals than the conventional type package without miniaturizing the pin pitch of the semiconductor package. The pinning requirement can be realized.

Further, as described in the embodiment of FIG. 1 or 2, the external connection terminals are provided on the upper edge of the outer edge of the package and the lower edge of the outer edge of the package, and the power supply terminal, the other signal terminals, and the package. It is possible to obtain advantages depending on the usage, such as preventing accidents such as IC destruction due to signal-power short circuit due to mounting mistakes by using them independently, such as the upper edge of the outer edge and the lower edge of the package. .

FIG. 3 is a sectional view of an embodiment in which the external connection terminal 12 of the semiconductor integrated circuit package shown in FIG. 2 has an LCC structure.

Also in the case of this embodiment, FIG. 1 and FIG.
The semiconductor integrated circuit package 10 is similar to the embodiment described above.
Power is supplied to the IC mounted in the package from the external connection upper terminal 12 of the package, and control signals and data signals are input and output from the external connection terminals 11 at the outer peripheral edge of the package.

Although the case where the external connection terminals on the outer peripheral edge of the package are used as signal terminals and the external connection terminals on the bottom surface of the package are used as power supply terminals has been described here, the method of using the external connection terminals is arbitrary and is not limited. .

Although the number of external connection terminals has been described as two, the number of external connection terminals can be three or more, and the number of steps can be changed at each outer edge of the package.

Further, although the case where the number of ICs mounted inside is two is shown here, the number of ICs is not limited to two, and the same applies to three or more.

Further, as for the internal wiring 15, which IC is connected to which terminal as shown in FIG. 4 is free and is not limited.

Further, it is not necessary that the thickness of the IC inside is the same. Further, although the present invention is basically based on arranging the ICs in parallel, even if some or all of the ICs arranged in parallel are arranged vertically as shown in FIG. High pin count can be realized. IC5 in the figure
5 and the IC 13 are arranged vertically.

Although the QFP and LCC structures have been described above as an example of the external connection terminal structure at the outer edge of the package, the dual inline package (DIP), Tape Au are described.
Similar effects can be obtained with other package structures such as tomated bonding (TAB).

Embodiment 2 FIG. 6 shows a ball grid array in a semiconductor integrated circuit package.
It is sectional drawing at the time of applying (BGA). here,
Although an example of BGA is shown, a Pin Grid Array (PGA) may be used. With this configuration, it becomes easier to increase the number of pins.

Embodiment 3 In the semiconductor package constructed as described above, the external leads are used for heat resistance and noise resistance. With this configuration, it is possible to obtain an effect of being resistant to heat generation and noise.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0028]

As described above, according to the present invention,
By arranging the external connection terminals for supplying power and inputting / outputting the control signal and the data signal to / from the IC mounted on the semiconductor package not only on the outer peripheral edge of the package but also on the outer peripheral edge of the package in two steps or more There is an effect that an external connection terminal can be prepared without reducing the pin pitch. Further, even if the ICs arranged in the package have different functions such as a microcomputer and a memory, the external terminals can be separated, which is advantageous in that they can be used safely.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor package according to a first embodiment.

FIG. 2 is a cross-sectional view of a semiconductor integrated circuit package according to another specific example of the first embodiment.

FIG. 3 is a sectional view of a semiconductor integrated circuit package according to still another specific example of the first embodiment.

FIG. 4 is a sectional view of a semiconductor integrated circuit package according to still another specific example of the first embodiment.

FIG. 5 is a sectional view of a semiconductor integrated circuit package according to still another specific example of the first embodiment.

FIG. 6 is a sectional view of a semiconductor integrated circuit package according to a second embodiment.

FIG. 7 is a conceptual diagram of a conventional semiconductor integrated circuit package.

[Explanation of symbols]

10 semiconductor integrated circuit package, 11, 12 external connection terminals, 13, 14 IC, 15 internal wiring.

Claims (3)

[Claims] 1. A semiconductor package in which external leads are vertically arranged in two steps or more or more at the outer edge of the package. 2. The semiconductor package according to claim 1, wherein a part of the external lead is used for heat dissipation or noise resistance. 3. The semiconductor package according to claim 1, wherein the internal ICs are arranged in parallel.