JP2003031721A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce coupling of signal lines without enlarging a size. SOLUTION: One terminal of a signal line 22A is connected to a semiconductor chip 25 by a bonding wire 26A, and the other terminal is connected to a via hole 28. One terminal of a passive component 29 such as capacitor, for example, is connected to the signal line 22A. The other terminal of the passive component 29 is connected through a via hole 30A to a ground layer 23. The ground layer 23 is provided with a slit 31. The slit 31 divides two via holes 30A. The slit 31 is extended from the terminal part of the ground layer 23 to a portion just under the semiconductor chip 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module, and more particularly to a microminiature high frequency semiconductor module using a multilayer substrate.

[0002]

2. Description of the Related Art In recent years, in order to realize miniaturization of mobile terminal equipment, miniaturization of parts thereof has been rapidly advanced.
As one of the technologies developed for miniaturization of components, a micro module technology using a multi-layer board is known. Using this technology, MMIC (Monolithic Microwave Integrated
The mounting area can be significantly reduced compared to the case where Circuit) and chip parts are mounted.

11 and 12 show an example of a mother board and a conventional semiconductor module mounted on the mother board.

The mother board 10 is generally composed of a multilayer substrate 11. The pattern of the signal line 12 is drawn on the upper surface of the multilayer substrate 11. One of the plurality of layers between the multilayer substrates 11 is a ground layer (ground layer) 13. The ground layer 13 is formed in a plate shape over the entire space between the multilayer substrates 11 so as to form an ideal ground plane.

A semiconductor module 20 is mounted on the upper surface of the mother board 10, for example, at a position surrounded by a broken line.
The semiconductor module 20 includes a multilayer substrate 21 and a semiconductor chip (eg, MMIC chip) 25 mounted on the multilayer substrate 21.
And bonding wires 26A and 26B.

On the upper surface of the multi-layer substrate 21, the pattern of the signal line 22A and the pattern of the bed 24 are drawn. A semiconductor chip 25 is mounted on the bed 24. The signal electrode of the semiconductor chip 25 and the signal line 22A are electrically connected by the bonding wire 26A. Signal line 2
2A is a via hole (via) formed in the multilayer substrate 21.
via the hole) 28 and is electrically connected to the signal line 12 on the upper surface of the motherboard 10.

Ground electrode of semiconductor chip and bed 24
And are electrically connected by a bonding wire 26B. One of the plurality of layers between the multilayer substrates 21 is a ground layer (ground layer) 23. Ground layer 23
Are formed in a plate shape over the entire space between the multilayer substrates 21 so as to form an ideal ground plane.

The bed 24 and the ground layer 23 are electrically connected by a via hole 27 formed in the multilayer substrate 21. In addition, the ground layer 2 of the semiconductor module 20
3 is electrically connected to the ground layer 13 of the motherboard 10 via the via holes 14 and 28.

As described above, the conventional semiconductor module 20
Has a multilayer substrate 21. This is because the module can be downsized by using the multilayer substrate 21. That is, the semiconductor chip 25 in recent years has been remarkably multifunctional, and the number of terminals thereof has become extremely large. Therefore, the number of signal lines 22A increases, and the signal lines 22A are long and thin.

By using the multi-layer substrate 21 to form a plurality of wiring layers, it is possible to prevent the module size from increasing even if the number of signal lines 22A increases.

Next, a microminiature high frequency semiconductor module will be described as a general example of a semiconductor module using a multilayer substrate.

FIG. 13 shows an example of a high frequency semiconductor module.

The multilayer substrate 21 is composed of, for example, three dielectric layers and a total of four metal layers formed between the respective dielectric layers and on the upper surface and the lower surface of the multilayer substrate 21, respectively. The first metal layer formed on the upper surface of the multilayer substrate 21 mainly constitutes the signal line 22A for high frequency signals. To the signal line 22A, one end of a passive component (capacitance element in this example) 29 normally composed of L (inductance element), C (capacitance element), and R (resistance element) is connected.

On the upper surface of the multi-layer substrate 21, a metal pattern 22B and a bed 24 as a ground layer are formed in addition to the signal line 22A. The other end of the passive component 29 is connected to the metal pattern 22B. A semiconductor chip (eg, MMIC chip) 25 is mounted on the bed 24.

Signal electrodes of the semiconductor chip 25 and the signal lines 22
A is electrically connected to A by a bonding wire 26A. The signal line 22A is electrically connected to the signal line of the motherboard via the via hole 28 formed in the multilayer substrate 21. The ground electrode of the semiconductor chip and the bed 24 are electrically connected by the bonding wire 26B.

The second metal layer formed between the multilayer substrates 21 and adjacent to the first metal layer constitutes the ground layer 23 so that the signal line 22A becomes a microstrip line.
The ground layer 23 is formed in a plate shape so as to form an ideal ground plane. The metal pattern 22B is electrically connected to the ground layer 23 via the via hole 30A. The bed 24 is electrically connected to the ground layer 23 via the via hole 27.

The third metal layer formed between the multi-layer substrates 21 mainly constitutes a line for DC bias. Further, the lower surface of the multilayer substrate 21, that is, the fourth metal layer formed on the back surface of the module constitutes an electrode pattern. The electrode pattern is for making contact with the electrodes on the motherboard.

[0018]

A problem in the semiconductor module as shown in FIG. 13 is that the ground layer 23 does not become an ideal ground plane. That is, the ground layer 2
As shown in FIG. 14, 3 is connected to the ground layer 13 of the motherboard via the via holes 14 and 28.
However, finite parasitic inductance exists in the via holes 14 and 28. Further, if the number of via holes 14 and 28 is increased infinitely, the ground layer 23 can be made to have an ideal ground potential, but in reality, due to the structure of the module, only a limited number of via holes 14 and 28 are arranged. I can't.

Therefore, the induced current generated in the ground layer 23 is not easily absorbed in the via holes 14 and 28, and the ground layer 23 of the semiconductor module is in a floating state, and the ground layer 23 does not serve as an ideal ground surface. The influence of the coupling between the signal lines 22A becomes large.

Qualitatively consider this problem.

First, two microstrip lines (Li
The coupling between ne1 and Line2) can be considered by decomposing into the following three.

Coupling between Currents Flowing in Line 1 and Line 2 Coupling between Induced Current Generated in the Ground Layer and Current Flown in Line 2 Induced Current Generated in the Ground Layer and Flowed in Line 1 Coupling with current As long as Line1 and Line2 are microstrip lines,
The couplings of and occur by necessity. That is, Line1 and Line2 are, for example, as shown in FIG. 15, a microstrip line 22A formed in pairs with a common ground plane immediately thereunder, and the ground layer 23 of the semiconductor module is formed of Line1 and Line2. Play the role of return path. If the ground layer 23 is an ideal ground plane, the density of the induced current generated in the ground layer 23 is Li
Directly below ne1 and Line2 is the largest, and becomes smaller with increasing distance from Line1 and Line2.

On the other hand, in the actual module, Line
The induced current generated in the ground layer 23 by the currents flowing in 1 and Line 2 flows to the end surface of the ground layer 23, and this time, flows along the end surface. Ground layer 2
Since the via holes 14 and 28 provided in 3 are electrically distant paths as return paths (paths through which return currents flow), almost no induced current flows and they do not have a function of absorbing induced currents.

As described above, in the actual semiconductor module, due to the existence of the induced current flowing along the end surface of the ground layer 23, the gap between the microstrip lines is smaller than that when the ground layer 23 is the ideal ground plane. The coupling effect is very large.

In order to avoid such a phenomenon, the number of via holes 14 and 28 is increased as much as possible to bring the ground layer 23 close to the ideal ground potential, and the induced current generated in the ground layer 23 is immediately applied to the via holes 14 and 28. It is necessary to absorb.

However, as described above, due to the structure of the semiconductor module, only a limited number of via holes 14 and 28 can be provided, and the number of via holes is reduced in order to achieve the recent miniaturization of the module. In the direction.

The present invention has been made to solve such a problem, and an object thereof is to increase coupling between signal lines due to the ground layer of a semiconductor module being in a floating state. To avoid the increase in the module size due to the increase in the number of via holes.

[0028]

A semiconductor module of the present invention comprises a first ground layer disposed on one of a plurality of metal layers of a multi-layer substrate and another one of the plurality of metal layers.
First and second signal lines that form a transmission line by forming a pair with the first ground layer, and a first portion of the first ground layer that faces the first signal line. The second of the first ground layer facing the second signal line
A slit is provided between the part and the part.

The first passive component is connected between the first signal line and the first portion, and the second passive component is connected between the second signal line and the second portion. However, the connection point between the first passive component and the first portion is separated from the connection point between the second passive component and the second portion by the slit.

A first via hole for contacting the second ground layer of the motherboard is connected to the first portion, and a second via hole for contacting the second ground layer is connected to the second portion. To be done.

The first via hole is arranged at an end of the first ground layer and at a portion overlapping with the first signal line, and the second via hole is formed at an end of the first ground layer. And, it is arranged in a portion overlapping with the second signal line.

A third via hole for contacting a third signal line of the motherboard is connected to an end of the first signal line, and a fourth signal of the motherboard is connected to an end of the second signal line. A fourth via hole for contacting the line is connected.

The first signal line is paired with the first portion, the third via hole is paired with the first via hole, and the second signal line is paired with the second portion. The fourth via hole is paired with the second via hole,
The third and fourth signal lines form a pair with the second ground layer to form a transmission line.

A bed on which a semiconductor chip is mounted is arranged on the other one of the plurality of metal layers, and the bed and the third portion are formed on a third portion of the first ground layer facing the bed. Only the via hole that electrically connects the portion is arranged.

The slit extends from the end of the first ground layer to the third portion. The slit is
The first and second parts are electrically separated from each other. The slit is a hole.

Microwaves are transmitted to the first and second signal lines.

A system of the present invention comprises the above-mentioned semiconductor module and a mother board on which the semiconductor module is mounted.

[0038]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor module of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a mother board and a semiconductor module according to the present invention mounted on the mother board. Figure 2
Shows the semiconductor module of FIG.

The mother board 10 is composed of a multi-layer substrate 11. The pattern of the signal line 12 is drawn on the upper surface of the multilayer substrate 11. One of the plurality of layers between the multilayer substrates 11 is a ground layer (ground layer) 13.
The ground layer 13 is formed in a plate shape over the entire space between the multilayer substrates 11 so as to form an ideal ground plane.

The semiconductor module 20 is mounted on the upper surface of the mother board 10 at a position surrounded by a broken line, for example.
In this example, the semiconductor module is premised on a high frequency semiconductor module.

The semiconductor module 20 includes a multilayer substrate 21.
And a semiconductor chip mounted on the semiconductor chip (for example, MMIC
Chip) 25, and bonding wires 26A and 26B for electrically connecting the multilayer substrate 21 and the semiconductor chip 25.

On the upper surface of the multi-layer substrate 21, the pattern of the signal line 22A and the pattern of the bed 24 are drawn. A semiconductor chip 25 is mounted on the bed 24. The signal electrode of the semiconductor chip 25 and the signal line 22A are electrically connected by the bonding wire 26A. Signal line 2
2A is a via hole (via) formed in the multilayer substrate 21.
via the hole) 28 and is electrically connected to the signal line 12 on the upper surface of the motherboard 10.

Ground electrode of semiconductor chip and bed 24
And are electrically connected by a bonding wire 26B. One of the plurality of layers between the multilayer substrates 21 is a ground layer (ground layer) 23. Ground layer 23
Are formed between the multilayer substrates 21 as planes having slits, as will be described later.

The bed 24 and the ground layer 23 are electrically connected by a via hole 27 formed in the multilayer substrate 21. In addition, the ground layer 2 of the semiconductor module 20
3 is electrically connected to the ground layer 13 of the motherboard 10 via a via hole.

The multilayer substrate 21 of the semiconductor module 20 is
For example, it is composed of three dielectric layers and a total of four metal layers formed between the respective dielectric layers and on the upper surface and the lower surface of the multilayer substrate 21, respectively. The first metal layer formed on the upper surface of the multilayer substrate 21 is mainly used for the signal line 2 for high frequency signals.
Make up 2A. The signal line 22A usually has L, C, R
One end of a passive component (capacitive element in this example) 29 such as is connected.

On the upper surface of the multilayer substrate 21, a metal pattern 22B and a bed 24 as a ground layer are formed in addition to the signal line 22A. The other end of the passive component 29 is connected to the metal pattern 22B. A semiconductor chip 25 is mounted on the bed 24.

The second metal layer formed between the multilayer substrates 21 and adjacent to the first metal layer constitutes the ground layer 23 so that the signal line 22A becomes a microstrip line.
The third metal layer formed between the multilayer substrates 21 mainly constitutes a line for DC bias. In addition, the fourth surface formed on the lower surface of the multilayer substrate 21, that is, the back surface of the module.
The metal layer constitutes an electrode pattern.

FIG. 3 shows an outline of the semiconductor module of the present invention.

A feature of the semiconductor module of the present invention resides in the ground layer 23 arranged immediately below the signal line 22A so that the signal line 22A becomes a microstrip line.

The problem with the conventional semiconductor module is that
The ground layer was not the ideal ground plane.
That is, the ground layer is connected to the ground layer of the motherboard via the via hole. However, there is a finite parasitic inductance in the via holes, and the number of via holes can be limited to a limited number because of the structure of the module.

Therefore, the induced current generated in the ground layer is
It did not flow into the via hole as a return current, but was distributed on the end face of the ground layer in a state where the current density was high, and as a result, the influence of the coupling between the signal lines became large ( Couplings described and.

Further, due to the recent miniaturization of the module, the number of via holes provided in the module is limited, and it is very difficult to immediately absorb the induced current generated in the ground layer of the semiconductor module into the via hole. Is.

Therefore, in the present invention, while it is acceptable that the potential of the ground layer for forming the microstrip line is in a floating state, as shown in FIG.
As a general rule, the ground layer 23 is provided for each signal line 22A so that the induced current generated in the ground layer 23 by the current flowing through one signal line 22A does not affect the current flowing through another signal line 22A. To do.

The plurality of ground layers 23 provided corresponding to the plurality of signal lines 22A may be electrically connected to each other or may be electrically separated from each other. When a plurality of ground layers 23 are electrically connected to each other, the connection points are thinned to have a high resistance so that the induced current generated in one ground layer 23 does not flow to the other ground layers 23. It is necessary to devise such as doing.

According to such a semiconductor module, the induced current generated in the ground layer 23 by the current flowing through the one signal line 22A will flow along the end surface of the ground layer when it reaches the end surface. The ground layer 23
Corresponds to only one signal line 22A and does not serve as a ground layer for the other signal line 22A.
It does not affect the current flowing through A.

That is, since the influence of the coupling due to and explained in the item of the problem to be solved by the invention can be reduced, as a result, the influence of the coupling between the signal lines can be greatly reduced.

FIGS. 4 and 5 correspond to the semiconductor module of FIG. 2 and show in detail the characteristic portions of the present invention.

The signal line 22A, the metal pattern 22B and the bed 24 are formed on the upper surface of the multilayer substrate 21, that is, on the first metal layer.

A passive component (for example, a capacitive element) 29 is arranged across the signal line 22A and the metal pattern 22B. The metal pattern 22B is connected to the ground layer 23 formed in the second metal layer immediately below the first metal layer via the via hole 30A.

Here, in the present invention, firstly, the slit 31 is formed in the ground layer 23. Slit 31
Extends from the end surface of the ground layer 23 to a portion directly below the bed 24 on which the semiconductor chip is mounted. That is, the slit 31 includes a portion of the ground layer 23 immediately below one signal line 22A (particularly, a contact portion of the via hole 30A to which one end of the passive component 29 is connected) X, and a ground layer directly below another signal line 22A. The portion 23 (particularly, the contact portion of the via hole 30A to which one end of the passive component 29 is connected) Y is separated.

Thus, the slits 3 are formed in the ground layer 23.
By providing 1, the configuration as shown in FIG.
Ground layer 2 for forming a microstrip line
It is possible to obtain a configuration similar to the configuration in which 3 is provided for each signal line 22A.

Therefore, even if the ground layer 23 corresponding to one signal line 22A floats, it is possible to reduce the influence on the current flowing through the other signal line 22A. The increase in coupling between lines can be avoided without increasing the module size due to the increase in the number of via holes.

Secondly, in the present invention, the slit 31
At least one (in this example, one) via hole 3 is provided in each of the portions X and Y of the ground layer 23 divided by
0B is connected. The via hole 30B is connected to the ground layer 13 in the motherboard via the electrode 32 formed on the back surface of the semiconductor module and the via hole 30C in the motherboard.

The bed 2 on which the semiconductor chip is mounted
4 is directly connected to the ground layer 23 of the semiconductor module, and the via hole 1 is formed in the ground layer 13 of the motherboard, as in the conventional case (FIG. 14).
No connection is made via 4, 28.

That is, according to the present invention, the connection point between the ground layer of the semiconductor module and the ground layer of the mother board is
It is provided only in the portions X and Y divided by the slit 31. This point will be described.

FIG. 6 shows a sectional view of a system including a mother board and the semiconductor module of the present invention.

In the present invention, slits are provided in the ground layer 23 of the semiconductor module, and the portions of the ground layers 23 corresponding to the signal lines 22A are formed.

In this case, for example, if a via hole connecting the ground layer 23 of the semiconductor module and the ground layer 13 of the mother board is provided only under the bed 24 on which the semiconductor chip 25 is mounted, as in the conventional case (FIG. 12). ,
The potential of each part of the ground layer 23 greatly deviates from the ideal ground potential, and the induced current generated in one part is transferred to the other part via the part of the ground layer 23 immediately below the bed 24. Can be considered.

Therefore, in the present invention, as shown in FIG.
Via holes 30B and 30C for connecting the ground layer 23 of the semiconductor module and the ground layer 13 of the motherboard
Is provided at each of the portions divided by the slits.

According to this structure, the ground layer 23
The induced current generated in one part does not affect the other part of the ground layer 23. Also, the signal line 22A
And ground layer 23, via hole 28 and via hole 30
B, 30C, and the signal line 12 and the ground layer 13 are
Since each of them constitutes a transmission line, it does not hinder the transmission of high frequency signals.

As described above, according to the semiconductor module of the present invention, the ground layer exists for each signal line even if the ground layer is in a floating state. The induced current does not affect the currents of other signal lines, and as a result, an increase in coupling between signal lines can be avoided without increasing the module size due to an increase in the number of via holes.

In this example, an example in which only one slit is provided in the ground layer of the semiconductor module has been described, but it goes without saying that a plurality of slits are formed in the ground layer according to the number of signal lines. You may. Further, the size, shape, position, etc. of the slit are not particularly limited, but are determined in consideration of facilitation of manufacturing, layout of signal lines, and the like.

Further, the via hole for connecting the ground layer of the semiconductor module and the ground layer of the mother board is preferably provided at the end of the ground layer of the semiconductor module and immediately below the high frequency signal line.

7 to 9 show application examples of the semiconductor module of the present invention. In these figures, the ground layer 23, which is a characteristic part of the present invention, is mainly shown.

In the example of FIG. 7, the ground layer 23 is provided with four slits 31. Each slit 31 extends from the end of the ground layer 23 toward a portion directly below the semiconductor chip 25. The signal line 22A and the ground layer 23 form a microstrip line. In addition, in each part of the ground layer 23 divided by the slit 31,
Via holes 30B and 30C are connected.

In the example of FIG. 8, four slits 31 are provided in the ground layer 23 as in the example of FIG. However, one end of each slit 31 does not reach the end of the ground layer 23, and each slit 31 is a hole. Other points are the same as in FIG. 7.

In the example of FIG. 9, the ground layer is electrically separated into five parts, and the ground layers 23A, 23B, 23
It is C, 23D, and 23E. The four ground layers 23A, 23B, 23C and 23D in the peripheral portion are respectively
Via holes 30B and 30C are connected to the ground layer of the motherboard. The central ground layer 23E on which the semiconductor chip is mounted is connected to the ground layer of the motherboard by the via holes 14 and 28.

As shown in FIG. 10, the ground layer 2
3A, 23B, 23C, 23D and 23D are respectively
Via holes VH1, VH2, VH3, VH4
It is electrically connected to the metal patterns M1, M2, M3, M4 of the metal layer (first metal layer) on the module surface. The metal patterns M1, M2, M3, M4 are electrically connected to the ground pads P1, P2, P3, P4 on the semiconductor chip 25 by bonding wires, respectively.

[0080]

As described above, according to the semiconductor module of the present invention, the ground layer is provided with the slit. The slit divides the ground layer of the semiconductor module into a plurality of parts. Then, one signal line is arranged corresponding to one portion of the ground layer.

In this case, the induced current generated in the portion of the ground layer corresponding to the one signal line by the current flowing in the one signal line passes through the contact portion provided for each portion of the ground layer to the motherboard. Is absorbed by the ground layer and does not reach the ground layer corresponding to other signal lines, so that the coupling between the signal lines can be reduced.

As described above, in the semiconductor module of the present invention, even if the ground layer is in a floating state, the increase in the coupling between the signal lines can be suppressed without increasing the module size due to the increase in the number of via holes. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a mother board and a semiconductor module of the present invention.

FIG. 2 is a diagram showing a semiconductor module of the present invention.

FIG. 3 is a diagram showing the principle of the present invention.

FIG. 4 is a diagram showing a characteristic part of a semiconductor module of the present invention.

FIG. 5 is a diagram showing a characteristic part of a semiconductor module of the present invention.

FIG. 6 is a diagram showing a system including a mother board and the semiconductor module of the present invention.

FIG. 7 is a diagram showing an application example of the semiconductor module of the present invention.

FIG. 8 is a diagram showing an application example of the semiconductor module of the present invention.

FIG. 9 is a diagram showing an application example of the semiconductor module of the present invention.

FIG. 10 is a diagram showing an application example of the semiconductor module of the present invention.

FIG. 11 is a diagram showing a mother board and a conventional semiconductor module.

FIG. 12 is a diagram showing a system including a mother board and a conventional semiconductor module.

FIG. 13 is a diagram showing a main part of a conventional semiconductor module.

FIG. 14 is a diagram showing a main part of a conventional semiconductor module.

FIG. 15 is a diagram showing a main part of a conventional semiconductor module.

[Explanation of symbols]

10: Mother board, 11, 21: Multilayer substrate, 12, 22A: Signal line, 13, 23, 23A to 23E: Ground layer, 14, 15, 27, 28, 30A, 30B, 30C:
Via hole, 20: Semiconductor module, 22B: Metal pattern, 24: Bed, 25: Semiconductor chip, 26A, 26B: Bonding wire, 29: Passive component, 31: Slit, 32: Electrode.

Claims (12)

[Claims] 1. A first ground layer disposed on one of a plurality of metal layers of a multilayer substrate, and a first ground layer disposed on another one of the plurality of metal layers and paired with the first ground layer. And a first signal line and a second signal line that form a transmission line, and the first portion of the first ground layer facing the first signal line and the first signal line facing the second signal line. A semiconductor module, wherein a slit is provided between the ground layer and the second portion. 2. A first passive component connected between the first signal line and the first portion, the second signal line and the second passive component.
A second passive component connected between the second passive component and the second portion, the connection portion between the first passive component and the first portion being connected by the slit to the second passive component and the second portion. The semiconductor module according to claim 1, wherein the semiconductor module is separated from the place. 3. The second portion of the motherboard is attached to the first portion.
2. The semiconductor module according to claim 1, wherein a first via hole for contacting a ground layer is connected, and a second via hole for contacting the second ground layer is connected to the second portion. . 4. The first via hole is arranged at an end of the first ground layer and at a portion overlapping with the first signal line, and the second via hole is the first via hole.
4. The end portion of the ground layer and the portion overlapping with the second signal line are arranged.
The semiconductor module described. 5. A third via hole for contacting a third signal line of the motherboard is connected to an end of the first signal line, and an end of the second signal line is connected to a third via hole of the motherboard. The semiconductor module according to claim 4, wherein a fourth via hole for contacting the four signal lines is connected. 6. The first signal line forms a pair with the first portion, the third via hole forms a pair with the first via hole, and the second signal line forms a pair with the second portion. None,
The fourth via hole may be paired with the second via hole, and the third and fourth signal lines may be paired with the second ground layer to form a transmission line. The semiconductor module according to claim 5. 7. A bed on which a semiconductor chip is mounted is disposed on the other one of the plurality of metal layers, and the bed and the bed are provided on a third portion of the first ground layer facing the bed. The semiconductor module according to claim 1, wherein only via holes electrically connecting to the third portion are arranged. 8. The semiconductor module according to claim 7, wherein the slit extends from an end of the first ground layer to the third portion. 9. The slit electrically separates the first and second portions from each other.
The semiconductor module described. 10. The semiconductor module according to claim 1, wherein the slit is a hole. 11. The semiconductor module according to claim 1, wherein microwaves are transmitted to the first and second signal lines. 12. The semiconductor module according to claim 1,
And a motherboard on which the semiconductor module is mounted.