JP2003031568A - Method of manufacturing semiconductor device, and the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, using a coating which has small stress as an insulation film, with proper embedding ability in a trench and so on, and low density in the trench. SOLUTION: Since heat treatment is applied on higher-order silane, which is expressed by any of the chemical formulas Sin H2n , Sin H2n+2 , and Si6+4n H12+6n (n is an integer of 1 or more), in an atmosphere containing oxygen, decomposition and oxidation of the higher order silane is developed, to form a silicon oxide thin film 3. The silicon oxide film is used as an embedded material and an interlayer insulating film of a trench 5 which is formed on the principle surface of a semiconductor substrate 1. A silicon oxide film (SiO2 ), made of the higher order silane, is far smaller in stress than a conventional oxide film, hardly causes warpage, has proper embedding ability, and is smaller in density of the trench than an interlayer insulation film which is formed on the flat principle surface of the semiconductor substrate, thereby achieving low relative permittivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device formed by this method,
In particular, the present invention relates to a novel material for burying an element isolation groove or forming an interlayer insulating film.

[0002]

2. Description of the Related Art At present, in semiconductor devices, a method of forming an element isolation region by STI (Shallow Trench Isolation) is often used as an element isolation technique. Then, as an insulating material embedded in the trench, TEOS /
O ₃ or HDP is used. FIG. 11 is a process cross-sectional view of forming a conventional STI type element isolation region.
CMP is performed on the main surface of the semiconductor substrate 101 such as silicon.
A silicon nitride film (SiN film) 102, which serves as a stopper film during (Chemical Mechanical Polishing), is formed. A trench (groove) 103 is formed on this main surface by RIE (Reactive Ion Etching) or the like. The diameter of the trench 103 is 0.08 to 0.1 μm, and the aspect ratio is 5 or more (FIG. 11A). Next, a TEOS film 104 is formed on the semiconductor substrate 101 so as to cover the buried silicon nitride film 102 inside the trench 103 (FIG. 11B). Next, using the silicon nitride film 102 as a stopper, the TEOS film 10 on the surface of the semiconductor substrate 101.
4 is subjected to CMP treatment to flatten the surface of the semiconductor substrate 101. The TEOS film 104 on the silicon nitride film 102 is removed, and the TEOS film 104 is embedded in the trench 103 (FIG. 11C). The same is true for HDP.

[0003]

However, TEOS / O
No. ₃ has good embeddability but poor oxide film quality 11
HDP, which requires high-temperature densification of 00 ° C. or higher, has a problem that the film quality is close to that of a thermal oxide film, but the filling property is poor. Further, although TEOS is often used as an interlayer insulating film, a ferroelectric capacitor is particularly subject to process damage due to H ₂ generated during TEOS film formation, plasma damage, or film stress generated during activation annealing. There was a problem.
Further, when miniaturization progresses, if the dielectric constant of the filling material is high, there is a possibility of inter-cell capacitive coupling in which cells to be separated are connected via the embedded separation groove. As a material, a material having a dielectric constant as low as possible, that is, a material having a low density is desired. The present invention has been made under such circumstances, and a method of manufacturing a semiconductor device using a coating film having a small stress as an insulating film, a good filling property in a trench or the like, and a low density in the trench, and A semiconductor device is provided.

[0004]

The present invention is based on Si
_{n H 2n, Si n H 2n} + 2 or _{Si 6 + 4n} H
_{12 + 6 n} (n is a positive number of 1 or more) is subjected to heat treatment in an atmosphere containing oxygen to cause a decomposition reaction and an oxidation reaction of the higher order silane to cause silicon oxidation. It is characterized in that a film is formed and is used as a filling material for a trench formed in the main surface of a semiconductor substrate or an interlayer insulating film. The silicon oxide film (SiO ₂ ) formed from this high-order silane is a method of forming a silicon oxide film using a novel material, and has a stress that is significantly smaller than that of a conventional oxide film and has almost no warp.
Further, it has the characteristics that it has a good burying property in the trench and the density in the trench is smaller than that of the interlayer insulating film of the same material formed on the flat main surface of the semiconductor substrate, and thus the relative dielectric constant is small. That is, the method for manufacturing a semiconductor device according to the present invention is applied to Si _n H _2n , Si _n H _{2n + 2} and Si _n H _{2n.
6 + 4n} H _{12 + 6n} (n is a positive number of 1 or more), a step of applying a solution containing a high-order silane represented by any one of the chemical formulas onto a semiconductor substrate, and heat-treating the semiconductor substrate in an atmosphere containing oxygen. Accordingly, a step of causing a decomposition reaction and an oxidation reaction of the higher order silane to form a silicon oxide film on the semiconductor substrate is provided. The solution may contain a solvent in which the higher order silane is dissolved.

The method of manufacturing a semiconductor device according to the present invention is
Si _n H _2n , Si _n H _{2n + 2} and Si _{6 + 4n} H
_{12 + 6n} (n is a positive number of 1 or more) represented by any one of the chemical formulas, a step of applying a solution containing a high-order silane dissolved in a solvent onto a semiconductor substrate, and oxygen of the semiconductor substrate is eliminated as much as possible. A step of evaporating the solvent contained in the solution by performing a first heat treatment in an atmosphere; and a second heat treatment in an atmosphere containing oxygen in the semiconductor substrate at a temperature higher than that of the first heat treatment. By doing so, a step of causing a decomposition reaction and an oxidation reaction of the higher order silane to form a silicon oxide film on the semiconductor substrate is provided. A method of manufacturing a semiconductor device of the present _{invention, Si n H 2n, Si n} H 2n + 2 , and S
i _{6 + 4n} H _{12 + 6n} (n is a positive number of 1 or more), and a step of applying a solution containing a high-order silane dissolved in a solvent onto the semiconductor substrate; A step of evaporating the solvent contained in the solution by performing a first heat treatment in an atmosphere in which oxygen is eliminated as much as possible; and an atmosphere containing oxygen in the semiconductor substrate at a temperature higher than that of the first heat treatment. Performing a second heat treatment to cause a decomposition reaction and an oxidation reaction of the higher order silane to form a silicon oxide film on the semiconductor substrate; and a step of forming the semiconductor substrate at a temperature higher than that of the second heat treatment by a third heat treatment. And a step of hardening the silicon oxide film by heat treatment. The atmosphere in which the oxygen is exhausted as much as possible has an oxygen concentration of 10 p.
It may be pm or less.

A method of manufacturing a semiconductor device according to the present invention is
A step of forming a trench in the main surface of the semiconductor substrate; a step of filling the trench with a silicon oxide film by the method according to claim 1 to form an element isolation region; And a step of forming a semiconductor element in the divided element region. The method of manufacturing a semiconductor device according to the present invention comprises: a step of forming a capacitor on a main surface of a semiconductor substrate on which a semiconductor element is formed via an insulating film; and a step of forming a capacitor on the main surface of the semiconductor substrate. To a step of forming a silicon oxide film by the method according to claim 5. A semiconductor device according to the present invention includes an element isolation region formed of a buried insulating film in a trench formed on the semiconductor substrate main surface, a transistor formed in the element region divided into the element isolation region, and the semiconductor substrate main surface. and an interlayer insulating film formed to insulate the capacitor or wiring above the buried insulating film constituting the isolation _{region, Si n H 2n, Si n} H 2n + 2
And Si _{6 + 4n} H _{12 + 6n} (n is a positive number of 1 or more), which is a silicon oxide film obtained by heat treatment of high-order silane.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 and FIG.
An example will be described. 1 and 2 are process cross-sectional views of a silicon semiconductor substrate in which a trench of an STI type element isolation region is formed on the surface for explaining the manufacture of a semiconductor device. For example, a silicon nitride film (SiN film) 4 serving as a stopper film at the time of CMP is formed on the main surface of the semiconductor substrate 1 such as p-type silicon. The trench 5 is formed on this main surface by RIE or the like. The diameter of the trench 5 is
0.07 to 0.1 μm, with an aspect ratio of 5
That is all (FIG. 1A). Si on this semiconductor substrate 1
_{n H 2n, Si n H 2n} + 2 , and _{Si 6 + 4n} H
A solution containing a high-order silane represented by any one of chemical formulas _{12 + 6n} (n is a positive number of 1 or more) is applied.

Toluene, xylene and teralin are used as solvents for dissolving higher order silanes.
), Decalin, Cyclohexane
xane), cycloheptane, cyclooctane, n-Octane,
n-Decane, methylcyclohexane (Meth
ylcyclohexane), ethylcyclohexane (Ethylcyclohexane)
hexane), propylene glycol monomethyl ether (Propylene glycol monomethyl ether), propylene glycol monopropyl ether (Propylene glycol m)
onopropyl ether) is used. Higher order silane is O ₂
Since it is ignitable below, the atmosphere to be applied needs to be an atmosphere in which oxygen is eliminated as much as possible (≦ 10 ppm). In this embodiment, cyclopentasilane represented by Si ₅ H ₁₀ or Si ₁₀ H ₁₈ is used as the higher order silane, and toluene is used as the solvent. Oxygen concentration is 1pp in nitrogen atmosphere
The coating film 2 is formed on the main surface of the semiconductor substrate 1 and inside the trench 5 at a room temperature of not more than m (FIG. 1B).

A cyclopen is formed in the trench 5 on the semiconductor substrate 1.
Tasilane-containing solution or Si_TenH ₁₈Apply the containing solution
However, the embedding property is very good, and as shown in the figure,
Good for aspect ratios above 3 (5 in this example)
Embedded. Next is the cyclopentasilane-containing solution
I Si_TenH₁₈Has a trench filled with a solution containing
The silicon semiconductor substrate 1 in an atmosphere containing oxygen
The heat treatment removes the solvent and increases the
The decomposition reaction of orchid and the oxidation reaction with oxygen contained in the atmosphere
The silicon oxide film 3 is formed by raising it.
Oxygen content of atmosphere in heat treatment is 20%, treatment temperature
Is 400 ° C. to 500 ° C. (FIG. 1 (c)).

Next, using the silicon nitride film 4 as a stopper, the silicon oxide film 3 on the surface of the semiconductor substrate 1 is subjected to CMP treatment to flatten the surface of the semiconductor substrate 1. By this process, the silicon oxide film 3 on the silicon nitride film 4 is removed, and the silicon oxide film 3 is embedded in the trench 5. The silicon oxide film 3 embedded in the trench 5 constitutes an STI element isolation region, and a semiconductor element is formed in the element region partitioned by the element isolation region (silicon oxide film) 3 (FIG. 2A). ). The semiconductor element is, for example, a MOS transistor, and an n-type source / drain region 6 is formed in the element region, a gate oxide film 7 is formed on the surface of the semiconductor substrate, a gate electrode 8 such as polysilicon is formed on the gate oxide film, and the gate electrode is covered and protected. The insulating protective film 9 is formed. An interlayer insulating film 10 such as a silicon oxide film is formed on the semiconductor substrate 1 so as to cover the gate electrode 8. Further, capacitors, wirings (not shown), etc. are formed on the interlayer insulating film to form a semiconductor device (FIG. 2B). As in this embodiment, the silicon oxide film formed of high-order silane has a stress that is much smaller than that of a conventional oxide film and has almost no warp, and an insulating film that has a good filling property in a trench is formed. To be done.

Next, a second embodiment will be described with reference to FIG. 3A to 3D are process cross-sectional views of a silicon semiconductor substrate in which trenches of STI type element isolation regions are formed on the surface for explaining the manufacture of a semiconductor device. For example, a silicon nitride film (SiN film) 24 serving as a stopper film at the time of CMP is formed on the main surface of the semiconductor substrate 21 such as p-type silicon. A trench 25 is formed on this main surface by RIE or the like. The trench 25 has a diameter of about 0.07 to 0.1 μm and an aspect ratio of 5 or more (FIG. 3).
(A)). On this semiconductor substrate 21, Si _n H _{2 n} , Si
A solution containing a high-order silane represented by any of the chemical formulas _n H _{2n + 2} and Si _{6 + 4n} H _{12 + 6n} (n is a positive number of 1 or more) is applied. The material presented in the first embodiment such as toluene is used as the solvent for dissolving the higher order silane. Higher-order silanes are ignitable under O ₂ , so the atmosphere to be applied should be an atmosphere in which oxygen is eliminated as much as possible (≦ 10 ppm).
is necessary. In this example, S is used as the higher silane.
i ₁₀ H ₁₈ is used and toluene is used as a solvent. In a nitrogen atmosphere, the oxygen concentration is 1 ppm or less, and the coating film 22 is formed at room temperature on the main surface of the semiconductor substrate 21 and inside the trench 25 (FIG. 3B).

Next, the semiconductor substrate 22 is heat-treated in nitrogen, and the solvent (toluene) in which the higher order silane is dissolved is evaporated by this heat treatment to evaporate the solvent to form a coating film 22 '.
Is formed. The temperature at which evaporation is performed needs to be lower than the heat treatment temperature in the oxygen-containing atmosphere to be performed next,
It is 110 degreeC (FIG.3 (c)). Next, the semiconductor substrate 22
Is heat-treated in an oxygen-containing atmosphere to cause a decomposition reaction of high-order silane and an oxidation reaction with oxygen contained in the atmosphere to form a silicon oxide film 23. Oxidation temperature is 50
It is 0 degreeC (FIG.3 (d)).

Next, the silicon oxide film 23 on the surface of the semiconductor substrate 21 is commercialized by using the silicon nitride film 24 as a stopper.
The surface of the semiconductor substrate 21 is planarized by P treatment. By this process, the silicon oxide film 23 on the silicon nitride film 24 is removed, and the silicon oxide film 23 is embedded in the trench 25. The silicon oxide film 23 buried in the trench 25 constitutes an STI element isolation region, and a semiconductor element is formed in the element region partitioned by the element isolation region (silicon oxide film) 23 (not shown). The semiconductor element is, for example, a MOS transistor, and has n
Type source / drain regions, a gate oxide film on the semiconductor substrate surface, a gate electrode such as polysilicon on the gate oxide film,
An insulating protective film is formed to cover and protect the gate electrode. An interlayer insulating film such as a silicon oxide film is formed on the semiconductor substrate 21 so as to cover the gate electrode. Further, although not shown, capacitors, wirings, etc. are formed on the interlayer insulating film to form a semiconductor device. As in this embodiment, the silicon oxide film formed of high-order silane has a stress that is much smaller than that of a conventional oxide film and has almost no warp, and an insulating film that has a good filling property in a trench is formed. To be done. Further, since the solvent is once volatilized, a denser silicon oxide film is formed.

Next, a third embodiment will be described with reference to FIGS. FIG. 4 and FIG. 5 are process cross-sectional views of a silicon semiconductor substrate having trenches of STI type element isolation regions formed on the surface for explaining the manufacture of a semiconductor device. For example,
CM is formed on the main surface of the semiconductor substrate 31 such as p-type silicon.
Silicon nitride film (SiN film) that becomes a stopper film at P
34 is formed. A trench 35 is formed on this main surface by RIE or the like. The diameter of the trench 35 is 0.0
It is about 7 to 0.1 μm, and the aspect ratio is 5 or more (FIG. 4A). _Si n H on the semiconductor substrate 31
_2n , Si _n H _{2n + 2} and Si _{6 + 4n} H _{12 + 6n}
A solution containing a high-order silane represented by any of the chemical formulas (n is a positive number of 1 or more) is applied. The material presented in the first embodiment such as toluene is used as the solvent for dissolving the higher order silane. Higher order silanes are ignitable under O ₂ , so the atmosphere for application is an atmosphere in which oxygen is eliminated as much as possible (≦ 10
ppm) is required. In this example, Si ₁₀ H ₁₈ is used as the higher order silane and toluene is used as the solvent. In a nitrogen atmosphere, the oxygen concentration is 1 ppm or less, and the coating film 32 is formed at room temperature on the main surface of the semiconductor substrate 31 and inside the trench 35 (FIG. 4B).

Next, the semiconductor substrate 32 is heat-treated in nitrogen, and the solvent (toluene) in which the higher order silane is dissolved is evaporated by this heat treatment to evaporate the solvent to form a coating film 32 '.
Is formed. The temperature at which evaporation is performed needs to be lower than the heat treatment temperature in the oxygen-containing atmosphere to be performed next,
It is 110 degreeC (FIG.4 (c)). Next, the semiconductor substrate 32
Is subjected to a heat treatment in an oxygen-containing atmosphere to cause a decomposition reaction of high-order silane and an oxidation reaction with oxygen contained in the atmosphere to form a silicon oxide film 33. Oxidation temperature is 50
It is 0 degreeC (FIG.5 (a)). Next, the semiconductor substrate 32 is heat-treated at a temperature higher than the oxidation temperature (500 ° C.) to densify the silicon oxide film 33 to form a hardened silicon oxide film 33 ′. Densification in this example is performed at 1000 ° C. in a nitrogen atmosphere (FIG. 5).
(B)).

Next, using the silicon nitride film 34 as a stopper, the silicon oxide film 33 'on the surface of the semiconductor substrate 31 is removed as C.
The surface of the semiconductor substrate 31 is flattened by MP processing. By this process, the silicon oxide film 33 'on the silicon nitride film 34 is formed.
Is removed and the silicon oxide film 33 ′ is buried in the trench 35. The silicon oxide film 33 'embedded in the trench 35 constitutes an STI element isolation region, and a semiconductor element is formed in the element region partitioned by the element isolation region (silicon oxide film) 33' (not shown). . The semiconductor element is, for example, a MOS transistor, and has an n-type source / drain region in the element region, a gate oxide film on the semiconductor substrate surface, a gate electrode such as polysilicon on the gate oxide film, and an insulating protective film for covering and protecting the gate electrode. Is formed. An interlayer insulating film such as a silicon oxide film is formed on the semiconductor substrate so as to cover the gate electrode. Further, although not shown, a capacitor,
Wiring and the like are formed to configure a semiconductor device. As in this embodiment, a silicon oxide film formed of high-order silane has a stress that is much smaller than that of a conventional oxide film and has almost no warp, and an insulating film that has a good filling property in a trench is formed. To be done. Further, since the solvent is once volatilized and further baked, a denser silicon oxide film is formed.

Next, the function and effect of the above-described embodiment will be specifically described with reference to FIGS. 6 to 9. 6 to 9
[Fig. 3] is a photograph of a cross section of a semiconductor substrate. When the present invention was applied to the filling of trenches (STI trenches) forming the element isolation region, it was possible to fill all trenches with aspect ratios up to 5 (see the first to third embodiments). FIG. 6 shows a photograph obtained by SEM photographing after cleaving the surface including the trench after the silicon oxide film (SiO ₂ film) was buried in the trench according to the first embodiment of the present invention and after Au deposition. . FIG. 6 has the same structure as that of FIG. 1, and the inside of the STI trench 5 formed in the semiconductor substrate 1 and the silicon nitride film (S
A silicon oxide film 3 is formed on the iN film) 4.
6 (a) and 6 (b) use cyclopentasilane (Si ₅ H ₁₀ ) as a raw material, and FIG.
(D) uses Si ₁₀ H ₁₈ . As shown in FIG. 6, it can be seen that the silicon oxide film 3 is densely filled in every trench. However, the contrast of the material in the trench is characterized by being stronger (darker) than the contrast of the silicon oxide film 3 on the silicon nitride film 4. This means that the layers are formed of the same material but have different densities of the layers depending on the place where they are formed.

Therefore, the sample shown in FIG.
After etching for 5 seconds with the H ₄ F solution, the shape shown in the photograph of FIG. 7 was obtained. FIG. 7 is an SE photographed after cleaving a semiconductor substrate including a trench filled with a silicon oxide film formed by the present invention and performing NH ₄ F etching.
It is sectional drawing of M image. FIG. 7A shows an example of a narrow trench, and FIG. 7B shows an example of a wide trench. As shown in FIG. 7, the etching rate of the silicon oxide film embedded in the trench 5 is faster than that of the silicon oxide film 3 in the solid film portion on the silicon nitride film 4. That is, the quality of the solid film portion and the film quality inside the trench are different. The reason for this high etching rate is presumably due to the low density of the silicon oxide film inside the trench (density not measured). If the density is low, the relative dielectric constant is naturally low.

Next, TEM observation was performed in order to know by actual measurement that the density in the trench was low. The result is shown in FIG. FIG. 8 is a cross-sectional view of a TEM observation image of the semiconductor substrate 1 in which the trench 5 is formed and covered with the silicon nitride film 4. The silicon oxide film 3 in the trench shown in FIG. 8 is filled up from the top to the bottom of the trench. Further, FIG. 8 shows analysis points of the semiconductor substrate. Analysis point P1 is silicon of the semiconductor substrate, analysis points P2 to P8
Is a silicon oxide film inside the trench, and the analysis point P9 is a silicon nitride film. ED across these 9 points
X analysis was performed. As shown in Table 1, the results show that Si: O = substantially at any analysis point (P2 to P8).
It was 1: 2, and there was no great difference in the composition of the silicon oxide film (SiO ₂ ). From this, it can be concluded that the reason for the high etching rate in the trench is that oxygen is insufficient and the density is different (the density is lower in the trench). In addition, in Table 1, N represents a nitrogen atom.

[0020]

[Table 1]

In the first embodiment, as shown in FIG. 6, the silicon oxide film was uniformly buried from the trench having an aspect ratio of 1 or less to the trench having an aspect ratio of 5 or more. Further, as shown in the third embodiment, even if the high temperature heat treatment was performed at 1000 ° C. for 1 hour, the buried film inside the trench was still buried cleanly without film peeling (FIG. 9). FIG. 9 is a photograph similar to FIG. 7, and is a cross-sectional view of an SEM image taken by densifying and cleaving a semiconductor substrate including a trench having a silicon oxide film formed therein according to the present invention. 9A shows a semiconductor substrate having a narrow trench, and FIG. 9B shows a semiconductor substrate having a wide trench.

Thus, by filling the trench with the silicon oxide film according to the present invention, it is possible to obtain a silicon oxide film having a lower density than the silicon oxide film (so-called solid film portion) formed on a plane such as on the silicon nitride film. This is advantageous when the trench is used as an element isolation region. For example, a silicon oxide film formed on a plane such as a silicon nitride film has a high relative dielectric constant of about 4.7, but a silicon oxide film formed to be embedded in a trench has a low density. The relative dielectric constant varies depending on the formation conditions of the oxide film, but can be formed to about 3 or less. As described above, when the relative permittivity is low, the inter-cell capacitive coupling between the cells to be separated becomes small, and therefore, it is optimal for a semiconductor device in which miniaturization is advanced. Thus, it is considered that the difference in film quality between the solid film portion and the inside of the trench is advantageous from the viewpoint of embedding property.

Next, a fourth embodiment will be described with reference to FIG.
Reveal FIG. 10 shows a silicon oxide film according to the present invention,
It is sectional drawing of a semiconductor substrate when it is used as an insulating film.
In this embodiment, a cache memory used for a DRAM memory or the like is used.
A method for manufacturing a semiconductor device having a capacitor will be described. DR
In AM, even if the miniaturization progresses, the capacity that configures DRAM
The data capacity cannot be reduced. Therefore, high dielectric
Index dielectric thin film can be introduced as a capacitor dielectric.
And are essential. Also, high-speed writing similar to DRAM
And ferroelectric as a non-volatile memory that can operate at low voltage
Ferroelectric using the spontaneous polarization of the body
cRAM is receiving attention. These capacitors are
Ta between the partial electrode 46 and the upper electrode 45₂O_FiveOr B
ST (Ba_xSr_1-xTiO ₃) And other high dielectric films
Or PZT (Pb (Zr, Ti) O₃) And SBT (Sr
Bi₂Ta₂O₉) Etc. sandwiched the ferroelectric film 47
It has a shape. MOS transistor (not shown)
Which semiconductor element is built into a semiconductor substrate such as silicon
The plate 41 has a silicon oxide film or the like formed by a normal technique.
Insulating film 42 is formed. On this insulating film 42
The above-mentioned capacitor is formed. The capacitor is
The lower electrode 46, the ferroelectric film 47, and the upper electrode 45 are sequentially formed.
It is composed of a laminated body formed. Capacitor coating
The interlayer insulating film 43 is formed so as to do so.

After forming the capacitor, Si _n H _2n or Si _n H _{2n + 2} or Si _{6 + 4n} H
A solution containing a high-order silane represented by a chemical formula such as _{12 + 6n} (n is a positive number of 1 or more) is applied. The atmosphere to be applied needs to be an atmosphere in which oxygen is eliminated as much as possible (≦ 10 ppm). In this example, cyclopentasilane represented by Si ₅ H ₁₀ was used as the higher order silane, and nitrogen was used as the atmosphere. Next, heat treatment is performed in nitrogen at a temperature lower than the heat treatment temperature in the oxygen-containing atmosphere in the next step to evaporate the solvent such as toluene in which the higher silane is dissolved. 110 ° C. was used as the evaporation temperature. Next, heat treatment is performed in an oxygen-containing atmosphere to cause a decomposition reaction of higher-order silane and an oxidation reaction with oxygen contained in the atmosphere to form an interlayer insulating film 43 made of a silicon oxide film. The oxidation temperature was 500 ° C. A connection wiring 48 made of tungsten or the like for electrically connecting a metal wiring (not shown) formed on the semiconductor substrate 41 after forming the interlayer insulating film 43 and the upper electrode 45.
To form. The metal wiring is electrically connected to a MOS transistor or the like formed on the semiconductor substrate 41 to form a memory such as a DRAM. This interlayer insulating film is
The stress is much smaller than that of the conventional oxide film, and it has almost no warpage.

In this embodiment, the silicon oxide film (SiO 2
₂ ) Measure the stress of the film. How to measure stress is
In this method, the radius of curvature is calculated from the warp of the silicon wafer on which the silicon oxide film is formed, and is calculated from the following equation (1). σ = Eh ² / (1−ν) × 6Rt (1) where E / (1−ν): biaxial elastic modulus of semiconductor substrate, h: thickness (m) of semiconductor substrate, t: silicon Thickness of oxide film (m), R: radius of curvature of semiconductor substrate (m), σ: average stress of silicon oxide film (Pa) The silicon oxide film produced by the method shown in this example has almost no warp. It was a stress-free film. Further, the stress of the silicon oxide film formed by the method shown in the first and second embodiments is 299.6MP.
a, and it was a Tensile film.

[0026]

According to the present invention, the stress is much smaller than that of the silicon oxide film formed by the conventional method, and there is almost no warp. Moreover, the filling property in the trench is good and the density in the trench is high. Is smaller than that of the interlayer insulating film of the same material formed on the flat main surface of the semiconductor substrate, and thus the relative dielectric constant thereof is small, so that a silicon oxide film (SiO ₂ ) can be obtained.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view of a semiconductor substrate having a trench of an STI type element isolation region formed on its surface for explaining the manufacture of a semiconductor device of a first embodiment according to the present invention.

FIG. 2 is a process cross-sectional view of a semiconductor substrate having a trench of an STI type element isolation region formed on its surface for explaining the manufacture of a semiconductor device of a first embodiment according to the present invention.

FIG. 3 is a process cross-sectional view of a semiconductor substrate having a trench of an STI type element isolation region formed on its surface for explaining the manufacture of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a process cross-sectional view of a semiconductor substrate in which a trench of an STI type element isolation region is formed on the surface for explaining the manufacture of the semiconductor device of the third embodiment according to the present invention.

FIG. 5 is a process cross-sectional view of a semiconductor substrate having a trench of an STI type element isolation region formed on its surface for explaining the manufacture of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a view showing a silicon oxide film (Si
(O ₂ film) and then open at the surface including the trench A
Sectional drawing of the semiconductor substrate which carried out SEM photography after u vapor deposition.

FIG. 7 is a cross-sectional view of a semiconductor substrate obtained by SEM photographing after burying a silicon oxide film formed according to the present invention, then cleaving the surface including a trench and performing NH ₄ F etching.

FIG. 8 is a cross-sectional view of a TEM observation image showing analysis points of a semiconductor substrate covered with a silicon nitride film which is cleaved at a surface including a trench after being embedded with a silicon oxide film formed according to the present invention.

FIG. 9 is a cross-sectional view of an SEM image taken by cleaving a semiconductor substrate including a trench in which a silicon oxide film is formed according to the present invention and performing densification.

FIG. 10 is a cross-sectional view of a semiconductor substrate when a silicon oxide film according to the present invention as a fourth embodiment of the present invention is used as an interlayer insulating film.

FIG. 11 is a process cross-sectional view illustrating the manufacture of a conventional semiconductor device.

[Explanation of symbols]

1, 21, 31, 41, 101 ... Semiconductor substrate, 2,
21, 31 ... Coating film containing high-order silane, 3, 2
3, 33, 43 ... Silicon oxide film (SiO ₂ ),
4, 24, 34, 102 ... Silicon nitride film (Si
N), 5, 25, 35, 103 ... Trench (STI
Grooves), 22 ', 32' ... Coating film containing higher order silane obtained by evaporating solvent, 33 '... Silicon oxide film (SiO ₂ ) cured, 42 ... Insulating film, 45.・
-Upper electrode, 46 ... Lower electrode, 47 ... Ferroelectric film, 104 ... TEOS film.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 29/78 F Term (Reference) 5F032 AA35 AA44 AA66 AA69 AA74 CA14 CA17 DA09 DA23 DA33 DA74 DA78 5F058 BA04 BA20 BC02 BD04 BF46 BH03 BH04 BJ01 5F083 AD21 FR01 GA27 GA30 JA06 JA14 JA15 JA17 JA56 5F140 AA08 AA39 AC32 BA01 BF01 BF04 BG50 CB04 CE07

Claims (8)

[Claims] 1. Si _n H _2n , Si _n H _{2n + 2} and Si
_{6 + 4n} H _{12 + 6 n} (n is a positive number of 1 or more), a step of applying a solution containing a high-order silane represented by any one of the chemical formulas onto a semiconductor substrate, and heat-treating the semiconductor substrate in an atmosphere containing oxygen. And a step of causing a decomposition reaction and an oxidation reaction of the higher order silane to form a silicon oxide film on the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the solution contains a solvent in which the higher order silane is dissolved. 3. Si _n H _2n , Si _n H _{2n + 2} and S
i _{6 + 4n} H _{12+ 6n} (n is a positive number of 1 or more) represented by any one of the chemical formulas, and a step of applying a solution containing a high-order silane dissolved in a solvent onto the semiconductor substrate; A step of evaporating the solvent contained in the solution by performing a first heat treatment in an atmosphere in which oxygen is eliminated as much as possible; a first heat treatment at a temperature higher than that of the first heat treatment in an atmosphere containing the semiconductor substrate; And the step of forming a silicon oxide film on the semiconductor substrate by causing a decomposition reaction and an oxidation reaction of the higher order silane by performing the heat treatment of 2. 4. Si _n H _2n , Si _n H _{2n + 2} and S
i _{6 + 4n} H _{12+ 6n} (n is a positive number of 1 or more), and a step of applying a solution containing a high-order silane dissolved in a solvent onto the semiconductor substrate, and the semiconductor substrate Evaporating the solvent contained in the solution by performing a first heat treatment in an atmosphere in which oxygen is eliminated as much as possible, and the semiconductor substrate in an atmosphere containing oxygen and at a temperature higher than that of the first heat treatment. Second heat treatment to cause a decomposition reaction and an oxidation reaction of the higher order silane to form a silicon oxide film on the semiconductor substrate, and the semiconductor substrate is heated at a temperature higher than that of the second heat treatment. And a step of hardening the silicon oxide film by heating the silicon oxide film. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the atmosphere in which oxygen is exhausted as much as possible has an oxygen concentration of 10 ppm or less. 6. A step of forming a trench in a main surface of a semiconductor substrate; a step of burying a silicon oxide film in the trench by the method according to claim 1 to form an element isolation region, And a step of forming a semiconductor element in an element region divided into the element isolation regions. 7. The step of forming a capacitor on the main surface of a semiconductor substrate on which a semiconductor element is formed via an insulating film, and the main surface of the semiconductor substrate on which the capacitor is formed, according to claim 1. And a step of forming a silicon oxide film by the method described in 1 .. 8. An element isolation region formed of a buried insulating film in a trench formed on the main surface of the semiconductor substrate, a transistor formed in the element region divided into the element isolation region, and on the main surface of the semiconductor substrate. and an interlayer insulating film formed to insulate the capacitor or wiring buried insulating film constituting the isolation region, Si _{n
H 2n, Si n H 2 n} + 2 and _{Si 6 + 4n} H
A semiconductor device comprising a silicon oxide film obtained by heat treatment of a high-order silane represented by any one of chemical formulas _{12 + 6n} (n is a positive number of 1 or more).