JP2003029988A - Task scheduling system and method, program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve processor using efficiency by shortening standby time and data transfer standby time by the dependency relation of each task. SOLUTION: A task arranging means 22 performs scheduling on the basis of a task graph 31 prepared by a task graph generation part 21. The task arranging means 22 shortens the interval between the leading task and final task of each processor by performing forward direction task scheduling when the highest priority task of each processor whose execution is specified in the processor whose design is started by a trigger generator 221 for the design start of each processor is already arranged and performing opposite direction task scheduling when it is not arranged. Further, at the time of task arrangement, the settable range of a transfer task is described in bus using information 34, and in the case that the data transfer standby time is generated, the data transfer standby time is shortened by rearranging the already arranged task by a task rearranging means 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static task scheduling system and method for scheduling a task of multitask processing in a multiprocessor system including a plurality of arithmetic processing units (processors) before executing the task.

[0002]

2. Description of the Related Art Conventionally, in a multi-tasking multi-processor system having a plurality of arithmetic processing units, task scheduling of tasks executed by each processor is performed to determine the execution time of each task, and then each task is executed. Sometimes a static task scheduling system is used. Japanese Patent Laid-Open No. 4-253228 describes a task scheduling system that performs static task scheduling. FIG. 11 is a block diagram showing the configuration of the task scheduling system. As shown in FIG. 11, the conventional task scheduling system uses the processor-specified task queue 5
13, the executable task queue 512, the task registration means 511, and the task selection means 514.

A task whose processor is designated is registered in the processor designated task queue 513. Executable tasks are registered in the executable task queue 512. The task registration unit 511 determines whether the execution processor is designated or not and the processor designation task queue 513.
The task is distributed to the executable task queue 512 and the task is registered. The task selection means 514 is provided with the executable task queue 512 or the processor-specified task queue 513.
Select the task with the highest priority from either of these queues.

This task scheduling system is
Task scheduling is performed based on the block structure of each task and a task graph 61 showing dependency relationships such as true data dependency, anti-dependency, and output dependency. Task registration means 5
The reference numeral 11 refers to this task graph 61 to check whether or not a processor of an executable task is designated, and if there is a designation, the task is designated as a processor designated task queue 51.
3 is registered, and if not specified, the task is registered in the executable task queue 512. Task selection means 5
When a task exists in the processor-specified task queue 513, 14 selects the task with the highest priority from among them, and when there is no task, the highest task from the executable task queue 512. Task scheduling is performed by selecting tasks with priorities.

Further, in a multiprocessor system, generally, each processor is connected by a bus, and if each task includes a task for transferring data using the bus, the task Bus access must be arbitrated. Material IP-96-24, published by the Information Processing Society of Japan in 1996, Sep. In 1996, a paper on such bus access arbitration, "Data transfer order optimization in non-synchronous near fine grain parallel processing", is published. In the task scheduling related to data transfer published in this paper, the level based on the longest path length to the end of the basic block is calculated for each transfer task, and the highest level is obtained when multiple data transfer tasks occur simultaneously. The data transfer task is prioritized for scheduling, and other data transfer tasks are made to wait until the bus is released.

[0006]

As described above, the conventional task scheduling system and method have the following problems. (1) Even if a task with a high priority has a dependency relationship with a task that specifies a processor, the task is executed until the task that specifies the processor ends I can't. Therefore, if there are many such tasks, the utilization efficiency of the processor becomes low. (2) When multiple data transfer tasks occur at the same time, the data transfer task with the highest level is given priority, but the data transfer wait time of the tasks may reduce the efficiency of use of the processor. is there.

It is an object of the present invention to provide a task scheduling system and method capable of improving the usage efficiency of a processor.

[0008]

In order to solve the above-mentioned problems, in the task scheduling system of the present invention, when performing multitask processing of a plurality of tasks in a multiprocessor system including a plurality of processors, the execution processor is designated. A processor to be designed in a static task scheduling system that performs task scheduling of each task before execution of each task based on a task graph showing the dependency relationship of each task including A trigger generator, a forward list in which tasks having the design target processor as an execution processor are registered in descending order of priority, and a task having the design target processor as execution processor in descending order of priority The backward list to be registered and the forward list And a task registration means for registering a task in the reverse direction list, and either the forward direction list or the reverse direction list is selected, and the execution time of each task is determined based on the selected list. And a task selecting means for performing the task selection.

In the task scheduling system of the present invention, a trigger generator is provided to determine the execution time of each task that specifies the processor only after the processor is included in the design target. By providing a reverse direction list and task selection means, it is possible to select forward and backward schedules so that the execution time intervals of each task are not vacant. Can be improved.

In another task scheduling system of the present invention, the execution time of a transfer task that transfers data via the bus, and the execution time of another transfer task does not change even if the execution time is changed. By referring to the bus use information in which the settable range of the execution time of the transfer task is registered and the bus use information, when the execution times of a plurality of transfer tasks are overlapped, within the settable range It further comprises task relocation means for relocating the execution time of each transfer task.

In the task scheduling system of the present invention, the settable range of the execution time of the transfer task is stored in the bus usage information, and the transfer task is transferred at the time within the settable range so that the transfer wait time does not occur. Since the tasks are rearranged, the data transfer waiting time can be shortened, so that the usage efficiency of each processor can be improved.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a task scheduling system and method according to an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings, the components having the same reference numerals indicate the same components.

(First Embodiment) First, a task scheduling system and method according to a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an environment in which the task scheduling system of this embodiment operates. As shown in Figure 1,
The task scheduling system 8 of this embodiment has three
This is a system for performing task scheduling of a multiprocessor system 100 including one processor PE1 to PE3. Multiprocessor system 100
The number of processors is three and the number of buses is one, but the present invention does not limit these numbers. The PEs 1 to 3 are connected to each other via the bus 15. Data transfer between the processors and between the processor and another device is performed via the bus 15. The task scheduling system 8 inputs a set of tasks to be scheduled from the task input means 1 and outputs the execution time of each scheduled task to the execution time output means 4.

Further, the task scheduling system 8
Then, the result of task scheduling is PE1 to PE3.
Therefore, data communication is possible between the task scheduling system 8 and PE1 to PE3. Task scheduling system 8 and P
The E1 to PE3 may be connected by a bus connection or may be connected by a communication line such as a LAN. Therefore, the task scheduling system 8 can also be realized by a personal computer (hereinafter, PC). When the task scheduling system 8 is a PC, a disk reading device or the like for reading the disk storing the program files of the respective tasks serves as the task input means 1, and the display or printing device of the PC serves as the execution time output means 4. .

FIG. 2 is a block diagram showing the configuration of the task scheduling system 8 of this embodiment. As shown in FIG. 2, the task scheduling system 8 includes a data processing unit 2 and a data storage unit 3. The data processing unit 2 operates under program control, and, for example,
As described above, the task scheduling system 8 is a PC
, The CPU of the PC operates by executing the program. In this case, the data storage unit 3
Is a magnetic disk device of a PC or the like.

The data processor 2 is a task graph generator 2
1 and task placement means 22. The data storage unit 3 also includes a task graph storage unit 31, a task arrangement list storage unit 32, and a bus usage information storage unit 33.

The task graph generator 21 examines the block structure of each task input from the task input means 1 and the dependency relationships between tasks such as true data dependency, anti-dependency, and output dependency, and based on the dependency relationships. Create a task graph. The task graph generated by the task graph generation unit 21 is stored in the task graph storage unit 31. An example of this task graph is shown in FIG. As shown in FIG.
The graph section shows each of the tasks A to P. The task located at the end point of each side of the graph cannot be executed unless the design of all tasks located at the start point of the side is completed. In addition, () in each section shows the designation of the execution processor of the task.

The bus usage information is information indicating the usage status of the bus 15 of the multiprocessor system 1 shown in FIG. The processors PE1 to PE3 perform data transfer via the bus 15 when the task to be executed is a transfer task. Normally, in a multiprocessor system, a plurality of devices cannot use a single bus at the same time, so it is necessary to grasp the usage status of the bus 15 when scheduling transfer tasks. The bus usage information is useful information when scheduling transfer tasks.

The task allocation list storage unit 32 is for storing the execution time of the allocated tasks, the task scheduling result such as the execution processor information, that is, the task allocation list. Task placement means 22
Determines the execution time of each task based on the task graph recorded in the task graph storage unit 31 and the bus usage information stored in the bus usage information storage unit 33, and the task placement list based on the execution time. Is created and stored in the task allocation list storage unit 32, and the bus usage status updated by the determination of the execution time of each task is reflected in the bus usage information in the bus usage information storage unit 33. The task placement unit 22 includes a trigger generator 221, a task registration unit 222, a forward list 223, and a backward list 224.
And task selection means 225. The trigger generator 221 determines a processor to be designed.

The task registration means 222 uses the forward list 2
The task is registered in 23 and the backward list 224. The forward list 223 is a list in which each task is described in descending order of priority, and the backward list 224 is a list in which each task is described in descending order of priority. The task selection means 225 selects either the forward list 223 or the backward list 224, and determines the execution time of the scheduled task in the order described in the selected list.

Next, the operation of the task scheduling system of this embodiment will be described. FIG. 4 is a flowchart showing the operation of the task scheduling system of this embodiment. First, when a task set is supplied from the task input means 1, the task graph generation unit 21 generates the task graph and stores it in the task graph storage unit 31 as described above, and calculates the priority of each task. Then
It is stored in the task graph storage unit 31 (step A
1). For the priority of each task, both the forward priority and the backward priority are calculated. The priority of each task is calculated as follows.

First, regarding the forward priority of each task, a task having a long path length from each task to the end task is given a higher priority. If there are tasks with the same path length, the task with the largest number of direct successor tasks is prioritized. Further, regarding the priority of each task in the backward direction, a task having a long path length from the terminal task to each task is given higher priority. When tasks with the same path length exist, the task with the smaller number of direct preceding tasks is prioritized.

After step A1 is completed, the task placement means 22
Then, first, the trigger generator 221 operates. The trigger generator 221 determines a processor to be included in the design target based on the task graph stored in the task graph storage unit 31 (step A2). In step A2,
The trigger generator 221 first includes, out of the processors to be used, a processor that is not designated for any task as a design target. The trigger generator 221 has only a task that specifies a processor as an undesigned task, and when the specified processor is not included in the design targets, the priority of the undesigned task in the forward direction is determined. Include the processor to which the highest task is assigned in the design target. Further, the trigger generator 221 is not a design target when data transfer occurs between a task designated as a design target processor and a task designated as a non-design target processor. Include the processor in the design target.

After step A2 is completed, the task placement means 22
Determines whether or not the task having the highest forward priority among the tasks for which the processor is designated is targeted (step A3). In step A3, if the task having the highest priority in the forward direction has already been arranged in all the processors to be designed, the task registration means 222
To create a forward list 223 (step A
4) The task selecting unit 225 schedules the task in the forward direction, and the execution time of the task is registered in the task placement list 32 (step A5).

In steps A4 and A5, the task registration means 222 calculates the tasks to be scheduled, that is, the tasks that are ready to be executed, and the forward list 223 is created. However, the predecessor task from the task whose execution is designated by the processor that is not the design target may not be designed. The task placement unit 22 takes out the task with the highest forward priority in this list, places the task at the earliest executable time, and registers the result in the task placement list 32 by the task selection unit 225. To do. When the task whose execution time is determined uses the bus 15, the task selecting means 225 refers to the bus usage information stored in the bus usage information storage unit 33 to check the time when the bus 15 is used. I'll do it.

In step A3, if the task having the highest priority in the forward direction has not been allocated in all the processors to be designed, the task registration means 222 creates the backward list 223 (step A6). ,
The task selecting means 225 schedules in the reverse direction, and the execution time of the task is registered in the task placement list 32 (step A7).

In steps A6 and A7, that is, in the backward task scheduling process, the task registration means 222 is used.
Creates a backward list 224 for tasks that have not been designed yet after the placement of subsequent tasks has been completed. However, the subsequent task of the task whose execution is designated for the processor that is not the design target may be undesigned. Further, in the processor, subsequent tasks from a task having a lower priority in the opposite direction than the task that triggers the design may be undesigned.

The task placement means 22 of FIG. 1 takes out the task having the lowest backward priority in this list and schedules it as the execution time of the task at the latest executable time, and the task selection means 22.
5, the scheduling result is registered in the task allocation list 32. When the task whose execution time is determined uses the bus 15 at this time, the time when the bus 15 is used is checked with reference to the bus usage information stored in the bus usage information storage unit 33.

Steps A4, A5, Steps A6, A7
When the task scheduling operation is performed by carrying out the process (1), that is, the placement of a certain task is completed, the task placement unit 22 checks whether or not the scheduling of all tasks is finished (step A8). If there are still unscheduled tasks, the trigger generation process (step A2) is performed in order to check whether or not there is a processor newly included in the design target in the task allocation.
Return to. When it is determined in step A8 that the scheduling of all the tasks has been completed, the scheduling result is output to the execution time output means 4 and the process is completed.

In the task scheduling system of this embodiment, a trigger generation process is provided, each task is arranged after the processor is included in the design target, and the forward and backward schedules are appropriately performed according to the schedule situation. Therefore, the usage efficiency of each processor can be improved.

Next, the operation of the task scheduling system of this embodiment when the task scheduling of each task set whose dependency is shown by the task graph of FIG. 3 is performed will be described. In this task graph, the processors PE1 to PE3 are designated, and there is no processor not designated in any of the tasks. Therefore, as shown in the process of step A2 of FIG. The PE1 assigned to the task A having the highest priority is included in the design target. And
Through the processing of steps A4 and A5, forward task scheduling from task A to task F is performed.

In the forward task scheduling, the execution time of each of the tasks A to F is later than the allocation time of the task A having the highest priority and is the earliest free time of the designated processor. . If the task is a transfer task that uses the bus 15, the time at which the transfer task uses the bus is reflected in the bus usage information. If the task is a task that transfers data to a task that specifies a processor that is not included in the design target, the processor that is not the design target is included in the design target. For example, since the task F is a task that transfers data to the task I that specifies PE2,
The task scheduling system of this embodiment is a PE
2 is included in the processor to be designed. After this, PE2
The task that specifies is also included in the scheduling target.

Next, the task scheduling system of the present embodiment designs the task I that triggered PE2 to be included in the design target, but the task G with a high priority in the forward direction in which PE2 is designated is designed. Since it has not been arranged, task scheduling having a higher priority than the task I is performed thereafter in the reverse direction in order from the task having a lower priority by the processing of steps A6 and A7.

In the backward task schedule, the backward priority is given to the succeeding task in which the processor to be designed is designated or the design of the succeeding task in which the processor is not designated is completed. Select the least frequent task. However, a successor task having a CP (critical path) value lower than the task (for example, task I) that caused the processor to be included in the design target is not included in the successor task described above. The task placement time refers to the task placement list and the bus usage information, and the time before the task placement time that caused the processor to be included in the design target, that is, the placeable time,
It is the latest time. In the task graph of FIG. 3, assuming that the task having the lowest backward priority after designing the task I is the task J, the task selecting unit 225 indicates that the task J is the task J.
Is placed immediately before task I.

When the task G is designed, the highest priority tasks in the forward direction of the processors (PE1 and PE2) that are the objects of design are in the designed state. Therefore, in the task scheduling system of this embodiment, Schedule tasks in the forward direction. After designing the task L, the PE 3 is included in the design target by the trigger generator 221, and the task schedule in the reverse direction is started. When the task M is designed, the task schedule in the forward direction is again performed.

The schedule result of the task scheduling system of this embodiment is shown in FIG. Figure 5 (a) shows
FIG. 5B shows the scheduling result of the task scheduling system of this embodiment, and FIG. 5B shows the scheduling result of the conventional task scheduling system. As shown in FIG. 5, in each processor, there is no time during which no task is executed between the time when the first task is executed and the time when the last task is executed.

Further, in the task scheduling system of this embodiment, the task selecting means 225 refers to the bus usage information stored in the bus usage information storage unit 33 for the transfer task for transferring the data using the bus 15. The task execution time. First, the processor P
The task allocation list of each task that specifies E1 is shown in FIG.
It is assumed that the bus usage information at that time is as shown in FIG. 6B, and the case where the task 4 which is the transfer task is scheduled will be considered. After deciding to place the task 4 at the time 4, when the task 4 is arranged at the time 4, the task selecting means 225 determines whether or not the use of the bus conflicts with another task placed earlier. To check. As shown in FIG. 6B, at time 4, since task B uses the bus, task 4 cannot be placed at time 4. Therefore, in the task scheduling system of this embodiment, the time 4
Among the subsequent times, the task 4 is arranged at the time 6 when the bus 15 is not used by another task.

By using the task scheduling system of this embodiment, when the usage efficiency of each processor is increased, the task processing cost is reduced and the periodic task can be processed at high speed. When performing the periodical processing of each task shown in the task graph of FIG. 3, in the conventional task scheduling system, as shown in FIG. , There is a time when each processor is not executing a task. Therefore, for example, the processor PE3 requires 11 cycles to execute all tasks. On the other hand, in the task scheduling system of this embodiment, as shown in FIG. 5A, the execution time for each processor is 6 cycles. The processor usage efficiency,
If the ratio of the time when the processor is actually executing the task to the time from the start time of the first task to the end time of the last task in each processor,
In the conventional task scheduling system of FIG. 5B, the processor usage efficiency is 62%, whereas in the task scheduling system of the present embodiment of FIG. 5A, the processor usage efficiency is 100%. .

(Second Embodiment) Next, a task scheduling system according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the task scheduling system of this embodiment. As shown in FIG. 7, the task scheduling system 9 of the present embodiment differs from the task scheduling system 8 of FIG. 2 in that a data processing unit 5 is provided instead of the data processing unit 2. The data processing unit 5
The task graph generation unit 21, the task placement unit 24, and the task relocation unit 23 are provided. Task placement means 2
Similar to the task placement means 22 of FIG. 2, 4 designates the execution time of each task based on the task graph stored in the task graph storage unit 31 to perform task scheduling, and the scheduling result is used as the task placement list. Is stored in the task allocation list storage unit 32 as described above, and the bus usage information in the bus usage information storage unit 34 is updated according to the scheduling result. The task rearrangement unit 23 rearranges the tasks on the task arrangement list stored in the task arrangement list storage unit 32.

The data storage unit 6 includes a task graph storage unit 31, a task arrangement list storage unit 32, and a bus use information storage unit 34. Bus usage information storage unit 3
Similarly to the bus use information storage unit 33 of FIG. 2, 4 stores the time when the transfer task can use the bus. When updating the bus usage information by performing the above-mentioned task scheduling, the task placement means 24 stores all the assignable times when the task can use the bus 15. The allocable time is the time at which the predecessor task that has the closest allocation time to that task among the predecessors of that task is allocated, and the successor task that has the closest allocation time to that task among the successor tasks to that task. It is a time between the allocated time and a time within a settable range in which the critical path values are equal among the tasks that specify the processor specified by the task. Therefore, in order to set the allocable time of the task, it is necessary to determine the allocating times of all the preceding tasks and the subsequent tasks of the task.

FIG. 8 is a diagram showing possible allocation times in the task scheduling system of this embodiment. If the task graph is as shown in Figure 8 (a),
Task B can be arranged between the execution times of task A and task D. Therefore, as shown in FIG.
The allocable time of task B is time 2 and 3, and
As shown in (c) and (d), since the task B and the task C have the same critical path value, their execution times can be exchanged.

When the task allocating means 24 allocates the transfer task, the task rearranging means 23 checks the data transfer waiting time of the task. In the task scheduling system according to the present embodiment, the transfer task cannot be arranged at an early time while the processor is idle because the bus 15 cannot be used during forward scheduling, or the bus cannot be used during backward scheduling. If the transfer task cannot be placed at a later time even though the processor is free, it is determined that a data transfer wait state occurs. When the data transfer waiting time occurs, the task rearrangement unit 24 tries the task rearrangement processing.

The task rearrangement means 24 temporarily arranges the transfer task at a time when the transfer waiting time does not occur. The time at which the temporary allocation is performed is the earliest time when no processor space is available in the forward schedule, and is the latest time when no processor space is available in the reverse schedule.

Next, the task relocation means 24 refers to the bus use information to find a task that causes a bus collision with the task that has been temporarily placed, and checks the movable range of the transfer task. If the moveable range of all transfer tasks of the bus collision partner does not cause a bus collision at the moved destination, the execution time of the transfer task of the bus collision partner is replaced with the instruction at the moved destination, and the temporary allocation is performed. Confirm the task execution time at that time. When the transfer task of the bus collision partner cannot be moved to another time, the temporary allocation time of the transfer task is shifted by one cycle. In the forward schedule, the time to shift is one cycle later than the time when the temporary placement was initially performed, and in the reverse schedule,
The time is one cycle earlier than the time when the temporary placement was initially performed.

When the relocation of the transfer task is completed, the task relocation means 23 executes the execution time of the task that was temporarily placed, the relocation time of the transfer task that causes a bus collision with it, and the relocated transfer task. The bus use time in which the execution time and the execution time of the task are exchanged is reflected in the task allocation list stored in the task allocation list storage unit 32, and the bus use time of the transfer task after rearrangement is stored in the bus use information storage unit 32. It is reflected in the information. FIG. 9 is a flowchart showing the operation of the task rearrangement unit 23 in the task scheduling system of this embodiment. As shown in FIG. 9, first, the task rearrangement unit 23 is created by the task placement unit 24, and the task placement list storage unit 32 is created.
By referring to the task allocation list stored in (3), it is determined whether or not a transfer waiting time has occurred for a transfer task that uses the bus 15 among the tasks (step C1).
If the transfer waiting time has occurred, the task rearrangement unit 23 temporarily arranges the transfer task at a time when the transfer waiting does not occur (step C2). After step C2, the task rearrangement unit 23 refers to the bus use information stored in the bus use information storage unit 34 and detects whether there is a task that causes a bus collision with the task that was provisionally placed in step C2. If there is such a task, the time at which the task can be arranged is referred to detect whether the task can be rearranged (step C3). If the task causing the bus collision is not relocatable at step C3, the temporarily placed task is temporarily placed at another time (step C4), and the process returns to step C3.

If the task causing the bus collision can be relocated in step C3, the task is relocated, and the temporary placement performed in step C2 is determined (step C5), and the process is terminated. . In the task scheduling system of this embodiment, after the task relocation means 23 completes the relocation, if all the task placements have not been completed, the task placement means 24 again schedules the tasks.

FIG. 10 is a diagram showing an example of bus usage information stored in the bus usage information storage unit 34 in the task scheduling system of this embodiment. It is assumed that the transfer task is currently arranged as shown in FIG. 10A and the bus use information is as shown in FIG. 10B.
In the task scheduling system of this embodiment, when a data transfer waiting state occurs due to the placement of a transfer task, the task relocation is attempted, but in FIG. 10, the task relocation means 23 assigns the task 4 to the time 4 ( 4 clk) is temporarily arranged. The task relocation unit 23 refers to the bus usage information stored in the bus usage information storage unit 34, detects a task that causes a bus collision with a task that has performed temporary allocation, and moves the allocation time of the transfer task. Check the possible range, that is, the possible arrangement time. In FIG. 10, the task B is the opponent of the bus collision, and the allocable time of the task B is the time 3 and the time 4. Therefore, in the task scheduling system of the present embodiment, the task B can be arranged also at the time 3, so the arrangement time of the task B is changed from the time 4 to the time 3. By this replacement, the task B uses the bus 15 at time 3, and the task 4 can use the bus 15 at time 4. However, when the allocable time of the task B does not exist other than the time 4, the task relocation means 23
The temporary placement time of task 4 is set to time 5, and the above-described processing is performed at time 5. The task relocation means 23 repeats this operation until the bus collision does not occur.

The task relocation means 23, at the time when the task can be placed, designs the transfer task and indicates the execution time of the transfer task which was temporarily placed and the execution time of the relocated task. , And the execution time of the rearranged task and the task whose execution order is exchanged are reflected in the task allocation list stored in the task allocation list storage unit 32. Further, the task relocation unit 23 reflects the bus usage time of the transfer task after the relocation on the bus usage information stored in the bus usage information storage unit 34. By performing the task replacement as described above, the task 4 arranged at the time 6 can be arranged at the time 4, and the data transfer waiting time can be shortened.

Further, even when there is no other possible allocation time of the task of the bus collision partner, the task can be allocated at the time when it was initially allocated. Therefore, in the task scheduling system of this embodiment, the task data transfer waiting time can be made equal to or shorter than that of the task scheduling system of the first embodiment.

As described above, in the task scheduling system of this embodiment, when a transfer waiting time occurs when a data transfer task is arranged, the task is rearranged to transfer the transfer waiting time. Can be reduced.

As described above, the task scheduling systems 8 and 9 are composed of the memory of the computer and the CPU (central processing unit), and load and execute the programs for realizing the functions of the above-mentioned respective parts in the memory. The function may be realized by doing so. This program may be recorded in a magnetic disk, a semiconductor memory, a CD-ROM, or any other computer-readable recording medium.

In the task scheduling system of this embodiment, the priority of each task is based on the critical path value, the number of preceding tasks (when creating the forward list), and the number of subsequent tasks (when creating the backward list). I asked. However, the present invention is not limited to this, and the task priority may be obtained under exactly the same conditions when the forward list is created and when the backward list is created.
The task priority may be obtained using another method such as the CP / MISF method or the CP / DT / MISF method.

[0053]

As described above, the task scheduling system of the present invention has the following effects. (1) Provide a trigger generation process that determines the start of design of each processor, do not allocate the task specified by that processor until the process is executed, and forward or reverse depending on the design status of the highest priority task of each processor. Since the task schedule of (1) is appropriately performed, the waiting state of the task for which the execution processor is designated can be reduced and the utilization efficiency of the processor can be improved. (2) Since the time when the transfer task can be allocated is stored in the bus usage information, and when a wait state occurs in the data transfer task, the task can be relocated to shorten the data transfer wait state. , The use efficiency of the processor can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an environment in which a task scheduling system according to a first embodiment of the present invention operates.

FIG. 2 is a block diagram showing a configuration of a task scheduling system of the first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing an example of a task graph.

FIG. 4 is a flowchart showing an operation of the task scheduling system according to the first exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a schedule result of the task scheduling system according to the first embodiment of this invention.

FIG. 6 is a diagram showing a task allocation list and bus usage information in the task scheduling system of the first exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a task scheduling system according to a second exemplary embodiment of the present invention.

FIG. 8 is a diagram showing possible arrangement times in the task scheduling system of the second exemplary embodiment of the present invention.

FIG. 9 is a flowchart showing an operation of a task rearrangement unit in the task scheduling system according to the second exemplary embodiment of the present invention.

FIG. 10 is a diagram showing an example of bus usage information stored in a bus usage information storage unit in the task scheduling system of the second exemplary embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional task scheduling system.

[Explanation of symbols]

1 task input means 2, 5 Data processing unit 3, 6 Data storage 4 Execution time output means 8, 9 task scheduling system 15 bus 21 task graph generator 22, 24, 51 task placement means 23 Task relocation means 31 task graph storage 32 task allocation list storage unit 33, 34 Bus usage information storage unit 61 task graph 62 Task placement list 63 Bus usage information 100 multiprocessor system 221 trigger generator 222 Task registration means 223 Forward list 224 Reverse list 225 task selection means 511 task registration means 512 Executable task queue 513 Processor-specified task queue 514 task selection means A1-A8, C1-C5 steps

Claims (33)

[Claims] 1. When performing multitask processing of a plurality of tasks in a multiprocessor system including a plurality of processors, based on a task graph showing a dependency of each task including a task whose execution processor is designated, In a static task scheduling system that performs task scheduling of each task before execution of each task, a trigger generator that determines a processor to be designed and a task whose execution processor is the processor to be designed are prioritized. A forward list registered in descending order of priority, a backward list in which tasks whose execution target is the processor to be designed is registered in descending order of priority, and a task in the forward list and the backward list Task registration means for registering the forward list or the reverse list. Select a list of either countercurrent list, task scheduling system, characterized in that it comprises a task selection means for determining the execution time of each task based on the selected list. 2. An execution time of a transfer task that transfers data via the bus, and a settable range of the execution time of the transfer task in which the execution times of other transfer tasks do not change even if the execution time is changed. If the execution times of a plurality of transfer tasks overlap with each other, the execution times of the transfer tasks are relocated within the settable range by referring to the bus usage information registered in The task scheduling system according to claim 1, further comprising: a task relocation unit that performs the task relocation. 3. A range in which a critical path value is equal between an execution time of a direct predecessor task whose execution time is closest to that of the transfer task and an execution time of a direct successor task whose execution time is closest to that of the transfer task The task scheduling system according to claim 2, wherein the settable range is set. 4. The trigger generator, when all the undecided tasks whose execution times have not been decided are designated to be executed by processors not included in the design target, the undecided tasks Of the above tasks, the task specified by the task with the highest priority in the forward direction is included in the design target, and the first processor that is the design target is specified. The task scheduling system according to any one of claims 1 to 3, wherein the second processor is included in a design target when a task that performs data transfer with two processors is a scheduling target. 5. The priorities of the respective tasks are given equally in the forward direction and the backward direction, and are given such that the longer the longest path length from the end task to the respective tasks in the task graph, the higher the priority. The task scheduling system according to any one of claims 1 to 4. 6. As a forward priority, a task having a longest path length from a terminal task in the task graph to each task is given a high priority, and tasks having the same path length directly succeed each other. A task with a large number of tasks is given a high priority, and as a reverse direction priority, a task with the longest path length from the end task to each task in the task graph is given a high priority and the path length is The task scheduling system according to any one of claims 1 to 4, wherein tasks having the same number of are assigned a higher priority to a task having a smaller number of direct preceding tasks. 7. The task registration means, when registering each of the tasks in the forward list,
The execution time of the direct predecessor task of each task is determined, or even if the execution time of the direct predecessor task is undecided, execution is specified in a processor that does not include the direct predecessor task in the design target. Registered tasks in the order of higher priority in the forward direction according to the priority, when registering each of the tasks in the backward list,
The execution time of the direct successor task of each task excluding the task with lower priority in the opposite direction than the task that triggered the design of the processor has been determined, or the execution time of the direct successor task has not been determined. 7. If the direct successor task is also specified to be executed by a processor that is not included in the design target, the respective tasks are registered in the ascending order of priority in the backward direction according to the priority. Task scheduling system. 8. The task selecting means, when the execution time of the task with the highest priority in the forward direction among the tasks whose execution is designated by the processor to be designed has already been arranged, 8. The task scheduling system according to claim 1, wherein the forward list is selected, and when the execution time of the task is not arranged, the backward list is selected. 9. The task selecting means selects, in the case of selecting the forward list, a task having the highest forward priority among the tasks designated to be executed by the processor to be designed. Of the later of either the execution time or the execution time immediately after the preceding task, the execution time of the scheduled task is placed at the earliest time that can be executed, and if the backward list is selected, Place the execution time of the scheduled task at the latest executable time of the execution time of the task that triggered the design on the processor or the time immediately before the subsequent task, whichever is earlier. The task scheduling system according to claim 1. 10. A multiprocessor system including a plurality of processors connected by a bus, when performing multitask processing of a plurality of tasks, a task indicating a dependency relationship of a plurality of tasks including a task whose execution processor is designated. In a static task scheduling system that performs task scheduling of each task before execution of each task based on a graph, the execution time of a transfer task and the execution time of another transfer task even if the execution time is changed. When the execution time of a plurality of transfer tasks overlaps with each other by referring to the bus usage information in which the settable range of the execution time of the transfer task that does not change is registered and the bus usage information And a task rearrangement means for rearranging the execution time of each transfer task within the range. Task scheduling system. 11. A range in which a critical path value is equal between the execution time of a direct predecessor task whose execution time is closest to that of the transfer task and the execution time of a direct successor task whose execution time is closest to that of the transfer task is The task scheduling system according to claim 10, wherein the range is settable. 12. When performing multitask processing of a plurality of tasks in a multiprocessor system including a plurality of processors, based on a task graph showing a dependency relationship of each task including a task whose execution processor is designated, In a static task scheduling method of performing task scheduling of each task before execution of each task, a first step of determining a processor to be designed, and a task having the processor to be designed as an execution processor Second to register in the forward list in descending order of priority
And a step of registering a task whose execution target is the processor to be designed in the backward list in order of low priority.
And a fourth step of selecting either the forward list or the backward list and determining the execution time of each task based on the selected list. Task scheduling method. 13. An execution time of a transfer task that transfers data via the bus, and a settable range in which the execution time of another transfer task does not change even if the execution time is changed are registered in the bus use information. A fifth step, and referring to the bus usage information, when the execution times of a plurality of transfer tasks overlap, the execution times of the transfer tasks are rearranged within the settable range. The task scheduling method according to claim 12, further comprising: 14. A range in which a critical path value is equal between the execution time of a direct predecessor task whose execution time is closest to that of the transfer task and the execution time of a direct successor task whose execution time is closest to that of the transfer task is The task scheduling method according to claim 13, wherein the settable range is set. 15. In the first step, if all undecided tasks whose execution times have not been decided are designated to be executed by a processor that is not included in the design target, each undecided task is undecided. Among the tasks, the processor specified by the task with the highest priority in the forward direction is included in the design target, the task that specifies the first processor of the design target is scheduled, and the processor is included in the target processor and the design target. The task scheduling method according to any one of claims 12 to 14, wherein the second processor is included in a design target when scheduling a task for performing data transfer with a second processor that is not included. 16. The priority of each task is given equally in the forward direction and the backward direction, and is given such that the longer the longest path length from the end task to each of the tasks in the task graph, the higher. Any one from 12 to 15
The task scheduling method described in the item. 17. As a forward priority, a task having a longest path length from the end task to each task in the task graph is given a high priority, and tasks having the same path length have a direct successor number of tasks. Is assigned to a task having a longest path length from the end task to each task in the task graph as a priority in the opposite direction. The task scheduling system according to claim 12, wherein a task having a small number of direct preceding tasks is given high priority. 18. In the second step, the execution time of the direct predecessor task of each task is determined, or even if the execution time of the direct predecessor task is not determined, the direct predecessor task becomes the design target. When execution by a processor that is not included is specified, the tasks are registered in the order of higher priority in the forward direction according to the priority, and in the third step, the reason why the processor becomes a design target is given. The execution time of the direct successor task of each task excluding tasks with lower priority in the opposite direction to the specified task has been determined, or the direct successor task is designed even if the execution time of the direct successor task has not been determined. 17. When execution by a processor which is not included in the target is designated, the respective tasks are registered according to the priority in ascending order of priority in the backward direction. Task scheduling method of others 17 wherein. 19. In the fourth step, when the execution time of the task with the highest priority in the forward direction among the tasks whose execution is specified by the processor to be designed has been allocated, 19. The task scheduling method according to claim 12, wherein the forward list is selected, and when the execution time of the task is not arranged, the backward list is selected. 20. In the fourth step, when the forward list is selected, the task with the highest forward priority is selected from among the tasks whose execution is designated by the processor to be designed. The scheduled task is placed at the earliest executable time, whichever is later, either the execution time of the task or the execution time immediately after the preceding task, and when the backward list is selected, the processor 13. The task to be scheduled is placed at the latest executable time of either the execution time of the task that triggered the design in 1. or the time immediately before the subsequent task, whichever is earlier. 20. The task scheduling method according to claim 1. 21. In a multiprocessor system including a plurality of processors connected by a bus, when performing multitask processing of a plurality of tasks, a task indicating a dependency relationship of a plurality of tasks including a task whose execution processor is designated. In a static task scheduling method for performing task scheduling of each task before execution of each task based on a graph, an execution time of a transfer task and an execution time of another transfer task even if the execution time is changed. The first step of registering the settable range of the execution time of the transfer task, which does not change, as bus usage information; and referring to the bus usage information, when the execution times of a plurality of transfer tasks overlap, A second step of rearranging the execution time of each transfer task within the settable range. Task scheduling method to the symptoms. 22. A range in which a critical path value is equal between the execution time of a direct predecessor task having the closest execution time to the transfer task and the execution time of a direct successor task having the closest execution time to the transfer task is set. The task scheduling method according to claim 21, wherein the settable range is set. 23. When performing multitask processing of a plurality of tasks in a multiprocessor system including a plurality of processors, based on a task graph showing a dependency relationship of each task including a task whose execution processor is designated, A program for causing a computer to execute static task scheduling of each task, determining a processor to be designed, and assigning tasks having the processor to be designed as an execution processor to a forward list in descending order of priority. Register, register a task whose execution target is the processor to be designed in the backward list in order of low priority, select either the forward list or the backward list, and select The computer executes the process of determining the execution time of each task based on the list. Program to be executed. 24. The execution time of a transfer task that transfers data via the bus, and a settable range in which the execution time of another transfer task does not change even if the execution time is changed are registered in the bus usage information. , If the execution times of a plurality of transfer tasks overlap with each other by referring to the bus use information, in order to further cause the computer to execute a process of rearranging the execution times of the transfer tasks within the settable range. 24. The program according to claim 23. 25. A range in which a critical path value is equal between the execution time of a direct predecessor task having the closest execution time to the transfer task and the execution time of a direct successor task having the closest execution time to the transfer task The program according to claim 24, which is set within a settable range. 26. When all undecided tasks whose execution times have not been decided are designated to be executed by a processor that is not included in the design target, a forward direction Include the processor specified by the task with the highest priority in the design target, perform the task schedule of the task that specifies the first processor that is the design target, and set the target processor and the second processor not included in the design target. 26. The program according to any one of claims 23 to 25, wherein the second processor is included in a design target when a task for performing data transfer is scheduled. 27. The priorities of the respective tasks are given equally in the forward direction and the backward direction, and the higher the longer the longest path length from the end task to the respective tasks in the task graph, the higher the priority. Any one of 23 to 26
The program described in the section. 28. As a forward priority, a task having a longest path length from the end task to each task in the task graph is given a high priority, and tasks having the same path length are directly followed. Is assigned to a task having a longest path length from the end task to each task in the task graph as a priority in the opposite direction. 27. The program according to claim 23, wherein a task having a small number of direct preceding tasks is given high priority. 29. The execution time of the direct predecessor task of each task is determined, or even if the execution time of the direct predecessor task is undecided, the direct predecessor task is not included in the design targets. When execution is specified, each task is registered in the forward list in the order of high priority in the forward direction according to the priority, and the task is prioritized in the backward direction over the task that triggered the design. Execution time of the direct successor task of each task excluding infrequent tasks has been determined, or even if the execution time of the direct successor task has not been determined, the direct successor task is not included in the design target. 29. When execution is specified, the respective tasks are registered in the backward list in order of decreasing backward priority according to the priority. Of the program. 30. Among the tasks whose execution is designated by the processor to be designed, when the execution time of the task with the highest forward priority has been allocated, the forward list is selected. The program according to any one of claims 23 to 29, wherein the backward list is selected when the execution time of the task has not been allocated. 31. When the forward list is selected, the execution time of the task with the highest forward priority among the tasks whose execution is designated by the processor to be designed, or the preceding task The task to be scheduled is placed at the earliest time that can be executed, whichever is later than the execution time immediately after, and when the backward list is selected, there is an opportunity to start designing on the processor. 31. The task to be scheduled is arranged at the latest executable time of either the latest execution time of the failed task or the previous time of the succeeding task, whichever is earlier. The listed program. 32. When performing multitask processing of a plurality of tasks in a multiprocessor system including a plurality of processors connected by a bus, a task indicating a dependency relationship among the tasks including a task whose execution processor is designated. A program for causing a computer to execute static task scheduling of each task based on a graph, wherein the execution time of a transfer task and the execution times of other transfer tasks do not change even if the execution time is changed. The settable range of the transfer task execution time is registered as bus usage information, and when the execution times of a plurality of transfer tasks are overlapped by referring to the bus usage information, each of the settable ranges is set in the settable range. A program that causes a computer to execute the process of rearranging the execution time of a transfer task. 33. A range in which a critical path value is equal between the execution time of a direct predecessor task having the closest execution time to the transfer task and the execution time of a direct successor task having the closest execution time to the transfer task is defined as 33. The program according to claim 32, which is within a settable range.