JP2003028607A - Capacitance detector and fingerprint collation apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a charging voltage is limited by the power- supply voltage of a detector although the detection sensitivity of a capacitance can be increased by increasing the charging voltage of a detection electrode, or by reducing a reference capacitance in the case of a voltage charging method, and that the influence of a disturbance noise or a noise in the operation of a circuit is increased so as to worsen an S/N ratio when the reference capacitance is reduced. SOLUTION: Under the control of a switching operation by a timing controller 16, a switch SA is first turned on at a sensor cell 100-k. The potential of the detection electrode is set to a reference potential (a GND level in this example). The switch SA is then turned off. A switch SB is turned on and the electric charge of the sensor cell 100-k is taken into the reference capacitance Cf1. The above procedure is repeatedly performed. The number of times of the operation is increased, the detection sensitivity is increased. A noise component is reduced by an averaging (integration) processing operation, and only a signal component is taken out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic capacitance detection device and a fingerprint collation device using the same, and particularly to an electrostatic capacitance detection device suitable for use as a fingerprint detection device and a fingerprint collation device using the detection device. Regarding

[0002]

2. Description of the Related Art As a fingerprint detection device (fingerprint sensor),
As shown in FIG. 6, the detection electrodes 101 that form the sensor cells 100 are arranged in an array on the surface of the semiconductor, and row selection lines ...
n-1, 102n, 102n + 1, ... And column sense lines ..., 103m-1, 103m, 103m + 1, ... Are wired in a matrix, and each of the detection electrodes 101 and column sense lines ..., 103m-1, 103m, 103m + 1 ,. , And cell selection switches Sr are connected between them, and these cell selection switches Sr are connected to row selection lines ... 102n-1, 102n, 10
A configuration is known in which selection is performed in units of rows via 2n + 1, ....

In this fingerprint detecting device, as shown in FIG. 7, when a finger is placed on the overcoat 104 covering the detecting electrode 101, the unevenness of the fingerprint is detected between the detecting electrode 101 and the surface of the finger. The principle of acquiring a fingerprint pattern (fingerprint pattern) by detecting the electrostatic capacitance Cs formed by the above is used. That is, regarding the electrostatic capacitance Cs formed between the detection electrode 101 and the surface of the finger, the distance between the detection electrode 101 and the detection electrode 101 becomes short at the ridge portion of the fingerprint, so that the capacitance value becomes large, and In the part, the detection electrode 10
Since the distance to 1 is long and the capacitance value is small, the fingerprint pattern can be obtained by detecting the capacitance Cs. Note that, in FIG. 7, the capacitance Cp is a parasitic capacitance between the detection electrode 101 and the Si substrate.

As a method of detecting the electrostatic capacitance Cs,
A voltage charging method in which the electrostatic capacitance Cs is charged with a constant voltage to detect electric charges accumulated in the electrostatic capacitance Cs, and a charge charging method in which the electrostatic capacitance Cs is charged with a constant electric charge to detect a voltage change. Is known.

First, an example of the former voltage charging method will be described with reference to FIG. 8 showing a circuit diagram of the principle. Here, the circuit system of the m-th column in FIG. 6 will be described as an example.

In FIG. 8, a column sense line 103m of m columns
The detection circuit 105m is connected to one end of the. In the detection circuit 105m, the negative phase (-) input terminal is the column sense line 10
An operational amplifier OP having a positive phase (+) input terminal connected to the voltage supply line 106 and a reference capacitance Cf connected between the negative phase input terminal and the output terminal of the operational amplifier OP; It has a reset switch Sb connected in parallel with the reference capacitance Cf. Voltage supply line 106
, A constant charge voltage Vc or a predetermined reference voltage Vref is alternatively applied to the switch.

At the output end of the detection circuit 105m, that is, the output end of the operational amplifier OP, the sample and hold circuit 107m is connected.
The input end of is connected. Sample and hold circuit 1
07m is the output terminal of the detection circuit 105m and the output signal line 10
Sampling switch Ss connected in series with 8
And the column selection switch Sc and these switches Ss, S
The holding capacitor Ch is connected between the common connection point Q of c and the ground. The output signal of the sample & hold circuit 107m is output from the output signal line 108 via the output buffer 109.

In the above structure, if the electrostatic capacitance to be detected is Cs and the charging voltage to this electrostatic capacitance Cs is ΔV, the output voltage Vsns of the detection circuit 105m is Vsns =-(Cs / Cf) × ΔV Become. As is clear from this equation, in order to increase the detection sensitivity of the electrostatic capacitance Cs, the charge voltage Δ of the detection electrode 101 can be increased.
It is only necessary to increase V or set the reference capacitance Cf small.

Next, an example of the latter charge charging method will be described with reference to FIG. 9 showing a circuit diagram of the principle.

In FIG. 9, row drive lines 111 and column sense lines 112 are arranged in a matrix with respect to the detection electrodes 101 arranged in an array. Power line 113
Between the column sense line 112 and the column sense line 112.
Nch selecting hMOS transistor Q1 and row
The MOS transistor Q2 is connected in series. The gate of the MOS transistor Q1 is the detection electrode 101.
The gate of the MOS transistor Q2 is connected to the row drive line 111.
Respectively connected to.

A PchMOS transistor Q3 and a charging current source Ic are connected in series between the power supply line 111 and the ground. The gate of the MOS transistor Q3 is connected to the reset line 114. The common connection point P between the MOS transistor Q3 and the charging current source Ic is the NchMOS transistor Q.
It is connected to the detection electrode 101 via 4. And
The gate of the MOS transistor Q4 is the charge control line 11
Connected to 5.

The detection circuit having the above structure is provided for each detection electrode 101, that is, for each sensor cell. here,
The circuit operation of this detection circuit will be described with reference to the timing chart of FIG.

First, a high level (hereinafter referred to as "H" level) row drive signal RAD is applied via the row drive line 111 to turn on the MOS transistor Q2, and then via the charge control line 115. Then, the MOS transistor Q4 is turned on by supplying the "H" level charge control signal CEN. Thereby, the row is selected.

At the same time as this row selection, the reset control line 11
A low level (hereinafter, referred to as “L” level) reset signal XRST is applied via 4 to turn on the MOS transistor Q3. Thereby, the detection electrode 1
The voltage 01 (hereinafter referred to as the detection voltage) VS is reset to the power supply voltage VDD which is the reference voltage. After that, the reset signal XRST transits to the “H” level,
The S transistor Q3 is turned off. As a result, the charge of the detection electrode 101 by the current source Ic is started through the MOS transistor Q4.

After the elapse of a certain time Tc, the charge control signal CEN transitions to the "L" level, and the MOS transistor Q4 is turned off. Thereby, the detection electrode 1
The charging of the electric charge for 01 ends. The voltage change amount from the reset of the detection electrode 101 at this time becomes the detection voltage Vsns, which is read out to the column sense line 112 through the source follower MOS transistor Q1 and the row selection MOS transistor Q2. Is output to the outside through.

Here, when the charging current to the electrostatic capacitance Cs is Ic and the charging time to the electrostatic capacitance Cs is Tc, the detection voltage Vsns becomes Vsns = (Ic × Tc) / Cs. As is clear from this equation, the detection voltage Vsns
In order to increase the detection sensitivity of the electrostatic capacitance Cs within the limited dynamic range, the reference charge (Ic × Tc) should be set small.

[0017]

Here, the electrostatic capacitance Cs
Considering the improvement of the detection sensitivity of the above, as described above, in the former voltage charging method, the charge voltage ΔV of the detection electrode 101 may be increased or the reference capacitance Cf may be decreased. If the reference capacitance Cf is reduced by the power supply voltage of the device, the influence of disturbance noise and noise during circuit operation increases, and the S / N ratio deteriorates. Further, for example, when the AC charge noise of the amplitude ΔQn is received, it depends on the timing of charging and sensing, but in the worst case, the noise charge of ΔQn is received. Therefore, when converted into the output voltage of the detection circuit 105m, the noise voltage is changed. Is ΔQn / Cf. This noise voltage is the reference capacitance C
If f is made small, it becomes large, which causes deterioration of S / N.

On the other hand, in the latter charge charging method, the detection sensitivity of the electrostatic capacitance Cs can be increased within the limited dynamic range of the detection voltage Vsns by setting the reference charge (Ic × Tc) small. However, similar to the voltage charging method, when AC charge noise of amplitude ΔQn is applied, noise of ΔQn is added to the reference charge of (Ic × Tc) in the worst case, so the S / N at this time is ΔQ.
It becomes n / (Ic × Tc), and if (Ic × Tc) is reduced, the S / N deteriorates.

Actually, considering the case where the above-mentioned fingerprint detecting device is mounted on an electric device such as a notebook type personal computer, in these devices, a DC voltage is generally supplied from an AC power source through a switching power source. Switching noise from the switching power supply is superimposed on the internal power supply voltage. Therefore, this switching noise becomes the above-mentioned asynchronous disturbance noise, and becomes a factor that causes S / N deterioration and malfunction of the fingerprint detection device (electrostatic capacitance detection device). That is, with any of the above-mentioned detection methods, there is a problem that the improvement of the detection sensitivity is limited as it is, and that it is weak against the asynchronous disturbance noise.

The present invention has been made in view of the above problems, and it is an object of the present invention to significantly improve the detection sensitivity without degrading the S / N and also significantly improve the resistance to asynchronous disturbance noise. An object of the present invention is to provide an improved electrostatic capacitance detection device and a fingerprint collation device using the same.

[0021]

A capacitance detection device according to the present invention comprises a detection electrode, a first switch connected between the detection electrode and a reference potential, and a connection between the detection electrode and a sense line. A sensor cell having a second switch, a detection means for capturing the electric charge output from the sensor cell to the sense line via the second switch into a reference capacitor and converting the electric charge into a voltage signal, and the first switch. It is configured to include a control means for turning on and then turning off the second switch to turn on the second switch to repeatedly perform the operation of taking the electric charge of the sensor cell into the reference capacitance of the detection means. . Then, this electrostatic capacitance detection device is used as a fingerprint detection means in a fingerprint collation device.

In the electrostatic capacitance detection device having the above structure or the fingerprint collation device using the electrostatic capacitance detection device as a fingerprint detection means, the first switch is first turned on under the switching control of the control means, and the potential of the detection electrode is used as a reference. Set to potential. Next, after turning off the first switch, the second switch is turned on to short-circuit the detection electrode and the sense line. Electric charges move from the detection electrode of the sensor cell to the reference capacitance of the detection means through the second switch and the sense line due to the potential change of the sense line at this time. Then, this series of operations is repeatedly executed. By repeating this, the averaging (integration) processing is performed, the noise component is reduced, and only the signal component is extracted. Further, since the signal to be detected is determined by the number of repetitions, the detection sensitivity is increased by increasing the number of repetitions.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a capacitance detection device according to an embodiment of the present invention,
Here, the case where it is used as a fingerprint detection device (fingerprint sensor) is shown as an example.

As shown in FIG. 1, the electrostatic capacitance detection device according to this embodiment has a sensor array section 11, a parasitic capacitance cancellation circuit 12, a detection circuit 13, a parallel-serial conversion circuit 14, and an output circuit 15. Has become. Similar to FIG. 6, in the sensor array portion 11, the detection electrodes forming the sensor cells are arranged in an array on the surface of the semiconductor by m columns × n rows. Here, one row of sensor cells 100-1, ..., 100-k ,.
Only 00-m shows the circuit configuration of the cell.

In the sensor array section 11, column sense lines 103-1, 103-k, 103-m are provided for each column, and row selection lines are provided for each row as in FIG. Although not shown in the drawing, a row drive circuit for driving these row selection lines and a drive for outputting the detection voltage read out in parallel to the parallel-serial conversion circuit 14 through the detection circuit 13 are output. It is assumed that a column drive circuit for performing the operation is provided.

In the following specific description, the circuit system of the k column shown in FIG. 2, that is, the sensor cell 100-k, the parasitic capacitance cancel circuit 12-k, the detection circuit 13-k, and the parallel-serial conversion circuit 14-k. Will be described as an example.

In the sensor cell 100-k, the capacitance C
s is an electrostatic capacitance formed between the detection electrode and the finger surface, and capacitance Cp is a parasitic capacitance between the detection electrode and the semiconductor substrate. The sensor cell 100-k includes a first switch SA connected between a detection point X of the electrostatic capacitance Cs and a reference potential point, for example, a ground GND, a detection point X, and a column sense line 103-k. And a second switch SB connected between them. These switches SA and SB are drive-controlled by the row drive circuit shown in FIG. 6, and only one selected row becomes active. For cells in the non-selected rows, the switch SA is on and the switch SB is off. It is assumed to be stopped in the state.

In the parasitic capacitance cancel circuit 12-k, not only the electrostatic capacitance Cs is formed between the detection electrode and the finger surface, but also the parasitic capacitance Cp exists between the detection electrode and the semiconductor substrate. An offset corresponding to the parasitic capacitance Cp is generated when the electrostatic capacitance Cs is detected, and the dynamic range of the detection circuit 13 is pressed. Therefore, the offset is provided to solve the problem caused by the parasitic capacitance Cp. .

Therefore, the parasitic capacitance cancel circuit 12
-K has a dummy detection electrode (hereinafter abbreviated as a dummy electrode) formed in the same manner as each detection electrode of the sensor array unit 11 outside the region of the sensor array unit 11 for each column. Therefore, a parasitic capacitance Cp ′ is also provided between the dummy electrode and the semiconductor substrate as in the case of each detection electrode of the sensor array section 11. In the parasitic capacitance cancel circuit 12-k, a switch SC is connected between the detection point Y of the parasitic capacitance Cp ′ and a reference potential point, for example, the power supply VDD. Further, the detection point Y and the column sense line 103-k
A switch SD is connected between and.

The detection circuit 13-k includes an operational amplifier OP1 whose negative phase input terminal is connected to one end of the column sense line 103-k.
And a reference capacitor Cf1 connected between the negative phase input terminal and the output terminal of the operational amplifier OP1, and a reset switch SE connected in parallel with the reference capacitor Cf1. A voltage (VDD / 2) that is half the power supply voltage VDD is applied to the positive-phase input terminal of the operational amplifier OP1.

A parallel-serial conversion circuit 14 is connected to the output terminal of the detection circuit 13-k. The parallel-serial conversion circuit 14 includes a first sample-and-hold circuit 142-k provided for each column between the output end of the detection circuit 13-k and the output signal line 141, and the output signal line 141. The output amplifier 143 is connected to the input terminal, and the second sample and hold circuit 144 is connected to the output terminal of the output amplifier 143.

First sample and hold circuit 142-k
Is connected between the sampling switch SF and the column selection switch SG connected in series between the output terminal of the detection circuit 13-k and the output signal line 141, and the common connection point of these switches SF and SG and the ground. Hold capacity C
and h1. Output amplifier 143
Is a detection circuit 13-k which receives the reference voltage VOS as a positive phase input and is supplied through the sample & hold circuit 142-k.
Operational amplifier OP2 in which the detection voltage Vsns of
And a reference capacitor Cf2 connected between the negative phase input terminal and the output terminal of the operational amplifier OP2, and a reset switch SH connected in parallel to the reference capacitor Cf2.

The second sample and hold circuit 144 is
A sampling switch SI whose input end is connected to the output end of the output amplifier 143, that is, the output end of the operational amplifier OP2.
And a hold capacitance Ch2 connected between the output terminal of the sampling switch SI and the ground. The output circuit 15 has a buffer configuration including an operational amplifier OP3 in which the hold output of the hold capacitor Ch2 in the second sample & hold circuit 144 is used as the positive phase input and the negative phase input end and the output end are short-circuited.

Next, the circuit operation of the electrostatic capacitance detection device according to this embodiment having the above-mentioned configuration will be described with reference to the timing chart of FIG. 3 using the circuit system of the k-column shown in FIG. In the timing chart of FIG. 3, the switch SA
Regarding "-SF", the "H" level means on and the "L" level means off. Further, the switches SA to SF in the initial state are all turned off. The switch S
Timing controller 1 for on / off control of A to SI
6 shall be performed.

First, at time t1, the reset switch SE of the detection circuit 13-k is turned on, and the electric charge of the reference capacitance Cf1 is set to 0.
To At this time, the column sense line 103-k is virtually grounded to VDD / 2 by the action of the operational amplifier OP1. At the same time, the switch S of the sensor cell 100-k
A is turned on to set the potential Vcell of the detection electrode to the ground level, the switch SC of the parasitic capacitance canceling circuit 12-k is turned on, and the potential Vdmy of the dummy electrode is set to V
Set to DD level.

At this time, the switch SB of the sensor cell 100-k and the switch SD of the parasitic capacitance cancel circuit 12-k are both in the off state. After that, the reset switch SE of the detection circuit 13-k and the sensor cell 10
0-k switch SA and parasitic capacitance cancel circuit 1
Both 2-k switches SC are turned off. At this time, since the electric charge is held in each node, the potential does not change.

Next, at time t2, the sensor cell 100-k
The switch SB of is turned on to detect the detection electrode and the column sense line 103.
-K and short. At this time, the column sense line 103-k
Is virtually grounded to VDD / 2 by the detection circuit 13-k, the potential Vcel of the detection electrode changes from the ground level to VDD / 2. Due to this change in potential, the reference electrode Cf1 of the detection circuit 13-k moves from the detection electrode to −
The electric charge of {(VDD / 2) × (Cs + Cp)} moves through the switch SB.

At time t2, the switch SD of the parasitic capacitance cancel circuit 12-k is further turned on to short-circuit the dummy electrode and the column sense line 103-k. At this time, the potential Vdmy of the dummy electrode changes from VDD to VDD / 2, so that the reference capacitance Cf1 of the detection circuit 13-k from the dummy electrode.
Then, the charge of (VDD / 2) × Cp ′ moves through the switch SD.

After all, the reference capacitance Cf1 has-{(VDD
/ 2) × (Cs + Cp−Cp ′)} charges are accumulated, so the detection voltage Vsns of the detection circuit 13-k is Vsns = (VDD / 2) + {(VDD / 2) × (Cs
+ Cp-Cp ')} / Cf1. At this time, if the dummy electrode is designed so that Cp = Cp ′, Vsns = (VDD / 2) + {(VDD / 2) × Cs}
/ Cf1 and the offset due to the parasitic capacitance Cp of the detection electrode can be canceled.

After that, the switch SB of the sensor cell 100-k and the switch SD of the parasitic capacitance cancel circuit 12-k are both turned off. At this time, since the electric charge of each node is held, the potential does not change.

At time t3, again, the sensor cell 100-k
Switch SA and parasitic capacitance cancel circuit 12-k
Both switches SC are turned on to detect the potential Vcel of the detection electrode.
l to the ground level and the potential Vdmy of the dummy electrode to V
Set to DD level. After that, the above-described series of operations based on the on / off control of the switches SA and SC and the switches SB and SB, that is, the operations from time t1 to time t3 are performed at time t3.
~ Time t5, time t5 ~ time t7, ... are sequentially repeated.

Each time this cycle is repeated, the detection voltage Vsns of the detection circuit 13-k increases by ΔVsns = {(VDD / 2) × Cs} / Cf1 = {VDD / (2 × Cf1)} × Cs. When this cycle is repeated K times in total, the detection voltage Vsns becomes Vsns = VDD / 2 + K × ΔVsns = VDD / 2 + K × {VDD / (2 × Cf1)} × Cs.

After repeating the cycle from time t1 to time t3 K times, both the switch SB of the sensor cell 100-k and the switch SC of the parasitic capacitance cancel circuit 12-k are turned off. Then, at time t8, the first sample-and-hold circuit 14 in the parallel-serial conversion circuit 14
The 2-k sampling switch SF is turned on. As a result, the detection voltage Vsns of the detection circuit 13-k is loaded into the first sample & hold circuit 142-k and held in the hold capacitor Ch1.

The operation of the k-column circuit system has been described above as an example, but the operations up to this point are simultaneously performed on a row-by-row basis in all columns. Then, in the parallel-serial conversion circuit 14, the voltages held in the hold capacitors Ch1 of the first sample & hold circuits 142-1 to 142-m for each column are sequentially output from a column drive circuit (not shown). The output column drive signal sequentially turns on and off the respective column selection switches SG of the first sample & hold circuits 142-1 to 142-m for serial conversion, and the output signal line 141, the output amplifier 143, and It is output via the second sample & hold circuit 144.

As described above, in the capacitance detecting device according to the present embodiment, the switch SA is first turned on in the sensor cell 100-k under the switching control of the timing controller 16 so that the potential of the detection electrode is used as a reference. The potential (in this example, the GND level) is set, and then the switch SA is turned off and then the switch SB is turned on to charge the sensor cell 100-k with the reference capacitance Cf of the detection circuit 13-k.
The signal Vsig detected by repeatedly performing the operation of taking in 1 becomes Vsig = K × {VDD / (2 × Cf1)} × Cs.

Therefore, the output sensitivity (detection sensitivity) is increased by increasing the number of repetitions K in which the charge of the sensor cell 100-k is taken into the reference capacitance Cf1 of the detection circuit 13-k.
Can be raised. That is, since the detection sensitivity can be controlled by changing the number of repetitions K, the detection circuit 13 can be controlled as in the conventional technique of the voltage charging method.
There is no need to externally control the charge voltage applied to the positive phase input terminal of the -k operational amplifier OP1.

As described above, since the detection sensitivity can be greatly improved by increasing the number of repetitions K, the film thickness of the overcoat (corresponding to the overcoat 104 in FIG. 7) covering the detection electrode of the sensor cell 100-k is increased. Therefore, the surface strength and electrostatic strength of the sensor cell 100-k can be improved. Moreover, since the detection sensitivity can be set to the number of repetitions K, that is, digitally controlled, a D / A converter for sensitivity adjustment is not required, which contributes to simplification of the circuit configuration of the entire apparatus and cost reduction.

Further, as in the case of the prior art, the amplitude ΔQn
Considering the case in which the AC charge noise of
However, compared with the prior art of the voltage charging method, for example, averaging (integration) processing is performed by repeating the operation of taking in the charge of the sensor cell 100-k to the reference capacitance Cf1 of the detection circuit 13-k. Since the noise component is reduced and only the signal component is extracted, the reference capacitance Cf1 can be set to K times that of the conventional technique if the detection sensitivity is set to the same as that of the conventional technique. . Therefore, the output voltage ΔQn / Cf1 of the detection circuit 13-k due to the noise charge ΔQn becomes 1 / K, so that the S / N can be improved by K times, and it becomes resistant to disturbance noise.

Here, in the capacitance detecting device according to the above embodiment, the reference voltage serving as the charge voltage is set to the ground level in the sensor cell 100-k, but this is only an example and the present invention is not limited to this. Not a thing. However, it is preferable to set the reference voltage to the ground level because the charge voltage can be obtained by using the potential of the semiconductor substrate that can be easily connected in the sensor cell 100-k, and the wiring is not required to that extent. .

In the above embodiment, the electrostatic capacitance detection device according to the present invention is a fingerprint detection device (fingerprint sensor).
However, the present invention is not limited to the fingerprint detection, but an overcoat that covers the detection electrode of the sensor cell 100-k (the overcoat 1 in FIG. 7 is used.
(Corresponding to 04)), it can be used for pattern detection of general concave-convex patterns in which electrostatic capacitance Cs is formed between the electrode and the detection electrode.

FIG. 4 is a block diagram showing an example of the configuration of a fingerprint collation device according to the present invention, which uses the electrostatic capacitance detection device according to the above-described embodiment as a fingerprint detection device (fingerprint sensor). As shown in FIG. 4, the fingerprint collation device 20 according to the present example includes a fingerprint detection device 21, an A / D converter 22, first and second memories 23 and 24, a registration unit 25, and a comparison unit 26. Has become.

In the fingerprint collation device 20 having the above structure, the capacitance detection device according to the above-described embodiment is used as the fingerprint detection device 21. That is, the fingerprint detection device 21
Responds to the fingerprint response between the detection electrode and the surface of the finger by repeating the operation of setting the potential of the detection electrode of the sensor cell to the reference potential and then capturing the charge in the reference capacitance of the detection circuit. The electrostatic capacitance Cs formed is detected with high detection sensitivity to obtain fingerprint information.

The output voltage of the fingerprint detection device 21 is stored in the first memory 23 after being digitized by the A / D converter 22. The registration unit 25 is used when registering a fingerprint pattern to be matched in advance, and extracts only feature points from the fingerprint information stored in the first memory 23 at the time of registration, The information of the characteristic point group is stored in the second memory 24 as registered pattern information.

The comparing unit 26 detects the detected fingerprint information stored in the first memory 21 and detected by the fingerprint detecting device 21 at the time of collating the fingerprint, for example, the second detected fingerprint.
The registered pattern information previously stored in the memory 24 of FIG. Then, when the detected fingerprint information matches the registered pattern information, the comparison unit 26 determines that the fingerprint detected by the fingerprint detection device 21 is a pre-registered fingerprint, and the collation result to that effect is output to the outside. Output to.

In the fingerprint collation device 20 according to this example,
Although the fingerprint information detected by the fingerprint detection device 21 is temporarily stored in the first memory 23, the first memory 23 can be omitted if the signal processing does not require it.

Further, as shown in FIG. 5, the fingerprint detecting device 2
1. The A / D converter 22 and the first memory 23 (the memory 23 can be omitted as shown by the dotted line) are configured as one unit 27, and the output of the unit 27 is sent to the personal computer 28. The personal computer 28 has the functions of the second memory 24, the registration unit 25, and the comparison unit 26.
It is also possible to combine these into a fingerprint collation device 20 '.

[0057]

As described above, according to the present invention,
After setting the potential of the detection electrode of the sensor cell as the reference potential,
By repeating the operation of fetching the electric charges into the reference capacitance of the detection circuit, the detection sensitivity can be significantly improved, so that the overcoat on the detection electrode can be made thicker and the surface of the sensor cell can be increased. The strength and electrostatic strength can be improved, and the resistance to asynchronous disturbance noise can be greatly improved, so that it becomes easy to take measures against power supply noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a capacitance detection device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a k-column circuit system.

FIG. 3 is a timing chart for explaining a circuit operation of the electrostatic capacitance detection device according to the embodiment.

FIG. 4 is a block diagram showing an example of a configuration of a fingerprint matching device according to the present invention.

FIG. 5 is a block diagram showing another example of the configuration of the fingerprint collation device according to the present invention.

FIG. 6 is a schematic diagram showing a basic configuration of a fingerprint detection device.

FIG. 7 is a principle diagram of a fingerprint detection device that senses capacitance.

FIG. 8 is a circuit diagram of the principle of the voltage charging method.

FIG. 9 is a circuit diagram showing the principle of the charge charging method.

FIG. 10 is a timing chart for explaining the operation of the charge charging method.

[Explanation of symbols]

11 ... Sensor array unit, 12, 12-1, 12-k,
12-m ... Parasitic capacitance cancel circuit, 13, 13-1,
13-k, 13-m ... Detection circuit, 14 ... Parallel-serial conversion circuit, 20, 20 '... Fingerprint collation device, 21 ... Fingerprint detection device, 100-1, 100-k, 100-m ... Sensor cell, 103 -1, 103-k, 103-m ... Column sense line, 141 ... Signal output line, 142-1, 142-
k, 142-m ... First sample-and-hold circuit, 14
3 ... Output amplifier, 144 ... Second sample & hold circuit

Continued front page    (72) Inventor Keiichi Shinozaki             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 2F063 AA43 BA29 BC04 CA08 CA29                       DA02 DC08 DD07 HA04 KA01                 4C038 FF01 FF05 FG00                 5B047 AA25 BB04

Claims (7)

[Claims] 1. A sensor cell having a detection electrode, a first switch connected between the detection electrode and a reference potential, and a second switch connected between the detection electrode and a sense line; Detection means for taking in the electric charge output from the sensor cell to the sense line via the second switch into a reference capacitance and converting it into a voltage signal; and turning on the first switch and then turning off the switch, An electrostatic capacitance detection device comprising: a control unit that controls to repeatedly perform an operation of turning on the second switch to take in the electric charge of the sensor cell into the reference capacitance of the detection unit. 2. The capacitance detection device according to claim 1, which is realized by a semiconductor device. 3. The capacitance detection device according to claim 2, wherein the reference potential is a semiconductor substrate potential. 4. The control unit controls the detection sensitivity of the detection unit by changing the number of times of repeating the charge of the sensor cell into the reference capacitance of the detection unit. Capacitance detection device. 5. The sensor cells are arranged in an array, and the detection means detects the capacitance formed between the detection electrode and the surface of the finger by taking in the charge of the sensor cell. The electrostatic capacitance detection device according to claim 1, wherein the fingerprint information is acquired by the fingerprint detection device. 6. An array of sensor cells having a detection electrode, a first switch connected between the detection electrode and a reference potential, and a second switch connected between the detection electrode and a sense line. Is formed between the detection electrode and the surface of the finger by incorporating the electric charge output from the sensor cell to the sense line via the second switch into the reference capacitor. A fingerprint detecting means having a detecting means for detecting a capacitance to obtain fingerprint information, and the sensor cell by turning on the first switch and then turning off the second switch. Control means for controlling to repeatedly execute the operation of fetching the electric charges of the above into the reference capacitance of the detection means, storage means for storing pattern information of a fingerprint registered in advance, said fingerprint detection A fingerprint collation device comprising: comparison means for comparing the fingerprint information acquired by the output means with the registered pattern information stored in the storage means, and outputting the comparison result as a fingerprint collation result. 7. The control means controls the detection sensitivity of the fingerprint detecting means by changing the number of times of repeating the charge of the sensor cell into the reference capacitance of the detecting means. Fingerprint matching device.