JP2003026500A - STRUCTURE OF CRYSTALLINE SiC THIN FILM AND METHOD OF PRODUCING THE SAME - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent loss of Ge in a buffer layer between forming cubic SiC and a Si substrate, and to provide a structure of a crystalline SiC thin film with which a high quality crystalline SiC thin film can be obtained and a method of producing the same. SOLUTION: A GeC buffer layer 12 is interposed at a hetero interface between the Si substrate 11 and the crystalline SiC thin film 13. Thereby, when the crystalline SiC thin film 13 is produced, the lattice mismatching of the cubic SiC and Si is reduced and the density of the crystal defects in the cubic SiC can be lowered. Further, it is possible to lower the formation temperature of the cubic SiC by utilizing a hydrogen plasma sputtering method. Consequently, the loss of Ge in the buffer layer is suppressed during formation of the cubic SiC and the crystalline SiC thin film 13 having higher quality is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a crystalline SiC thin film and a method for producing the same, and more specifically, crystalline Si thin film having a crystalline SiC thin film excellent in crystallinity formed on the surface of a Si substrate.
The present invention relates to a structure of a C thin film and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, cubic SiC called 3C-SiC (β-Si) has been developed. Cubic SiC is
Since it has a large band gap (2.2 eV) and a large electron mobility (1000 cm ² / Vs), it is expected to be a promising next-generation semiconductor substrate that can operate even at high temperatures. However, this cubic SiC can obtain only extremely small crystals of about several mm ² by the sublimation method or the liquid phase growth method. Therefore, in order to obtain a large-area crystal, it is necessary to carry out heteroepitaxial growth on a heterogeneous substrate. Usually heteroepitaxial (hereinafter, hetero)
Although Si is used as the growth substrate, the cubic S
iC was hard to get. So, as a kind of CVD method,
For example, as in "Method for producing silicon carbide thin film" described in JP-A-9-82643, the surface of a Si substrate is carbonized, and the surface thereof is chemically reacted to form crystalline SiC of cubic SiC.
Methods for forming thin films have been developed.

However, there is a difference in thermal expansion coefficient of about 8% between cubic SiC and Si, and about 20%.
Large lattice mismatch (lattice constant: _a3C-SiC = 4.
36 angstroms, a _Si = 5.43 angstroms). Therefore, the obtained crystalline SiC thin film has high-density (> 10 ⁹ cm ⁻² ) crystal defects (dislocations or stacking faults). Moreover, it is 1 in the CVD method.
A high growth temperature of about 350 ° C. (hereinafter, the temperature is the substrate temperature) is required. Therefore, it was not possible to obtain a high-quality crystalline SiC thin film due to the loss of Si during growth and the occurrence of a large stress at the interface between SiC and Si when the growth temperature returns to room temperature.

Therefore, as another conventional technique for solving this problem, "Surface Science vol21, 2000, pp348-
354 ", a method of manufacturing a crystalline SiC thin film is known. In this method, a SiGeC buffer layer is formed at the hetero interface between the Si substrate and the crystalline SiC thin film by hetero growth. In this way, the lattice mismatch between cubic SiC and Si is relaxed, and the crystal defect density in cubic SiC is further reduced. More specifically, Si having an atomic radius of 1.32 angstroms and C having an atomic radius of 0.91 angstroms have a larger atomic size, and Ge of the same IV element (atomic radius 1.37 angstroms) is introduced into the hetero interface. Thereby, the lattice constant of the buffer layer is adjusted. The adjustment of the lattice constant is performed by configuring the buffer layer 3
This is done by changing the content of each type of element. If the lattice constant of the buffer layer changes from the lattice constant of the Si substrate to the lattice constant of the SiC thin film, the lattice mismatch between the thin film and the substrate will be eliminated.

[0005]

However, in such a conventional method for producing a crystalline SiC thin film, there are two problems.
There are two major problems. First, Ge having a high crystallization temperature of the SiC thin film (1000 ° C. or higher) and an evaporation start temperature of about 650 ° C. in the buffer layer during growth of the SiC thin film.
Is that it evaporates. Secondly, since the SiGeC buffer layer is composed of three elements, adjustment of the lattice constant requires adjustment of the composition of three kinds of elements. In addition, it is difficult to control the composition of the SiGeC buffer layer in consideration of the fact that a chemical reaction method has to be used for producing the buffer layer and the effect of out-diffusion of Si in the Si substrate. As a result, high quality crystalline SiC
It was not possible to make a thin film. Therefore, the inventor introduced hydrogen plasma into the production of a thin film,
We succeeded in lowering the crystallization temperature of the SiC thin film to about 800 ° C. In addition, the buffer layer is composed of three-element SiGe.
By changing from C to GeC having two elements, the lattice constant of the buffer layer can be easily adjusted. Further, the manufacturing temperature of the buffer layer was lowered to 600 ° C. This allows Si
The Si of the substrate was made difficult to diffuse into the buffer layer. As a result, they have found that a high-quality crystalline SiC thin film can be obtained, and completed the present invention.

[0006]

The object of the present invention is to lower the crystallization temperature of Ge into cubic SiC, and to reduce the crystallization temperature during the formation of cubic SiC.
To provide a structure of a crystalline SiC thin film capable of obtaining a high quality crystalline SiC thin film by preventing Ge loss of the eC buffer layer and precisely controlling the composition of the buffer layer, and to provide a manufacturing method thereof. , Its purpose is.

[0007]

The invention according to claim 1
Is bonded to the surface of the Si substrate via the GeC buffer layer.
Crystalline SiC thin film structure with crystalline SiC thin film formed
is there. The type of Si substrate is not limited. Usually single crystal
It is a recon wafer. The size of the Si substrate is not limited
Yes. In addition, the thickness of the GeC buffer layer is not limited. Communication
It is usually 1 to 10 nm, preferably 5 nm. in this case,
The composition ratio of Ge and C is not limited. However, Ge
_1-y C _yAt y = 0.5 to 0.7, especially y =
0.63 is preferable. When y is less than 0.5, the buffer layer
There is some inconvenience that the lattice constant is too large. Well
Also, when y exceeds 0.7, the lattice constant of the buffer layer is small.
There is some inconvenience that it is too small. Thickness of SiC thin film
The size is not limited. Usually, it is 0.5 to 300 μm.
The above matters also apply to claim 4 and claim 6.
Method of forming GeC buffer layer and said cubic SiC thin film
The law is not limited. For example, in the conventional plasma CVD method
Alternatively, an inert gas sputtering method may be used.

The invention according to claim 2 is the structure of the crystalline SiC thin film according to claim 1, wherein the GeC buffer layer is made of Ge _0.37 C _0.63 .

The invention according to claim 3 is the structure of the crystalline SiC thin film according to claim 1 or 2, wherein the GeC buffer layer has a thickness of 1 to 10 nm.

The invention according to claim 4 comprises the step of forming a GeC buffer layer on the surface of the Si substrate by sputtering, and the step of forming a crystalline SiC thin film on the surface of the GeC buffer layer by sputtering. And a method of manufacturing a crystalline SiC thin film. The generation temperature of the GeC buffer layer is not limited as long as it is lower than 910 ° C. at which Ge evaporates. However, usually room temperature to 650 ° C., especially 600 to
625 ° C is preferred. The formation temperature of the crystalline SiC thin film is also
Similarly, it is not limited as long as it is less than 910 ° C. However, it is preferably less than 850 ° C, particularly preferably 800 to 850 ° C.
At the time of sputtering the GeC buffer layer and the crystalline SiC thin film, the gas supplied into the furnace of the sputtering apparatus may be hydrogen gas or various inert gases.

The fifth aspect of the present invention is the method for producing a crystalline SiC thin film according to the fourth aspect, wherein the sputtering is performed in hydrogen plasma.

According to a sixth aspect of the present invention, there is provided a semiconductor chip in which a crystalline SiC thin film for forming a device is laminated on the surface of a substrate made of single crystal silicon with a GeC buffer layer interposed therebetween. The type of semiconductor chip is not limited. For example, it can be used for IC and LSI. Usually crystalline S
Various devices are formed on the surface of the iC thin film.

[0013]

According to the inventions of claim 1, claim 4 and claim 6, since the GeC buffer layer is interposed at the hetero interface between the Si substrate and the crystalline SiC thin film, when the crystalline SiC thin film is manufactured, It is possible to relax the lattice mismatch between cubic SiC and Si and reduce the crystal defect density in cubic SiC. Specifically, Ge has atomic sizes of Si and C.
It is larger, the bond strength is smaller than Si and C, and the bond length is longer than Si and C. Therefore, G
With the introduction of e-coupling, flexibility can be expected in the buffer layer. As a result, the interface stress due to the difference in thermal expansion coefficient between the crystalline SiC thin film and the Si substrate is relaxed. In addition, if the GeC buffer layer is interposed between the Si substrate and the crystalline SiC thin film in this manner, the lattice mismatch between the Si substrate and the crystalline SiC thin film is reduced by controlling the composition of the buffer layer, A SiC thin film having high properties can be obtained.

In particular, in the method for producing a crystalline SiC thin film according to claim 4, the GeC ceramic plate is sputtered on the target in hydrogen plasma or plasma of an inert element, and S
A GeC buffer layer is formed on the surface of the i substrate. afterwards,
SiC in hydrogen plasma or plasma of inert elements
A ceramic plate is sputtered on a target to form a cubic SiC thin film on the surface of this GeC buffer layer. In the sputtering method, the thin film formation does not depend on the substrate temperature,
Since the crystallization temperature is lowered by using hydrogen plasma or plasma of an inert element, the formation temperature of cubic SiC is set to Ge.
Can be lower than the evaporation temperature of. This eliminates the loss of Ge during the production of cubic SiC, and as a result, a high-quality crystalline SiC thin film can be obtained.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. FIG. 1 shows a crystalline SiC according to an embodiment of the present invention.
FIG. 3 is an enlarged cross-sectional view of a main part of a semiconductor chip having a thin film structure. FIG. 2 is a vertical cross-sectional view of a semiconductor chip manufacturing apparatus having a crystalline SiC thin film structure according to an embodiment of the present invention. In FIG. 1, 10 is crystalline Si according to one embodiment.
This is a semiconductor chip adopting a C thin film structure (hereinafter referred to as a thin film structure), and this semiconductor chip 10 is a substrate (Si substrate).
A GeC buffer layer 12 having a predetermined thickness is formed on the surface of 14, and a thickness of about 1.0 μm is formed on the surface of the GeC buffer layer 12.
The crystalline SiC thin film 13 of m is formed. Hereinafter, the semiconductor chip 10 will be described in detail according to its manufacturing method.

First, referring to FIG. 2, a sputtering apparatus 20 for obtaining this semiconductor chip 10 will be described. The sputtering apparatus 20 has a cylindrical heating furnace 21 made of stainless steel. A turbo molecular pump 22 and a rotary pump 23 are connected to the exhaust pipe 21a of the heating furnace 21 in this order in the downstream direction. The inside of the heating furnace 21 can be depressurized to 7.5 × 10 ⁻⁴ Pa by the turbo molecular pump 22. Further, a microfiltration device 24 and an H ₂ gas cylinder 25 are connected to the gas introduction pipe 21b of the heating furnace 21 in order toward the downstream side. Hydrogen gas can be introduced into the heating furnace 21 from the H ₂ gas cylinder 25.

In this sputtering apparatus 20, the Si substrate 14 is placed on the upper side of the heating furnace 21, and the target is placed on the lower side of the heating furnace 21.
A disk-shaped target 26 made of graphite is vertically opposed to each other. A heater plate 27 is installed above the heating furnace 21 via an anode plate that anodizes the Si substrate 14 during film formation. The heater plate 27 is a support plate made of an insulating material of PBN in which a graphite resistor is inserted, and the entire body is heated by supplying electricity from a DC power supply 28 to the resistor. The Si substrate 14 is detachably attached to the lower surface of the heater plate 27 via a substrate holder (not shown). On the other hand, below the heating furnace 21, a plasma generator 30 is arranged by applying a high frequency from a high frequency power source 29 via a capacitor C. This plasma generator 3
The target 26 is held on the upper surface of 0. A Ge small piece or a Si small piece is placed on the target 26. The Ge pieces are used when forming the GeC buffer layer 12, and the Si pieces are used when forming the crystalline SiC thin film 13. Further, a quartz window 30 is provided on the upper side wall of the heating furnace 21.
Through the window 30, the radiation thermometer 32 is
The surface temperature of the substrate 14 can be measured.

Next, a crystal using this sputtering apparatus 20
A method of manufacturing the conductive SiC thin film 13 will be described. First, Si group
The GeC buffer layer 12 is formed on the surface (lower surface) of the plate 14.
It That is, a Ge small piece is placed on the graphite target 26.
The turbo molecular pump 22 and the rotary
Pump 23 and the inside of the heating furnace 21 7.5 × 10 ^-4
Decompress once to Pa. Then H_TwoGas cylinder 2
The hydrogen gas of No. 5 was filtered by the microfiltration device 24, and
It is introduced into the heating furnace 21 and the pressure inside the furnace is adjusted to 150 Pa.
To adjust. The flow rate of hydrogen gas here is 20 sccm (standard
Quasi-cubic centimeters / minute). Next, DC power supply 2
The heater plate 27 is heated by passing electricity of 8 to the resistor.
Then, the Si substrate 14 is heated to 600 ° C. This
Of the plasma generator with the substrate temperature of 600 ° C maintained.
Place high frequency power of 200W at 13.56MHz on the unit 30.
When added, a small piece of Ge on the Si substrate 11 and the target 26
Hydrogen plasma is generated between and. In the spatter action
From the surface of the Si substrate 14_0.37C_0.63But
To generate. Sputter at 600 ℃ for 5 minutes only
By continuing, the 5 nm GeC layer on the Si substrate 14
The buffer layer 12 is formed (see FIG. 1).

Next, a crystalline SiC thin film 13 is formed on the surface of the GeC buffer layer 12. That is, the internal gas of the heating furnace 21 is exhausted by the rotary pump 23, and the Si piece is placed on the target 26 instead of the Ge piece.
Then, the inside of the heating furnace 21 is 7.5 × 10 ⁻⁴ P in the same manner by the turbo molecular pump 22 and the rotary pump 23.
Decompress once to a. After that, H ₂ gas cylinder 25
Of hydrogen gas of the heating furnace 21
And the pressure inside the furnace is adjusted to 150 Pa. The flow rate of hydrogen gas is about 20 sccm. Next, the Si substrate 14 is heated to 850 ° C. through the energized heater plate 27. Then, 200 W of 13.56 MHz high frequency power is applied to the plasma generator 30 while maintaining the substrate temperature of 850 ° C. Thereby, the GeC buffer layer 1
Hydrogen plasma is generated between 2 and the Si piece on the target 26. Due to the sputtering action, crystalline SiC is generated on the surface of the GeC buffer layer 12. This 850 ℃
By continuing the sputtering in 4 hours for 4 hours, a crystalline SiC thin film 13 of about 1000 nm is formed on the GeC buffer layer 12 (see FIG. 1).

Thus, the Si substrate 14 and the crystalline SiC
Since the GeC buffer layer 12 is provided at the hetero interface between the thin film 13 and the thin film 13, when the thin film growth temperature (850 ° C.) is returned to room temperature, the difference in thermal expansion coefficient between the SiC thin film 13 and the Si substrate 14 (8%) is caused. The interface stress is absorbed by the weak bond of Ge. Further, by adjusting the composition of the buffer layer 12, the lattice constant of the buffer layer 12 becomes S from the lattice constant of the Si substrate 14.
The lattice constant of the iC thin film 13 is changed, and the lattice mismatch (20
%) To reduce the density of crystal defects in crystalline SiC. Moreover, by adopting the hydrogen plasma sputtering method, the crystallization temperature of the SiC thin film 13 is lowered, and the evaporation loss of Ge in the GeC buffer layer 12 during the growth of the SiC thin film can be avoided. Further, by changing the composition of the buffer layer 12 to GeC of two elements, the composition can be easily changed and the lattice constant of the buffer layer 12 can be controlled. The low temperature growth (600 ° C.) of the buffer layer 12 limits Si diffused from the substrate into the buffer layer 12, and the composition of the buffer layer 12 can be easily controlled. Due to these, a high-quality cubic SiC thin film 13 is obtained. After that, the Si substrate 14 carried out from the heating furnace 21 is
A device is formed on the C thin film 13 and cut into a large number of semiconductor chips 10 by a dicing device.

With respect to the semiconductor chip 10 of the above-mentioned one embodiment obtained in this way, respective analysis results will be reported. FIG. 3 is a graph showing X-ray diffraction patterns of the crystalline SiC thin film of the conventional example and the test example. FIG. 4 is a graph showing the relationship between the growth time of the GeC buffer layer and the X-ray diffraction intensity of the crystalline SiC thin film. FIG. 5 is a graph showing the relationship between the growth time of the GeC buffer layer and the relative decrease in the (111) crystal plane spacing. FIG. 6 is a graph showing the relationship between the growth time of the GeC buffer layer and the half-width of the rocking curve.
FIG. 7 is a reference photograph of a crystalline SiC thin film of a conventional example by a transmission electron microscope. FIG. 8 shows the crystalline SiC of the test example.
It is a reference photograph of a thin film by a transmission electron microscope.

At this time, GeC on the surface of the Si substrate 11
The generation time of the buffer layer is 0 minutes (comparative example) and 1 minute to 7 minutes (test example). Other conditions are the same as those in the above-mentioned one embodiment. In the comparative example (FIG. 7) in which the GeC buffer layer was not formed, an amorphous layer of about 3 nm was observed at the interface between the SiC thin film and the Si substrate, and strain of the SiC crystal lattice was also observed. On the other hand, in the test example, when the GeC buffer layer has a thickness of 5 nm (FIG. 8), a GeC buffer layer having a thickness of 5 nm is confirmed at the interface between the SiC thin film and the Si substrate. This S
Crystal layers are observed near the iC thin film / buffer layer interface and the buffer layer / Si substrate interface. An amorphous layer exists in the region of the GeC buffer layer. The structure of this buffer layer suggests that the interfacial stress between crystalline SiC and the Si substrate is open to the amorphous layer. Further, no strain is observed in the SiC layer in the SiC thin film. Therefore, both the morphology and crystallinity of the crystalline SiC thin film were improved. From the X-ray diffraction pattern shown in FIG. 3, the SiC crystal is (1
11), the crystallinity was greatly improved.

Further, from the graph of FIG. 4, it was found that the X-ray diffraction intensity of the crystalline SiC thin film was the largest when the GeC buffer layer was 5 nm. Furthermore, it can be seen from the graph of FIG. 5 that the SiC crystal is compressed in the growth direction due to stress. GeC buffer layer 3-5
In the case of nm, the stress decreases, and the decrease of the lattice constant is 0.
It was improved to 12 to 0.14%. Then, as shown in the graph of FIG. 6, when the thickness of the GeC buffer layer is 5 nm, the half-width of the rocking curve of the crystalline SiC thin film is 4.
It was a minimum of 1 degree. The crystallinity of the growth surface was evaluated by a TEM (transmission electron microscope) device. Crystalline SiC
The thickness of the thin film and the surface morphology were observed with a scanning electron microscope. As described above, a GeC buffer layer made of Ge _0.37 C _0.63 having a thickness of 5 nm formed on a Si substrate is a crystal of high-purity cubic (111) SiC on the surface of the GeC buffer layer. A thin SiC film could be formed. On the other hand, in the conventional example in which the crystalline SiC thin film was directly formed on the Si substrate, crystal defects frequently occurred in cubic SiC, resulting in low-purity cubic SiC.

[0024]

According to the present invention, the Si substrate and the crystalline S
Since the GeC buffer layer is interposed at the hetero interface with the iC thin film, the lattice mismatch between cubic SiC and Si is relaxed during the production of the crystalline SiC thin film, and the crystal defect density in the cubic SiC is reduced. be able to. As a result, a SiC thin film having high crystallinity can be obtained.

In particular, in the method for producing a crystalline SiC thin film according to claim 4, since the crystalline SiC thin film is formed on the surface of the Si substrate through the GeC buffer layer by sputtering, the lattice constant of the GeC buffer layer is increased. Can be controlled by the composition of the two elements. That is, the control is easier than in the case of the conventional three elements (SiGeC buffer layer). Moreover, by adopting the sputtering method, the formation temperature of the crystalline SiC thin film is lowered, and the loss of Ge in the buffer layer during the formation of the thin film can be avoided. as a result,
A higher quality crystalline SiC thin film can be obtained.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a main part of a semiconductor chip having a crystalline SiC thin film structure according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view of a semiconductor chip manufacturing apparatus having a structure of a crystalline SiC thin film according to an embodiment of the present invention.

FIG. 3 is a graph showing X-ray diffraction patterns of crystalline SiC thin films of a conventional example and a test example.

FIG. 4 is a graph showing the relationship between the growth time of a GeC buffer layer and the X-ray diffraction intensity of a crystalline SiC thin film.

FIG. 5 is a graph showing the relationship between the growth time of a GeC buffer layer and the relative decrease in (111) crystal face spacing.

FIG. 6 is a graph showing the relationship between the growth time of a GeC buffer layer and the half-width of a rocking curve.

FIG. 7 is a reference photograph by a transmission electron microscope of a crystalline SiC thin film of a conventional example.

FIG. 8 is a transmission electron microscope reference photograph of the crystalline SiC thin film of the test example.

[Explanation of symbols]

10 semiconductor chips, 11 bases, 14 Si substrate, 12 GeC buffer layer, 13 Crystalline SiC thin film.

Claims (6)

[Claims] 1. A structure of a crystalline SiC thin film in which a crystalline SiC thin film is formed on the surface of a Si substrate via a GeC buffer layer. 2. The GeC buffer layer is Ge _0.37 C
The structure of the crystalline SiC thin film according to claim 1, which is composed of _0.63 . 3. The GeC buffer layer has a thickness of 1-10.
The crystalline Si according to claim 1 or 2, wherein the crystalline Si
Structure of C thin film. 4. Production of a crystalline SiC thin film, comprising a step of forming a GeC buffer layer on the surface of a Si substrate by sputtering, and a step of forming a crystalline SiC thin film on the surface of the GeC buffer layer by sputtering. Method. 5. The method for producing a crystalline SiC thin film according to claim 4, wherein each of the sputtering is performed in hydrogen plasma. 6. A surface of a substrate made of single crystal silicon,
Crystalline S for device formation through the GeC buffer layer
A semiconductor chip in which an iC thin film is laminated.