JP2003023103A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for stably manufacturing a memory cell capacitor having roughened polysilicon electrode having sufficient strength and a superior electric characteristic. SOLUTION: A silicon oxidized film 102 and a doped polysilicon film 103 are deposited on a silicon substrate 101. The doped polysilicon film 103 is immersed in diluted hydrofluoric acid and hydrogen peroxide water and a silicon oxidized film 104 is formed on a surface. An amorphous silicon film 105 is deposited on the silicon oxidized film 104. Then, a roughened polysilicon film 106 is formed on the surface of the amorphous silicon film 105. The roughened polysilicon film 106 is heat-treated in a phosphine gas atmosphere being phosphorus hydroxide obtained by diluting the roughened polysilicon film 106 by hydrogen gas. Phosphorus is doped by heat diffusion. Then, the memory capacitor including above processes is manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory cell capacitor of DRAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art In recent years, DRAM devices have been required to realize a large capacitance value with a small memory cell occupation area in order to achieve high integration and large capacity. Therefore, as disclosed in JP-A-5-110023 and JP-A-5-175456, as a method of increasing the capacitance value,
Attempts have been made to increase the capacitance value by roughening the surface of the polysilicon lower electrode to increase the surface area.

A conventional method of manufacturing a memory cell capacitor will be described below with reference to FIG.

First, as shown in FIG. 2A, a silicon substrate 201 is oxidized at 950 ° C. in wet oxygen to form a silicon oxide film 202 having a thickness of 100 nm, and SiH ₄ gas is used thereon. A doped polysilicon film 203 having a gap of 100 nm is deposited by a low pressure CVD method.

After that, the doped polysilicon film 203,
Once the silicon oxide film 202 and the silicon substrate 201 are
It is taken out of the VD chamber and a natural oxide film 204 having a thickness of several Å is formed on the surface of the doped polysilicon film 203. Then, the film is again introduced into the CVD chamber, and an amorphous silicon film 205 is deposited to 100 nm on the doped polysilicon film 203 with the natural oxide film 204 interposed therebetween.

Next, as shown in FIG. 2B, the amorphous silicon film 205 is annealed in a vacuum atmosphere to cause migration from the surface, so that the roughened polysilicon film 2 is formed.
06 is formed. At this time, since the migration stops at the natural oxide film 204 on the surface of the doped polysilicon film 203, it does not reach the doped polysilicon film 203.
Then, As is ion-implanted into the roughened polysilicon film 206 to obtain electrical conduction, and the natural oxide film 204 on the surface of the doped polysilicon film 203 is destroyed by ion implantation.

Finally, as shown in FIG. 2C, a silicon nitride film 208 as a capacitor insulating film and a doped polysilicon film 209 as an upper electrode are deposited to form a capacitor structure.

[0008]

However, in this conventional method, the film thickness and film quality of the natural oxide film 204 formed at the interface are stable because they depend on the conditions of exposing the doped polysilicon film 203 to the atmosphere. However, it has been difficult to obtain the same characteristics.

For example, when the time of exposure to the atmosphere is short, or when the atmosphere in the atmosphere is low temperature and low humidity, the film thickness of the natural oxide film 204 formed is very thin and the amorphous silicon film for roughening the surface. 205 is a roughened polysilicon film 206 which is affected by the crystal orientation of the lower doped polysilicon film 203 and has a low degree of roughening. That is, it is not possible to obtain a sufficiently roughened surface shape without re-diffusion of silicon atoms.

On the contrary, when the exposure time to the atmosphere is long, or when the atmosphere during the exposure to the atmosphere is high temperature and high humidity, the film thickness of the natural oxide film formed becomes thick. At this time, the uppermost amorphous silicon film 205 is roughened, but since a thick silicon oxide film is formed at the interface, the roughened polysilicon film 206 is lifted off by hydrofluoric acid cleaning in a later step. It peels off.

On the other hand, using the CVD chamber used for depositing the doped polysilicon film 203, dry oxygen is introduced into the same chamber after depositing the doped polysilicon film 203 to form the natural oxide film 204. Then
The film thickness of the natural oxide film 204 increases from 1.5 nm to 4 nm.

Therefore, peeling of the roughened polysilicon film 206 due to lift-off becomes a problem. Further, the ion implantation technique is applied when removing the natural oxide film 204 formed on the interface, but the dopant is uniformly introduced into the roughened polysilicon film 206 having variations in size and shape. Is difficult. Furthermore, the natural oxide film 20
Since the 4th film is thick, the natural oxide film 204 cannot be removed sufficiently, and in addition to the problem of peeling due to lift-off, there is a problem in electrical characteristics that a resistance component is added to the capacitance capacitance.

Therefore, an object of the present invention is to solve the above problems, and to provide a method capable of stably producing a roughened polysilicon electrode having sufficient strength and excellent electrical characteristics. Is.

[0014]

A method for manufacturing a semiconductor device according to the present invention comprises a step of depositing a doped polysilicon film on a semiconductor substrate to form a lower electrode, and a step of forming a silicon film on the surface of the doped polysilicon film. A step of forming an oxide film by a wet process, a step of depositing an amorphous silicon film on the silicon oxide film, a step of modifying the amorphous silicon film into a roughened polysilicon film having irregularities on the surface, and a roughening And a step of doping the polysilicon film and the silicon oxide film with an N-type impurity and simultaneously reducing and removing the silicon oxide film.

According to the present invention, when the silicon oxide film is formed on the doped polysilicon electrode, the polysilicon electrode is not exposed to the atmosphere.

In the method of manufacturing a semiconductor device of the present invention, the silicon oxide film has a thickness of 0.3 nm or more and 1.4 or more.
More preferably, it is not more than nm.

In the method for manufacturing a semiconductor device of the present invention, it is more preferable that the step of forming the silicon oxide film by the wet treatment is to immerse the doped polysilicon film in hydrogen peroxide.

In the method of manufacturing a semiconductor device according to the present invention, the step of forming the silicon oxide film by the wet treatment may be performed by dipping the doped polysilicon film in diluted hydrofluoric acid and then in hydrogen peroxide. preferable.

In the method of manufacturing a semiconductor device according to the present invention, the doped polysilicon film contains 1E20 N-type impurities.
It is more preferable to introduce (1 / cm ³ ) or more.

In the method of manufacturing a semiconductor device of the present invention, it is more preferable that the N-type impurity introduced into the doped polysilicon film is phosphorus.

In the method of manufacturing a semiconductor device of the present invention, the step of doping the roughened polysilicon film and the silicon oxide film with an N-type impurity may be performed by heat treatment in a mixed atmosphere of phosphorus hydride and hydrogen. preferable.

In the semiconductor device manufacturing method of the present invention, the heat treatment in the mixed atmosphere of phosphorus hydride and hydrogen is more preferably performed in a phosphorus hydroxide atmosphere in which hydrogen gas is diluted with 1%.

In the method of manufacturing a semiconductor device of the present invention, the step of doping the roughened polysilicon film and the silicon oxide film with N-type impurities has an impurity concentration of 3E20.
It is more preferably (1 / cm ³ ) or more.

In the method for manufacturing a semiconductor device of the present invention, it is more preferable that the N-type impurity introduced into the roughened polysilicon film and the silicon oxide film is phosphorus.

[0025]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1A, the silicon substrate 101 is annealed at 1000 ° C. in an oxygen atmosphere containing water vapor to form a silicon oxide film 102.
The film thickness of the silicon oxide film 102 is, for example, 100 nm.

Subsequently, a reduced pressure C is formed on the silicon oxide film 102.
A doped polysilicon film 103 is deposited by using the VD method. The thickness of the doped polysilicon film 103 is 50 nm
The deposition conditions are as follows: silane (SiH ₄ ) gas and phosphine (PH ₃ ) gas are used as source gases, and the deposition temperature is 500.
℃ or above. Further, the concentration of phosphorus, which is an N-type impurity, needs to be 1E20 (1 / cm ³ ) or more in order to obtain conductivity. When the phosphorus concentration is lower than this, the electrode is depleted during the operation of the capacitor, and a problem arises in that a sufficient capacitance cannot be obtained. At this time, the doped polysilicon film 103
A natural oxide film including a silicon oxide film is formed on the surface of the.

Subsequently, heat treatment is performed at 800 ° C. for 30 minutes in a nitrogen atmosphere to completely crystallize the doped polysilicon film 103. Crystallization densifies the film and makes it resistant to hydrofluoric acid attack. When the deposition temperature of the doped polysilicon film 103 is 550 ° C. or higher, this heat treatment is unnecessary because it has already been crystallized.

Next, as shown in FIG. 1B, the doped polysilicon film 103 is diluted with hydrofluoric acid (HF: H ₂ O =).
1: 300) to completely etch away the silicon oxide film including the natural oxide film on the surface, and continuously immerse in the hydrogen peroxide solution to form the silicon oxide film 104 again on the surface.

The concentration of hydrogen peroxide water is 1:40, and the liquid temperature is 7
It is 0 ° C. The thickness of the silicon oxide film is 0.3 nm or more and 1.4 nm or less. When the film thickness of the silicon oxide film 104 is less than 0.3 nm, the silicon film deposited on the silicon oxide film 104 is the doped polysilicon film 103.
The surface roughness of silicon cannot be obtained because it is crystallized under the influence of the crystallinity and the surface diffusion of silicon becomes impossible.
On the other hand, when the film thickness of the silicon oxide film 104 is 1.5 nm or more, the film thickness is too large and problems such as lift-off due to hydrofluoric acid cleaning and electrical characteristics occur.

By this step, which is a feature of the present invention, the film thickness of the silicon oxide film 104 can be formed with good control. Therefore, the silicon oxide film 104 is exposed to the atmosphere.
Reproducibility is better than that in the case of forming.

Furthermore, wet oxidation is more likely to form a thin silicon oxide film 104 than formation by dry oxygen. Further, since wet oxidation is formed at a temperature close to room temperature, there is also an advantage that element deterioration due to thermal history is less than in a dry oxidation method which requires high temperature treatment.

Subsequently, a reduced pressure C is formed on the silicon oxide film 104.
The amorphous silicon film 105 is deposited by using the VD method. The film thickness of the amorphous silicon film 105 is 30 n
m, the deposition condition is that silane (SiH ₄ ) gas is used as the source gas, and the deposition temperature is 510 ° C. or lower. Since the concentration of phosphorus becomes an inhibitory factor when the surface of phosphorus is roughened,
It must be E20 (1 / cm ³ ) or less.

Next, as shown in FIG. 1C, the amorphous silicon film 105 is annealed in an ultrahigh vacuum of 1E-8 (Toor) or less, and at the same time, silane (SiH ₄ ) gas is supplied to the surface. Form a nucleus. Then, the silicon nuclei play a central role and the silicon in the amorphous silicon film 105 is surface-diffused and aggregated, and the roughened polysilicon film 1
06 is formed.

At this time, the silicon atoms contributing to aggregation are
It is limited to the silicon in the amorphous silicon film 105, and the silicon in the lower doped polysilicon film 103 and the silicon oxide film 104 are not crystallized or oxidized, but do not diffuse on the surface. As a result, the strength of the lower layer of the lower electrode is maintained.

Subsequently, the surface-roughened polysilicon film 106 is heat-treated in a phosphine (PH ₃ ) gas atmosphere, which is phosphorus hydroxide diluted to 1% with hydrogen gas, to form silicon grains on the surface of the surface-roughened polysilicon film 106. Phosphorus serving as a dopant is doped inside by thermal diffusion. The phosphorus concentration may be 3E20 (1 / cm ³ ) or more. The temperature of the heat treatment is 700 (° C.) and the pressure is 300 (Torr).

Hydrogen diluting gas used at this time and hydrogen radicals generated by decomposition of phosphine reduce the lower silicon oxide film 104 to form silicon, and the doped polysilicon film 103 and the roughened polysilicon film 106. Physically and electrically bond with the surface.

By this step which is the feature of the present invention,
Compared with destruction and removal by ion implantation, less damage is given to the roughened polysilicon film 106, and strong strength can be maintained. Furthermore, since the silicon oxide film can be removed uniformly,
It has the feature that it is easy to obtain uniform electrical characteristics. From the viewpoints of reproducibility and large-scale processing, phosphine annealing is lower in cost and superior in mass productivity than ion implantation.

Next, as shown in FIG. 1D, the lower electrode portion is patterned by using photolithography and dry etching techniques to be processed into a capacitor lower electrode.

Finally, as shown in FIG.
A low pressure CVD method using a silicon nitride film as the insulating film 107.
At dichlorosilane (SiH₂Cl₂) And ammonia
(NH ₃) Is used to deposit. Film thickness is 5 nm, deposition temperature
Is 700 ° C.

Further, the silicon nitride film 107 is heat-treated in an oxygen atmosphere to form a laminated film of a silicon nitride film and a silicon oxide film. The annealing temperature is 800 ° C. Next, as an upper electrode, a doped polysilicon film 108 is deposited at a deposition temperature of 540 ° C. by a low pressure CVD method using SiH ₄ gas. The film thickness is 200 nm.

Then, as shown in FIG.
Heat treatment is performed at 10 ° C. for 10 seconds to activate phosphorus, patterning is performed using a conventional technique, and a capacitor upper electrode is processed. Although the present embodiment shows an example of dry etching the lower electrode, it goes without saying that the capacitor structure is formed without dry etching.

[0043]

As described above, according to the present invention, the silicon oxide film is formed on the surface of the first doped silicon film by immersing it in the hydrogen peroxide solution. Therefore, the reproducibility is better than that in the case where the silicon oxide film is formed by exposure to the air. Furthermore, wet oxidation is easier to form a thin silicon oxide film than dry oxygen. Further, since wet oxidation is formed at a temperature close to room temperature, there is also an advantage that element deterioration due to thermal history is less than in a dry oxidation method which requires high temperature treatment.

Further, since the formed silicon oxide film is reduced and removed by the phosphine gas containing hydrogen, compared to the destructive removal by ion implantation, the roughened grains are less damaged and a strong strength can be maintained. Further, since the silicon oxide film can be uniformly removed, it has a feature that it is easy to obtain electrically uniform characteristics.

[Brief description of drawings]

FIG. 1 is a process sectional view in an embodiment of a semiconductor device of the present invention.

2A to 2C are process cross-sectional views in an embodiment of a conventional semiconductor device.

[Explanation of symbols]

101 Silicon substrate 102 Silicon oxide film 103 doped polysilicon film 104 Silicon oxide film 105 amorphous silicon film 106 roughened polysilicon film 107 Capacitor insulating film 108 doped polysilicon film 201 Silicon substrate 202 Silicon oxide film 203 doped polysilicon film 204 Natural oxide film 205 amorphous silicon film 206 roughened polysilicon film 207 Lower electrode 208 Silicon nitride film 209 Doped polysilicon film

Claims (10)

[Claims] 1. A step of depositing a doped polysilicon film on a semiconductor substrate to form a lower electrode, a step of forming a silicon oxide film on the surface of the doped polysilicon film by a wet treatment, and a step of forming the silicon oxide film. A step of depositing an amorphous silicon film on the film, a step of modifying the amorphous silicon film into a roughened polysilicon film having irregularities on the surface, and an N-type conversion of the roughened polysilicon film and the silicon oxide film. A method of manufacturing a semiconductor device, comprising the steps of doping impurities and simultaneously reducing and removing the silicon oxide film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an oxide film thickness of the silicon oxide film is 0.3 nm or more and 1.4 nm or less. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the silicon oxide film by a wet process is performed by immersing the doped polysilicon film in hydrogen peroxide. Of manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the silicon oxide film by a wet process is performed by immersing the doped polysilicon film in diluted hydrofluoric acid, A method of manufacturing a semiconductor device, which comprises immersing water in hydrogen peroxide. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the doped polysilicon film contains 1E20 N-type impurities.
A method of manufacturing a semiconductor device, wherein (1 / cm ³ ) or more is introduced. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the N-type impurity is phosphorus. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of doping the roughened polysilicon film and the silicon oxide film with an N-type impurity is performed in a mixed atmosphere of phosphorus hydride and hydrogen. A method of manufacturing a semiconductor device, which comprises heat treatment. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the heat treatment in the mixed atmosphere of phosphorus hydride and hydrogen is performed in a phosphorus hydroxide atmosphere in which hydrogen gas is diluted with 1%. A method of manufacturing a semiconductor device, comprising: 9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of doping the roughened polysilicon film and the silicon oxide film with an N-type impurity has an impurity concentration of 3E20.
(1 / cm ³ ) or more, A method for manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the N-type impurity is phosphorus.