JP2003023086A - Semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase in signal propagation delay due to the influence of crosstalks without increasing the area of a wiring region in a semiconductor circuit. SOLUTION: In a drive circuit 120 for driving an output signal line 150, a first potential combination on a high potential side which is the combination of a first high potential (Vdd) and a first low potential (Vdd/2+a) and a second potential combination on a low potential side which is the combination of a second high potential (Vdd/2-a) and a second low potential (0 v) are forcibly switched at every potential change of clock signals by an output potential switching circuit 160. The first low potential (Vdd/2+2) is set to a potential which is equal to or higher than the second high potential (Vdd/2-a). Thus, since the potential change of two adjacent signal lines are prevented from being related in opposite phases, an increase in signal propagation delay due to the influence of the crosstalks is prevented without increasing wiring or increasing the area of the wiring region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit,
More specifically, the present invention relates to preventing a signal propagation speed from decreasing due to crosstalk between adjacent signal wirings.

[0002]

2. Description of the Related Art In recent years, as the scale of semiconductor integrated circuits has increased, the wiring density has increased and the capacitance between wirings has increased, so that crosstalk between adjacent signal lines cannot be ignored. The signal propagation delay of the signal line increases or decreases due to the influence of crosstalk as compared with the case where there is no crosstalk. That is, the signal propagation delay decreases when the signals of the adjacent signal lines change in the same phase, and increases when the signals change in the opposite phase. The maximum operating speed of a semiconductor circuit is constrained by the speed when the signal on the signal line of the critical path changes in anti-phase due to the effect of crosstalk, so crosstalk is one of the obstacles to speeding up semiconductor circuits. It has become. Therefore, it has been a problem to suppress an increase in signal propagation delay due to crosstalk.

As one of the solutions to the above problems, it has been conventionally proposed to adopt a configuration in which a control wiring fixed to a predetermined potential such as a power supply wiring is arranged between adjacent signal wirings. In this configuration, the signal changes of the adjacent signal lines are neither in-phase nor in anti-phase and have a fixed potential, so that an increase in signal propagation delay due to crosstalk can be suppressed. Further, in the technique disclosed in Japanese Patent Application Laid-Open No. 5-82646, a control wiring is arranged between adjacent signal wirings in parallel with the signal wiring, and the control wiring has a potential equal to that of the signal line. The driving configuration is adopted. In this configuration, the potential of the adjacent wiring always changes in the same phase as the potential of the signal line, so that an increase in signal propagation delay due to crosstalk can be suppressed.

[0004]

However, in the above-mentioned conventional configuration, although it is possible to suppress an increase in signal propagation delay due to crosstalk, in each case, one or two control lines are provided for each signal line. Wiring is required,
The wiring area of the signal line to which the above configuration is applied is twice or three times as large.
Double. Therefore, in a chip having a large wiring area, if the above-described conventional configuration is applied to a multi-bit bus or long wiring in the chip, there arises a problem that the rate of increase in the chip area becomes large.

The present invention solves the above-mentioned problems, and it is an object of the present invention to suppress an increase in signal propagation delay due to the influence of crosstalk without the need for arranging a control wiring for a signal line. It is to provide a semiconductor circuit capable of

[0006]

In order to solve the above problems, according to the present invention, two signals on two adjacent and parallel signal lines are forcibly forced from high potential to low potential every cycle. Or in the same phase from low potential to high potential.

Specifically, a semiconductor circuit according to a first aspect of the present invention receives a binary input signal and is connected to an output signal line, and has a first high potential corresponding to a potential of the input signal. And one of the first potential combinations of the first low potential lower than the first high potential and the second high potential and the second low potential lower than the second high potential. Drive means for outputting to the output signal line any one of a second potential combination with a potential, and the first potential combination and the second potential combination of the drive means are alternated for each cycle. And a first low potential of the first potential combination is set to a potential equal to or higher than a second high potential of the second potential combination.

According to a second aspect of the present invention, in the semiconductor circuit according to the first aspect, the first low potential of the first potential combination and the second high potential of the second potential combination are different from each other. It is characterized in that they are set to the same potential.

Further, the invention according to claim 3 is the semiconductor circuit according to claim 1 or 2, wherein the input signal is connected to the output signal line, and the signal of the output signal line is used as an input signal. It is characterized in that it is provided with a receiver means for outputting a signal that changes to a corresponding binary value.

In addition, the invention according to claim 4 is the semiconductor circuit according to claim 1 or 2, in which another output signal line extending in parallel adjacent to the output signal line is provided. Another drive means having the same structure as the drive means and connected to the other output signal line is provided, and the first potential combination and the second potential combination of the other drive means are the output potential switching. It is characterized in that it is alternately switched every cycle by means.

As described above, in the semiconductor circuit according to the first aspect of the invention, the two signals on the two adjacent and parallel signals extend from the high potential to the low potential, and the low potential changes. To a high potential and maintaining the potential, in one cycle, for example, when the first high potential or the first low potential of the first potential combination on the high potential side is present, in the next cycle, The second high potential or the second low potential among the second potential combinations forcibly on the low potential side (first high potential> first low potential ≧ second high potential> second low potential) In the next cycle, the first potential combination on the high potential side is forcibly changed to the first high potential or the first low potential. Therefore, since the signals of the adjacent signal lines do not have an opposite phase relationship, the signal propagation delay does not increase due to the influence of crosstalk, and the control signal line is different from the conventional one for each signal line. Since it is not necessary to arrange the wirings, the wiring area is not increased, and the increase of the chip area is suppressed.

Particularly, in the invention according to claim 2, the first
Since the low potential and the second high potential are set to the same potential, the amplitude of the output potential of the drive means is minimized, and the power consumption can be suppressed small.

According to the third aspect of the invention, it is possible to configure a transmitting / receiving circuit in which an increase in signal propagation delay due to crosstalk is suppressed.

[0014]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor circuit according to an embodiment of the present invention will be described below with reference to FIGS.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows a semiconductor circuit of the embodiment. In FIG. 1, 15
0 is an output signal line, 100 is a first block A having a drive circuit (drive means) 120 connected to the output signal line 150 and driving the output signal line 150.
00 is a second block B similarly having a drive circuit (drive means) 120 connected to the output signal line 150 and driving the output signal line 150. The first
The drive circuits 120 included in the block A and the second block B have the same configuration. Hereinafter, the internal configuration of the drive circuit 120 in the first block A will be described as an example.

A signal 140 is input to the drive circuit 120. As shown in FIG. 3B, the input signal 140 is a binary signal that changes between the potential Vdd and 0 (v), for example. In the drive circuit 120, the power supply terminal 107 having the first high potential Vdd, the power supply terminal 117 having the first low potential (Vdd / 2 + a), and the second high potential (Vdd / 2-a). A power supply terminal 118 having
A power supply terminal 108 having a second low potential 0 (v). The first high potential Vdd and the first low potential (Vdd /
2 + a) to form a first potential combination,
The high potential (Vdd / 2-a) and the second low potential 0 (v) form a second potential combination. The first low potential (Vdd / 2 + a) is the second high potential (Vdd / 2−2).
The potential is set to a) or higher.

In the drive circuit 120,
Reference numeral 101 is a PMOS transistor, and 102 is an NMOS transistor, both drains of which are commonly connected. The source of the PMOS transistor 101 is connected to the first high potential terminal 107, and the NMOS transistor 102
Is connected to the second low potential terminal 108. 10
Reference numeral 3 is a PMOS transistor, and 104 is an NMOS transistor, the drain and the source of which are commonly connected, the source thereof is connected to the drains of the PMOS transistor 101 and the NMOS transistor 102, and the drain thereof is an output signal line. Connected to 150.

In the drive circuit 120, 10
5 is an OR circuit, 106 is an inverter,
The input signal 140 to the drive circuit 120 of the first block A and the inverted signal of the output enable signal 130 of the drive circuit 120 of the first block A are input to the input of the circuit 105. The output of the OR circuit 105 is PMO.
It is input to the gate of the S transistor 103, and its inverted output is input to the gate of the NMOS transistor 104.

Further, in the drive circuit 120, 11
Reference numeral 1 is a PMOS transistor, and 112 is an NMOS transistor, both drains of which are commonly connected. P
The source of the MOS transistor 111 is connected to the first low potential terminal 117, and the source of the NMOS transistor 112 is connected to the second high potential terminal 118. 113 is P
The MOS transistor 114 is an NMOS transistor, the drain and the source of which are commonly connected, and the sources thereof are the PMOS transistors 111 and NM.
The drain of the OS transistor 112 is connected to the output signal line 150. 1
Reference numeral 15 is a NAND circuit, and 116 is an inverter. The input of the NAND circuit 115 is an input signal 140 to the drive circuit 120 of the first block A and an output enable signal of the drive circuit 120 of the first block A. Thirteen
0 is input. The output of the NAND circuit 115 is
It is input to the gate of the PMOS transistor 113, and its inverted output is input to the gate of the NMOS transistor 114.

The drive circuit 120 in the second block B
, 240 is a binary input signal and 230 is an output enable signal. Second block B drive circuit 1
The output signal of 20 is output to the output signal line 150 as in the first block A.

In FIG. 1, 160 is an output potential switching circuit (output potential switching means). In the output potential switching circuit 160, 162 is an OR circuit,
The output enable signal 130 of the block A and the output enable signal 230 of the second block B are input. 1
An AND circuit 61 receives the output of the OR circuit 162 and the clock signal 163. An inverted output flip-flop 164 receives the output of the AND circuit 161 at its control terminal and returns its output to the input side. Therefore, one of the output enable signals 130 and 230 of the first and second blocks A and B has a high potential (Vdd).
In this case, the inverting output flip-flop 164 inverts each time the potential of the clock signal 163 changes.

The output of the inverting output flip-flop 164 of the output potential switching circuit 160 is the PMOS transistors 101 and 111 and the NMOS transistor 10 of the drive circuits 120 of the first and second blocks A and B.
It is input to the gate of 2,112. Therefore, in the first and second blocks A and B, every time the potential of the clock signal 163 changes (every cycle), the first high potential Vdd and the first low potential (Vdd / 2 + a) 1 potential combination, second high potential (Vdd / 2-a) and second low potential 0
The second potential combination with (v) is selected alternately.

In each drive circuit 120 of the first and second blocks A and B, the output enable signals 130 and 2 are output.
When the output potential switching circuit 160 selects the first potential combination when 30 is at the high potential (vdd), the input signals 140 and 240 are at the low potential (0 (v)).
If so, the first high potential Vdd is selected and the output signal line 1
50, and the input signals 140 and 240 are at high potential (V
If it is dd), the first low potential (Vdd / 2 + a) is selected and output to the output signal line 150. On the other hand, when the second potential combination is selected by the output potential switching circuit 160, the input signals 140 and 240 are low potential (0.
If (v)), the second low potential (0 (v)) is selected and output to the output signal line 150. If the input signals 140 and 240 are high potential (Vdd), the second high potential (0) is selected. Vdd / 2-
A) is selected and output to the output signal line 150.

FIG. 2 shows an example in which the first block A and the second block B both have two sets of drive circuits 120, and the outputs thereof are output to two output signal lines 150 and 151, respectively. . The other drive circuit (other drive means) 120 in the first and second blocks A and B has the same configuration as the drive circuit 120 of FIG.

In FIG. 2, 130 is the first block A.
Output enable signal, 140 is an input signal to the drive circuit 120 of the first block A connected to the output signal line 150, and 141 is a drive circuit 120 of the first block A connected to the output signal line 151. Input signal, 230
Is an output enable signal of the block B, 240 is an input signal to the drive circuit 120 of the second block B connected to the output signal line 150, and 241 is a drive circuit of the second block B connected to the output signal line 151. This is an input signal to 120. Output signal line 150 and other output signal line 151
Are adjacent to each other and extend in parallel as in a bus line, for example, crosstalk occurs when the drive circuit 120 has a normal buffer configuration, and a signal propagation delay occurs when the output signal has an opposite phase. It is arranged to increase.

Next, in the semiconductor circuit shown in FIG.
The operation will be described with reference to FIGS. Figure 3 is the first
The signals are output only from the block A of the output signal lines 150 and 151.
4 is output to the first block A in the middle.
When the signal output is switched from the second block B to the second block B, FIG. 5 shows an example in which the signal is not output from the first block A or the second block B in the middle.

In FIG. 3, signals are output to the output signal lines 150 and 151 from only the first block A. The output waveform of the output potential cutoff circuit 160 is shown in FIG. 9A, the input signals 140 and 141 of the first block A are shown in FIG. c),
Drive circuit 120 in the first and second blocks A and B
Output enable signals 130 and 230 of FIG.
The signals of the output signal lines 150 and 151 are shown in FIG.
When the output of the output potential switching circuit 160 is at a low potential (0 (v)) and the input signals 140 and 141 are at the high potential Vdd, the output signal lines 150 and 151 are at the first low potential (Vdd / 2 +).
a), the input signals 140 and 141 are low potential (0
In the case of (v), the output signal lines 150 and 151 have the first high potential Vdd. On the contrary, when the output of the output potential switching circuit 160 is the high potential Vdd, if the input signals 140 and 141 are the high potential Vdd, the output signal lines 150 and 151 become the second high potential (Vdd / 2-a), Input signal 140, 141
Is a low potential (0 (v)), the output signal lines 150 and 151
Becomes the second low potential (0 (v)). Output potential switching circuit 1
Output enable signals 130 and 23 which are input signals of 60
Since the logical sum of 0 is always 1, the output potential switching circuit 16
The output of 0 is low potential (0 (v)) and high potential Vd every cycle.
Toggle alternately with d. Therefore, the output signal line 150,
The potential of 151 changes as shown in FIG. At this time, the output signal lines 150 and 151 both have a rising waveform in the odd cycle and a falling waveform in the even cycle. Therefore, the phase relationship between the output signal lines 150 and 151 does not become opposite in any combination of input signals, and it is possible to prevent an increase in signal propagation delay due to the influence of crosstalk.

In FIG. 4, the signal output is the first in the fourth cycle.
The case where the block A is changed to the second block B is shown. Even in this case, the logical sum of the output enable signals 130 and 230 in the output potential switching circuit 160 is always 1, so that the output of the output potential switching circuit 160 is the low potential (0 (v)) and the high potential Vdd in each cycle. Toggle alternately. Therefore, in the odd cycle, the output signal lines 150, 15
Both 1 have a rising waveform, and both even-numbered cycles have a falling waveform. Therefore, any input signal 140, 14
Even if the combination of 1, 240, 241 is used, the output signal line 1
Since the phase relationship of 50 and 151 does not become opposite phases, it is possible to prevent an increase in signal propagation delay due to the influence of crosstalk.

In FIG. 5, the signal output is first in the fourth cycle.
The case where both the block A and the second block B of FIG. In this case, in the fourth cycle, the output potential switching circuit 1
At 60, since the logical sum of the output enable signals 130 and 230 becomes 0, the output of the output potential switching circuit 160 becomes 4
It does not toggle at the second cycle. Therefore, next, the output enable signal 130 of the first block A or the second block B is output.
Alternatively, when 230 becomes 1, the signal waveform of the output signal line becomes a rising waveform if it was the falling waveform last time, and becomes a falling waveform if it was the rising waveform last time. Therefore, any input signal 140, 141, 24
Even if the combination of 0 and 241, the output signal line 150,
Since the phase relationship of 151 is not reversed, it is possible to prevent an increase in signal propagation delay due to the influence of crosstalk.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
An embodiment will be described. FIG. 6 shows the semiconductor circuit of this embodiment, which is an example in which both the first low potential and the second high potential have the same potential value (Vdd / 2).

The structure of the semiconductor circuit of this embodiment is the same as the drive circuit 120 of FIG. 1 of the first embodiment except that the PMOS transistor 111 and the NMOS transistor 112 are deleted.
The same potential (Vdd / 2) is applied to the drains commonly connected to the MOS transistor 114. Except for the changes described above, the configuration is the same as that of the first embodiment.

The operation of the semiconductor circuit configured as described above will be described with reference to FIG. FIG. 7 shows a case where signals are output to the output signal lines 150 and 151 only from the first block A. When the input signals 140 and 141 have a low potential (0 (v)) and the output of the output potential switching circuit 160 has a low potential (0 (v)), the output signal lines 150 and 151 have the first high potential Vdd. If the output of the output potential switching circuit 160 is the high potential Vdd, the output signal lines 150 and 151
Both become the second low potential (0 (v)). Input signal 14
If 0 and 141 are high potential Vdd, the output signal line 150,
151 has the same potential (first low potential = second high potential) (Vdd / 2) regardless of the output of the output potential switching circuit 160. The output signal lines 150 and 151 both have a rising waveform in the odd-numbered cycles, one has no change and the other has a rising waveform,
Alternatively, both of them have no change, the even-numbered cycles both have a falling waveform, one has no change, the other has a falling waveform, or both have no change.

In this embodiment, the output signal lines 150, 1
The expected value of the potential amplitude of 51 is half the high potential Vdd (Vd
d / 2), which is the minimum. Further, since the first low potential and the second high potential are set to the same potential (Vdd / 2), the control of the drive circuit 120 can be simplified and the output power consumption can be suppressed.

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 8 shows a semiconductor circuit of this embodiment. In the figure, the first block A (10
0) and the output potential switching circuit 160 are as described in the first or second embodiment.

In FIG. 8, a receiver circuit (receiver means) 310 receives a signal from the output signal line 150 and outputs a binary output signal corresponding to the input signal to the output terminal 308. In this receiver circuit 310,
301 is an NMOS cross-coupled differential amplifier, 302 is a PMOS cross-coupled differential amplifier, and one input terminal of each is connected to the output signal line 150. N
The other input terminal of the MOS cross-coupled differential amplifier 301 has a first potential that is between the first high potential Vdd and the first low potential (Vdd / 2 + a) of the drive circuit 120.
The reference potential 303 is input. The other input terminal of the PMOS cross-coupled differential amplifier 302 has a potential between the second high potential (Vdd / 2-a) and the second low potential (0 (v)) of the drive circuit 120. Then, the second reference potential 304 is input. Reference numeral 305 is an enable signal for the NMOS cross-coupled differential amplifier 301. PMOS
The enable signal of the cross-coupled differential amplifier 302 is
It is an inverted signal of the enable signal 305. An exclusive OR 307 receives the output 311 of the NMOS cross-coupled differential amplifier 301 and the output 312 of the PMOS cross-coupled differential amplifier 302. The output to the output terminal 308 of the exclusive OR 307 becomes the output of the receiver circuit 310.

Next, the operation of the semiconductor circuit of this embodiment will be described with reference to FIG. In the figure, the first reference potential 303 is the first high potential Vdd and its half value (Vd
d / 2), and the second reference potential 304 is set between the half voltage value (Vdd / 2) and 0v. Further, the first low potential and the second high potential are set to the same potential (Vdd / 2).

When the input signal 140 of the drive circuit 120 has the waveform shown in FIG. 9B, the output signal line 150 changes as shown in FIG. 9D. The potential of the output signal line 150 is 0 v, the intermediate potential (Vdd / 2), and the high potential Vdd.
There are three types. When the potential of the output signal line 150 is 0 v, the first reference potential 303 of the output signal 311 of the NMOS cross-coupled differential amplifier 301 is the output signal line 1
Since it is higher than the potential of 50, the potential is near 0v. In the output signal 312 of the PMOS cross-coupled differential amplifier 302, the second reference potential 304 is the output signal line 1
Since it is higher than the potential of 50, it also becomes a potential near 0v. Therefore, the output potential of the exclusive OR 307 is 0
and 0v of the input signal 140 of the drive circuit 120
It is restored to the same 0v potential as the potential.

On the other hand, the potential of the output signal line 150 is in the middle (V
At the time of dd / 2), the output signal 311 of the NMOS cross-coupled differential amplifier 301 becomes a potential near 0 v because the first reference potential 303 is higher than the potential of the output signal line 150. Further, the output signal 312 of the PMOS cross-coupled differential amplifier 302 has the second reference potential 304 lower than the potential of the output signal line 150, and thus the high potential Vd.
The potential is near d. Therefore, exclusive OR30
The output potential of 7 becomes the high potential Vdd, and the drive circuit 12
High potential Vdd equal to the high potential Vdd of the input signal 140 of 0
Restored to.

Further, the potential of the output signal line 150 is the high potential V.
When dd, NMOS cross-coupled differential amplifier 301
The first reference potential 303 of the output signal 311 is lower than the potential of the output signal line 150, and thus has a potential near the high potential Vdd. In addition, the output signal 312 of the PMOS cross-coupled differential amplifier 302 has a high potential V because the second reference potential 304 is lower than the potential of the output signal line 150.
The potential becomes close to dd. Therefore, exclusive OR3
The output potential of 07 becomes 0v, and is restored to the same 0v potential as the 0v potential of the input signal 140 of the drive circuit 120.

Therefore, with the above-described structure, it is possible to obtain a semiconductor circuit capable of transmitting and receiving while suppressing an increase in signal propagation delay due to crosstalk.

[0041]

As described above, according to the first to fourth aspects of the present invention, the signal lines extending adjacently and in parallel with each other are not arranged for the respective signal lines provided. Since it is possible to prevent the signals from having an opposite phase relationship,
It is possible to prevent an increase in signal propagation delay due to the influence of crosstalk while suppressing an increase in chip area due to an increase in wiring.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram in the case where the semiconductor circuit has two output signal lines and two output blocks.

FIG. 3 is a diagram showing an operation timing chart in the case where only one block outputs a signal in the semiconductor circuit of FIG.

FIG. 4 is a diagram showing an operation timing chart in the same semiconductor circuit when a block that outputs a signal is switched on the way.

FIG. 5 is a diagram showing an operation timing chart when the two blocks in the same semiconductor circuit stop outputting signals in the middle of the process.

FIG. 6 is a diagram showing a configuration of a semiconductor circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an operation timing chart of the same semiconductor circuit.

FIG. 8 is a diagram showing a configuration of a semiconductor circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing an operation timing chart of the same semiconductor circuit.

[Explanation of symbols]

107 first high potential (Vdd) 108 second low potential (0 (v)) 117 first low potential (Vdd / 2
+ A) 118 Second high potential (Vdd / 2
-A) 119 first low potential (= second high potential) 120 drive circuit (drive means) 130, 230 output enable signals 140, 141 240, 241 input signal to drive circuit 150 output signal line 151 other output Signal line 160 Output potential switching circuit (output potential switching means) 163 Clock signal 303 First reference potential 304 Second reference potential 305 Enable signal 308 Output signal 310 of receiver circuit Receiver circuit (receiver means)

Continued front page    F-term (reference) 5F038 AV06 CD05 CD08 CD09 CD13                       DF08 EZ20                 5F064 BB19 BB26 BB35 CC12 EE15                       EE18 EE19 EE46 EE47                 5J055 AX28 BX17 CX27 DX22 DX43                       DX73 EX02 EX07 EY21 EZ00                       EZ12 EZ31 FX18 GX01 GX04

Claims (4)

[Claims] 1. A first high potential and a first lower potential lower than the first high potential corresponding to a potential of the input signal, the first high potential being connected to an output signal line and receiving a binary input signal. Any one of a first potential combination with a low potential and a second potential combination of a second high potential and a second low potential lower than the second high potential. And a drive means for outputting the potential of the drive means to the output signal line, and an output potential switching means for alternately switching the first potential combination and the second potential combination of the drive means for each cycle. The first low potential of the potential combination is set to a potential equal to or higher than the second high potential of the second potential combination. 2. The semiconductor according to claim 1, wherein the first low potential of the first potential combination and the second high potential of the second potential combination are set to the same potential. circuit. 3. A receiver means is provided, which is connected to the output signal line, and which uses a signal of the output signal line as an input signal and outputs a signal that changes into a binary value corresponding to the input signal. The semiconductor circuit according to claim 1 or 2. 4. Another output signal line extending parallel to and adjacent to the output signal line, and another drive having the same configuration as the drive means according to claim 1 and connected to the other output signal line. 3. The first potential combination and the second potential combination of the other drive means are alternately switched for each cycle by the output potential switching means. Semiconductor circuit.