JP2003022680A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which occurrence of a defective read-out operation of data due to the increase of the number of times of data rewriting processing can be deterred. SOLUTION: In data rewriting processing, write-in operation and erasure operation are performed even to a dummy cell 16 similarly to a memory cell. Also, when data verification is performed in data rewriting processing, reference voltage generated by a reference voltage generating section 15 is compared with voltage of bit lines BL1-BLn and a read-out reference line RL, data of the memory cell and the dummy cell are read out. In data read-out processing, each of voltage of the bit lines BL1-BLn is compared with the read-out reference line RL, and data of a memory cell is read out. Since the dummy cell is deteriorated similarly as deterioration of a characteristic of the memory cell caused by increment of the number of times of rewriting of data, data read-out error can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, an EEPROM (electrically erasable ann).
The present invention relates to a nonvolatile semiconductor memory device such as a d programmable read only memory).

[0002]

2. Description of the Related Art Although an EEPROM is a non-volatile memory that does not require a power source to hold stored data, it has an excellent feature that the stored data can be electrically rewritten. Therefore, it is widely used, for example, as a program memory or a memory card of a computer-embedded device.

FIG. 4 is a schematic block diagram showing the structure of a conventional general EEPROM. EEP shown in FIG.
The ROM includes a memory cell array 1, a word line controller 2, a bit line controller 3, a sense amplifier 4, a reference voltage generator 5,
It has a load 6 and a load 7.

The memory cell array 1 has a structure in which non-volatile memory cells such as floating gate type transistors whose threshold voltage changes according to a storage state are arranged in a matrix. The memory cells in each row in this matrix are connected to the same word line WL1 to word line WLm, and the memory cells in each column are connected to the same bit line BL1 to bit line BLn. However,
m and n show arbitrary natural numbers.

The data stored in the memory cell array 1 is rewritten by a predetermined write voltage or a predetermined write voltage according to the write data on the word lines WL1 to WLm and the bit lines BL1 to BLn corresponding to the target memory cell. Is performed by applying the erase voltage of. Further, in reading the stored data, a predetermined read voltage is applied to the word lines WL1 to WLm corresponding to the target memory cell, and the bit lines BL1 to BLn pulled up to the voltage VR via the load 6 are applied. This is done by detecting the voltage change of.

In the data read process, the word line controller 2 selects one word line corresponding to the address data AD from the word lines WL1 to WLm and applies a predetermined read voltage. Also in the data rewriting process, one word line corresponding to the address data AD is selected from the word lines WL1 to WLm, and the erase voltage is applied when the data is erased, and the write voltage is applied when the data is written. To do.

In the data read process, the bit line controller 3 sequentially selects the bit lines BL1 to BLn by an internal selector circuit and connects them to the input terminal of the sense amplifier 4. In the data write process, first, an erase voltage is applied to all bit lines to erase data. In addition, the input write data WD is held in the internal latch circuit. Next, the write voltage according to each bit value of the held write data WD is applied to the bit lines BL1 to BLn for a predetermined period. afterwards,
The bit lines BL1 to BLn are sequentially selected by the internal selector circuit and connected to the sense amplifier 4, and the data RD detected by the sense amplifier 4 and the data held in the latch circuit are collated for each bit. As a result of this comparison, the write voltage is applied again to the bit for which the detection data RD and the held data do not match. The application of the write voltage and the collation of data are repeated until the detection data RD and the held data match in all the bits.

In the sense amplifier 4, the input terminal I1 is connected to the bit line selected by the selector circuit of the bit line control unit 3 and is pulled up to the voltage VR via the load 6, and the input terminal I2 is connected to the reference voltage. It is connected to the output line of the generator 5 and is pulled up to the voltage VR via the load 7. The input terminal I1 and the input terminal I
The voltage difference from 2 is amplified to detect the data RD of the memory cell.

The reference voltage generator 5 is a block for supplying a reference voltage to the input terminal I2 of the sense amplifier 4, and normally has a dummy cell having a structure equivalent to each memory cell forming the memory cell array 1 inside. is doing. Predetermined data is written in advance in this dummy cell.
Further, it has a switch equivalent to the selector circuit of the bit line control unit 3, and connects the bit line of the dummy cell and the input terminal I2 of the sense amplifier 4 via this switch. That is, a dummy circuit of a circuit from the memory cell to the input terminal I1 via the bit line control unit 3 is formed.

According to the EEPROM having the above configuration, the address data AD
While the read voltage is applied to the word line corresponding to, each bit line is sequentially selected and connected to the input terminal I1 of the sense amplifier 4. As a result, a current flows from the voltage VR through the load 6 to the selected bit line.

At this time, since the current flowing through the bit line differs depending on the data stored in the memory cell, a voltage corresponding to the stored data is input to the input terminal I1. For example, when a floating gate type transistor whose threshold voltage is set according to a storage state is used as a memory cell, the transistor is turned off when the threshold voltage is higher than the read voltage of the word line, and is turned on when the threshold voltage is low. Become. Depending on the conduction state of this transistor, the input terminal I
The input voltage of 1 changes. In the sense amplifier 4, the voltage of the input terminal I1 is compared with the voltage of the input terminal I2 generated by the reference voltage generator 5, and the stored data of the memory cell is read out according to the comparison result.

In the data rewriting process, first, a predetermined erase voltage is applied to the word line selected by the address data AD and each bit line to erase the data in the memory cell connected to this word line. In the following description, it is assumed that the value "0" is set in the memory cell by this data erasing. That is, all the data of the address to be rewritten is cleared to the value "0".

Then, a predetermined write voltage is applied to the word line selected by the address data AD and the bit line corresponding to the write data WD. In the following description, it is assumed that the value "1" is set in the memory cell by this data writing. That is, the value "1" is set to the bit corresponding to the write data WD.

After the write voltage is applied for a predetermined period, the read voltage is applied to the word line of the write address next, and each bit line is sequentially connected to the input terminal I1 of the sense amplifier 4. As a result, the data of each bit is detected by the sense amplifier 4. The detected data RD is collated for each bit with the data of each bit held in the latch circuit of the bit line control unit 3, and the write voltage is applied again to the bit where the detected data RD and the held data do not match. It The application of the write voltage and the data collation are repeated until the detection data RD and the held data match in all bits. For example, since the threshold voltage of the floating gate type transistor changes according to the application time of the write voltage, the threshold voltage can be controlled by adjusting the application time of the voltage.

[0015]

By the way, ordinary EE
In the PROM, there is a problem that the characteristics of the memory cell are deteriorated as the above-mentioned data rewriting process is repeated, the time required for rewriting becomes long, or a rewriting failure occurs.

FIG. 5 is a diagram for explaining the relationship between the number of times data is rewritten and the characteristic deterioration in a memory cell using a transistor whose threshold voltage is set according to the storage state.

FIG. 5A is a schematic graph showing the relationship between the number of rewrites and the threshold voltage. The horizontal axis represents the number of data rewrites and the vertical axis represents the threshold voltage. Further, the curve CV1A shows the change of the high threshold voltage corresponding to the value "0", and the curve CV2A shows the change of the low threshold voltage corresponding to the value "1". As can be seen from this graph, the threshold voltage changes as the number of times of data rewriting increases, and in the example of the figure, the threshold voltage rises according to deterioration. When the low threshold voltage of the value "1" rises and exceeds the read voltage Vw applied to the gate of the transistor, the transistor in the value "1" is turned from the ON state to the OFF state. It becomes impossible to read.

FIG. 5B is a schematic graph showing the relationship between the number of times of rewriting and the input voltage of the sense amplifier. The horizontal axis shows the number of times of data rewriting and the vertical axis shows the input voltage of the sense amplifier. Further, a curve CVB1 shows a change of an input voltage for a high threshold voltage memory cell in which a value '0' is stored, and a curve CVB2 shows an input for a low threshold voltage memory cell in which a value '1' is stored. The change in voltage is shown. As can be seen from this graph, the input voltage of the sense amplifier changes due to the increase of the threshold voltage, and in particular, the change of the input voltage to the memory cell in which the value '1' at which the transistor changes from the ON state to the OFF state is stored. Is remarkable. This voltage is the reference voltage Vref of the sense amplifier.
If it exceeds, the value "0" will be returned for the data of value "1".
Erroneous data is detected by the sense amplifier.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of suppressing the occurrence of a data read failure due to an increase in the number of data rewriting processes.

[0020]

In order to achieve the above object, a semiconductor memory device of the present invention is arranged in a matrix, connected to the same word line for each row, and connected to the same bit line for each column. In a data read process, a plurality of connected memory cells are provided, a read voltage is applied to a word line corresponding to a desired read address, and the stored data in the memory cell is read according to the voltage level of the bit line, In the data rewriting process, after applying a predetermined erase voltage to the word line and the plurality of bit lines corresponding to a desired write address, a write voltage according to desired write data is applied, and after applying the write voltage, The stored data of the memory cell corresponding to the write address is read out and collated with the write data,
A semiconductor memory device in which application of the write voltage is repeated according to the matching result, the read reference line being connected to the read reference line and being connected to each of the plurality of word lines, which is equivalent to the memory cell. A plurality of read reference memory cells having different structures, and in the data read process, the stored data of the memory cells is read according to the comparison between the voltage of the bit line and the voltage of the read reference line, and at the time of the data collation. A data read circuit for reading data stored in the memory cell and the read reference memory cell according to a comparison between a voltage of the bit line and the read reference line and a predetermined write reference voltage; and a read operation in the data rewriting process. After applying the erase voltage to the reference line, apply the specified write voltage. And, after application of the write voltage, and compares the stored data and the predetermined data of the read reference memory cell read in the data detection circuit,
And a control circuit that repeats the application of the write voltage according to the comparison result.

According to the semiconductor memory device of the present invention, in the data rewriting process, the predetermined write voltage is applied after the erase voltage is applied to the read reference line. After the application of the write voltage, the stored data of the read reference memory cell read according to the comparison between the voltage of the read reference line and the predetermined write reference voltage is collated with the predetermined data. The application of the write voltage is repeated according to the comparison result. As a result, predetermined data is written in the read reference memory cell. Since the read reference memory cell has a structure equivalent to that of the memory cell, the characteristics of the read reference memory cell deteriorate like the memory cell as the number of times of rewriting increases. In the data read process, the stored data in the memory cell is read according to the comparison between the voltage of the bit line and the voltage of the read reference line, so that there is a change in the voltage of the bit line and a change in the voltage of the read reference line due to deterioration of the characteristics. To approximate.

In the memory cell and the read reference memory cell, the threshold voltage changes according to a predetermined write voltage applied to the word line and the bit line, and the read voltage applied to the word line. A transistor that changes the voltage level of the bit line according to the difference between the voltage and the threshold voltage may be included.

Further, the control circuit may count the occurrence of the data writing process and write the data into the read reference memory cell at a predetermined frequency based on the counting result.

It is also possible to have a write reference memory cell having a structure equivalent to that of the memory cell, storing predetermined data and outputting the write reference voltage according to the stored data.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device shown in FIG. 1 includes a memory cell array 11, a word line control unit 12, a bit line control unit 13, a data read unit 14, a reference voltage generation unit 15,
And a dummy cell array 16.

The memory cell array 11 has a structure in which non-volatile memory cells such as floating gate type transistors whose threshold voltage changes according to a storage state are arranged in a matrix. The memory cells in each row in this matrix are connected to the same word line WL1 to word line WLm, and the memory cells in each column are connected to the same bit line BL1 to bit line BLn.

The data stored in the memory cell array 11 is rewritten by a predetermined write voltage or a predetermined write voltage according to the write data in the word lines WL1 to WLm and the bit lines BL1 to BLn corresponding to the target memory cell. Is performed by applying the erase voltage of. Further, the reading of the stored data is performed by applying a predetermined read voltage to the word lines WL1 to WLm corresponding to the target memory cell and detecting the voltage change of the bit lines BL1 to BLn.

In the data read process, the word line controller 12 selects one word line corresponding to the address data AD from the word lines WL1 to WLm and applies a predetermined read voltage. Also in the data rewriting process, one word line corresponding to the address data AD is selected from the word lines WL1 to WLm, and the erase voltage is applied when the data is erased, and the write voltage is applied when the data is written. To do.

In the data read process, the bit line control unit 13 sequentially selects the bit lines BL1 to BLn and connects them to the input line SB of the data read unit 14. In addition, the read reference line RL connected to the dummy cell array 16 and the input line Rr of the data read unit 14
ef is connected.

In the data write process, first, the erase voltage is applied to all the bit lines and the read reference line RL. It also holds the input write data WD. Next, a write voltage according to each bit value of the held write data WD is applied to the bit lines BL1 to BLn for a predetermined period, and a predetermined write voltage is also applied to the read reference line RL. After that, the bit lines BL1 to BLn are sequentially selected and connected to the data reading unit 14, and the data RD detected by the data reading unit 14 and the held write data WD are collated for each bit. As a result of this comparison, the detection data R
The write voltage is applied again to the bit for which D and the held data do not match. The application of the write voltage and the collation of data are repeated until the detection data RD and the held data match in all the bits.

In the data read process, the data read section 14 amplifies the voltage difference between the input line SB and the input line Rref to detect the stored data in the memory cell. Further, at the time of collating data in the data rewriting process, the voltage difference between the input line SB and the input line Wref or the voltage difference between the input line Rref and the input line Wref is amplified to detect the storage data of the memory cell or the dummy cell.

The reference voltage generating section 15 is a block for supplying a reference voltage to the input line Wref of the data reading section 15 at the time of collating data in the data rewriting process. For example, a dummy cell having a structure equivalent to each memory cell forming the memory cell array 1 may be used to form a dummy circuit of a circuit from the memory cell to the input line Wref via the bit line control unit 13. Alternatively, the reference voltage may be generated by another constant voltage circuit.

The dummy cell array 16 has a structure in which a plurality of dummy cells having a structure equivalent to each memory cell of the memory cell array 11 are connected to the read reference line RL instead of the bit line. The dummy cells are further connected to the word lines WL1 to WLm, respectively. That is, the dummy cell array 16 corresponds to one column of memory cells of the memory cell array 11. More than,
3 is a description of each component of the semiconductor memory device shown in FIG. 1.

Next, a more specific configuration example of the above-mentioned memory cell array 11 and its peripheral circuits will be described. FIG. 2 is a schematic block diagram showing a more specific configuration example of the memory cell array 11 and its peripheral circuits.

In the example of FIG. 2, the memory cell array 11
Is constituted by a memory cell Mjk (where j is an integer of 1 ≦ j ≦ m and k is an integer of 1 ≦ k ≦ n) including a floating gate type transistor. The gate of the floating gate type transistor is the word line Wj.
In addition, the drain is connected to the bit line BLk and the source is connected to the reference potential line, and the threshold voltage rises or falls according to the erase voltage or the write voltage applied to the word line and the bit line.

The dummy cell array 16 is composed of dummy cells DC1 to DCm which are floating gate type transistors equivalent to the memory cell array 11. In this floating gate type transistor, the gate is the word line Wj and the drain is the read reference line RL.
In addition, the sources are connected to the reference potential line, respectively, and the threshold voltage rises or falls according to the erase voltage or the write voltage applied to the word line and the read reference line RL.

In the selector circuit 131, the sources are connected to the bit lines BL1 to BLn of the memory cell array 11 and the drains are commonly connected to the input line SB of the data reading section 14, and the transistors Q1 to Q are connected.
have n. In the data rewriting process and the data reading process, the transistors Q1 to Q
n gate voltage B1 to gate voltage Bn are controlled by a control circuit (not shown) to control the bit lines BL1 to BLn.
And the input line SB are sequentially connected.

The transistor 134 is the transistor Q1.
A transistor having a structure equivalent to that of the transistor Qn, the source of which is connected to the read reference line RL of the dummy cell array 16 and the input line Rr of the data reading unit 14.
The drain is connected to ef. Also, the gate voltage B
The same voltage as the gate voltage that sets the transistors Q1 to Qn to the conductive state is applied to R and is always set to the on state.

The sense amplifier 142 amplifies the voltage difference between the input terminal I1 and the input terminal I2 to detect the storage data of the memory cell or the dummy cell.

The input terminal I1 of the sense amplifier 142 is connected to the input line SB via the drain-source terminal of the transistor 143, and the transistor 1
Input line Rre via the drain-source terminal of 44
It is connected to f and is further pulled up to the voltage VR via the load 147. The input terminal I2 of the sense amplifier 142 is connected to the input line Rref via the drain-source terminal of the transistor 145 and is pulled up to the voltage VR via the load 148. It is connected to the reference potential line via the transistor 146 and the transistor 151 which are connected in series.

The transistor 151 is a floating gate type transistor having a structure equivalent to that in the memory cell array 11, and is preset to a predetermined threshold voltage. Further, the same voltage as the read voltage Vw applied to the word line is applied to the gate.

The latch unit 133 is a block that temporarily holds the input write data WD. The rewrite control unit 132 is a block that controls the voltage applied to each bit line and the read reference line RL in the data rewrite processing, and performs processing related to data collation.
That is, in the data rewriting process, the erase voltage is applied to all the bit lines and the read reference line RL, and then,
A write voltage according to each bit value of the write data WD held in the latch unit 133 is applied to the bit lines BL1 to BLn for a predetermined period, and a predetermined write voltage is also applied to the read reference line RL. After that, at the time of data collation, the data RD detected by the sense amplifier 142 and the write data W held in the latch unit 133
Each bit of D is sequentially collated, and the write voltage is repeatedly applied to the unmatched bits in the collation result.

The read control unit 141 is a block that controls the gate voltages of the transistors 143 to 146 according to the processing and sets them to the on state or the off state. That is, in the state in which the write voltage is applied to the input line SB and the input line Rref by the rewrite control unit 132, the transistors 143 to 145 are set to the off state and the sense amplifier 14 is set.
2 and the rewrite control unit 132 are separated. In the data reading process, the transistors 143 and 145 are turned on and the transistor 1 is turned on.
44 and the transistor 146 are turned off,
The input terminal I1 of the sense amplifier 142 and the input line SB,
The input terminal I2 and the input line Rref are connected to each other. Further, at the time of data collation of the memory cell, the transistors 143 and 146 are turned on and the transistors 144 and 145 are turned off. As a result, the input terminal I1 and the input line SB of the sense amplifier 142 and the input terminal I2 and the input line Wref are connected to each other. At the time of data matching of the dummy cell, the transistors 144 and 146 are set to the ON state, the transistors 143 and 145 are set to the OFF state, and the input terminal I1 and the input line Rref of the sense amplifier 142 and the input terminal I2 and the input line Wref of the sense amplifier 142 are set. Connect each.

The above is the memory cell array 11 shown in FIG.
And each component of the peripheral circuit.

The operation of the semiconductor memory device shown in FIGS. 1 and 2 will be described below. First, in the data read process, a read voltage is applied to the word line corresponding to the address data AD, and each bit line is sequentially selected by the selector 131 and connected to the input line SB of the data read unit 14. At this time, the transistors 143 and 145 are set to the on state, and thus the selected bit line is pulled up to the voltage VR via the load 147, and similarly, the read reference line RL is also connected via the load 148. It is pulled up to the voltage VR.

At this time, since the current flowing through the bit line varies depending on the data stored in the memory cell, a voltage corresponding to the stored data is input to the input terminal I1 of the sense amplifier 142. That is, when the threshold voltage of the floating gate type transistor is higher than the read voltage of the word line, the transistor is turned off and the voltage of the input terminal I1 becomes high level. When the threshold voltage is low, the transistor is turned on and the voltage of the input terminal I1 becomes low level. On the other hand, the input terminal I2
Although the voltage of 1 is determined according to the storage state of the dummy cell, as will be described later, since the same data is always set in the dummy cell in the data rewriting process, the voltage of the input terminal I2 is constant. Therefore, the sense amplifier 142 compares the constant voltage of the input terminal I2 with the high level voltage or the low level voltage of the input terminal I1 to read the data of the value “1” or the value “0”.

In the data rewriting process, first, a predetermined erase voltage is applied to the word line and each bit line selected by the address data AD and the read reference line RL for a predetermined period, and the memory cell connected to this word line. Will be erased. That is, all the data of the address to be rewritten is cleared to the value "0".
Since the same erase voltage is applied to all bit lines at the time of applying the erase voltage, for example, with all the transistors Q1 to Qn of the selector 131 set to the conductive state, all the bit lines are erased at once. An erase voltage may be applied.

Next, a predetermined write voltage is applied to the word line selected by the address data AD and the bit line corresponding to the write data WD held in the latch section 133. That is, the write data WD
The value "1" is set to the bit corresponding to.

After the write voltage is applied for a predetermined period, the memory cell MCjk and the dummy cell DCj are next.
Stored data is read out for data collation. When the storage data of the memory cell MCjk is read,
A read voltage is applied to the word line of the write address, and each bit line is sequentially connected to the input line SB by the selector circuit 131. Also at this time, the transistor 1
43 and transistor 146 are turned on, and transistor 144 and transistor 145 are turned off. As a result, the bit line selected by the selector circuit 131 is pulled up to the voltage VR via the load 147. Similarly, the input line Wref is loaded by the load 148.
Is pulled up to the voltage VR via. In this way, the voltage of each bit line and the voltage of the reference voltage generator 15 are compared in the sense amplifier 142, and the memory cell MC
The stored data of jk is read.

When the data stored in the dummy cell DCj is read, the transistors 144 and 146 are turned on and the transistors 143 and 145 are turned off. Therefore, the read reference line RL is connected to the input terminal I1. To be done. Therefore, the voltage of the read reference line RL and the voltage of the reference voltage generation unit 15 are compared in the sense amplifier 142, and the storage data of the dummy cell DCj is read.

The data RD of the memory cell MCjk detected by the sense amplifier 142 is collated bit by bit with the data of each bit held in the latch unit 133, and the detected data RD and the held data are not matched. The write voltage is applied again. The application of the write voltage and the data collation are repeated until the detection data RD and the held data match in all bits. Similarly, the data of the dummy cell DCj is also collated with predetermined data (value “1”), and if they do not match, the write voltage is repeated on the read reference line RL.

As described above, according to the semiconductor memory device of the embodiment of the present invention, writing and erasing are executed on the dummy cell referred to in the data read process, similarly to the memory cell. Therefore, with the deterioration of the characteristics of the memory cell due to the increase in the number of times of rewriting data, the dummy cell that generates the reference voltage at the time of reading data is also deteriorated.

FIG. 3 is a schematic graph showing the relationship between the number of rewrites and the voltage of the input line of the data read section 14 in the semiconductor memory device shown in FIG. Indicates the voltages of the input line SB and the input line Rref at the time of reading data, respectively. Further, a curve CV1 shows a voltage change of the input line SB for a high threshold voltage memory cell storing a value “0”, and a curve CV2 shows a low threshold voltage memory cell storing a value “1”. Shows the voltage change of the input line SB, and the curve CV3 shows the voltage change of the input line Rref connected to the read reference line RL of the dummy cell array 16.

As can be seen from this graph, the voltage of the input line SB for the memory cell storing the value "1" gradually rises with the increase in the number of rewrites, but the dummy cell also has the same characteristic deterioration as the memory cell. As a result, the threshold voltage of the transistor rises, so that the voltage of the input line Rref also rises. Therefore, especially when reading the stored data of the value “1”, it is possible to suppress the decrease in the voltage difference between the input line SB and the input line Rref, and thus it is possible to reduce the data read error. In addition, the maximum number of rewrites that guarantees normal operation can be increased as compared with the conventional one.

Further, at the time of data collation in the data rewriting process, the data of the memory cell and the dummy cell are read based on the reference voltage generated by the reference voltage generating section 15, and the read data matches the desired data. The application of the write voltage is repeated until this is done. Therefore, the data rewriting error can be reduced as compared with the case where the data collation is not performed.

The present invention is not limited to the above embodiment. For example, the bit line control unit 13 may cause the occurrence of data write processing to be counted, and the frequency of data write to the dummy cell may be adjusted based on the count result. For example, when the data writing process occurs twice, the data writing to the dummy cell may be performed once. In this way, the frequency of setting the value “0” or the value “1” to each bit and the frequency of writing data to the dummy cell can be made close to each other, so that the dummy cell may be deteriorated due to deterioration of average characteristics of the memory cell. The characteristic deterioration of can be made closer.

The memory cell array shown in FIG. 2 is merely an example, and the present invention is not limited to this. For example, NAN
The present invention may be applied to memory cells of various types as well as D-type memory cell arrays.

[0058]

According to the present invention, it is possible to prevent the occurrence of data read failure due to the increase in the number of data rewriting processes. Further, since data collation is performed in the rewriting process, it is possible to suppress the occurrence of rewriting failure.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a more specific configuration example of a memory cell array and its peripheral circuits.

FIG. 3 is a schematic graph showing the relationship between the number of rewrites and the voltage of the input line of the data reading unit in the semiconductor memory device shown in FIG.

FIG. 4 is a schematic block diagram showing a configuration of a conventional general EEPROM.

FIG. 5 is a diagram illustrating a relationship between the number of times data is rewritten and characteristic deterioration in a memory cell using a transistor whose threshold voltage is set according to a storage state.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Word line control unit, 13
... bit line control unit, 14 ... data reading unit, 15 ... reference voltage generation unit, 16 ... dummy cell array, MC11 to M
Cmn ... Memory cell, DC1 to DCm ... Dummy cell, 1
31 ... Selector circuit, 132 ... Rewrite control unit, 133
... Latch section, 141 ... Read control section, 142 ... Sense amplifier, 134, 143 to 146, 151 ... Transistor, 147, 148 ... Load.

Claims (4)

[Claims] 1. A plurality of memory cells arranged in a matrix, connected to the same word line for each row, and connected to the same bit line for each column, and having a desired read address in a data read process. A read voltage is applied to the word line corresponding to the word line, the storage data of the memory cell is read according to the voltage level of the bit line, and in the data rewriting process, the word line corresponding to the desired write address and the plurality of bit lines After a predetermined erase voltage is applied to the memory cell, a write voltage according to the desired write data is applied, and after the write voltage is applied, the stored data in the memory cell corresponding to the write address is read and collated with the write data. A semiconductor memory device that repeatedly applies the write voltage according to the matching result, A reference line, a plurality of read reference memory cells connected to the read reference line and connected to the plurality of word lines, respectively, and having a structure equivalent to that of the memory cell; and the bit line in the data read process. The stored data of the memory cell is read according to the comparison between the voltage of the read reference line and the voltage of the read reference line, and at the time of the data collation, the voltage of the bit line and the read reference line is compared with a predetermined write reference voltage. And a data read circuit for reading the stored data of the memory cell and the read reference memory cell, and applying a predetermined write voltage to the read reference line after applying the erase voltage to the read reference line in the data rewriting process. Read out in the data detection circuit after application of A semiconductor memory device comprising: a control circuit for collating stored data of a reference memory cell with predetermined data and repeating application of the write voltage according to the collation result. 2. The read voltage applied to the word line is changed in a threshold voltage of the memory cell and the read reference memory cell according to a predetermined write voltage applied to the word line and the bit line. 2. The semiconductor memory device according to claim 1, further comprising a transistor that changes a voltage level of the bit line according to a difference between a voltage and the threshold voltage. 3. The semiconductor device according to claim 1, wherein the control circuit counts the occurrence of the data write process, and writes data to the read reference memory cell at a predetermined frequency based on the count result. Storage device. 4. The semiconductor according to claim 1, further comprising a write reference memory cell that has a structure equivalent to that of the memory cell, stores predetermined data, and outputs the write reference voltage according to the stored data. Storage device.