JP2003022214A - Memory controller and control equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller for improving the performance of data update by bit units. SOLUTION: This memory controller is provided with a writing control part 24 for transmitting writing permission signal to each bit of a memory device 20 and a data control part 22 for applying data to each bit of a data memory. The writing control part applies the writing permission signal to all the bits at the time of executing data writing by word units, and applies the writing permission signal only to the bits being the targets of data update at the time of executing data writing by bit units. The data control part applies the information of word data to each bit as they are at the time of executing the data writing by word units, and applies the same data to all the bits at the time of executing the data writing by bit units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and control equipment.

[0002]

Ladder languages are generally used as programming languages in PLCs and other control devices. The addressing in this ladder language is 8bi
There are channel addressing for designating t or 16 bits (1 word = 1 channel) and bit addressing for designating 1 bit (contact). This bit addressing consists of the channel address to which the bit to be accessed belongs and the bit address that represents the bit position within that channel.

Therefore, in the access to the data memory in the control device, the channel unit and the 1 bit unit access are mixed. Access to a plurality of bits in a channel is handled by a program because there is no designation method.

As a normal memory device such as SRAM, a device having a width in data is used. For example, in the memory device 1 shown in FIG. 1, 8-bit data can be read / written at one time for each element. Based on the signal from the memory controller 2, 8 bits given to the data terminals D7-D0 for a predetermined area specified according to the address information given to the address terminals A12-A0.
Minute data is written and read from the D7-D0 data terminals.

On the other hand, in data access in a control device such as a PLC, access is not always made in units of 8 bits, but access is frequently made to an arbitrary 1 bit in 8 bits. In this case, at the time of reading, after reading 8 bits, the memory controller 2 selects an arbitrary 1 bit, whereby data can be read by one memory access.

However, in the case of writing (writing), from the memory controller 2 to the memory device 1
However, since the data can only be written in 8-bit units, the memory controller 2 first reads the 8-bit data forming the channel including the write-target bit (channel read), and the write-target 1b.
Only it is changed to generate new 8 ibt data, and the updated 8 bit data is collectively written to the storage area of the channel address read again. As a result, before and after writing, only the corresponding 1-bit data is updated. In the above example, 8b
Although the operation of the memory controller in the unit of it has been described, the same applies to the case of the unit of 16 bits.

As described above, the conventional 8 bits or 1
In the memory controller 2 in units of 6 bits, 1 bit
In the case of correcting only one, the read-modify-write operation is performed in which the word data to which the 1 bit belongs is read once, the corresponding bit is changed, and then the data is written back. Therefore, the memory controller 2 needs to access the memory twice, in order to correct a certain 1-bit data based on the bit write instruction from the higher order.

Therefore, in the memory controller 2, not only the processing time is required and the performance is deteriorated, but also a sequencer for performing the read / modify / write operation, a register for temporarily storing the read word data, and the like. It requires a complicated configuration.

Moreover, the update processing of 1-bit data is performed by updating ON / OFF information of an input device such as a sensor,
Since a control device has a relatively high frequency such as an ON / OFF control command for an output device such as a lamp or a motor, the performance degradation in the update process of the 1-bit data becomes a significant problem.

On the other hand, if attention is paid only to the update of 1-bit data, a method can be adopted in which only 1 bit is allocated to 1 channel (1 word) so that a change can be made in units of words even when 1-bit is accessed. With this configuration, the data can be updated in bit units at a high speed.
Since 1 bit is represented by it or 16 bits, the use efficiency of the memory deteriorates. Further, in the control device, bit data may be collectively handled as word data, and in such a case, memory access is required by the number of bits forming a word, which causes a reduction in speed. Therefore, such a response is not very realistic.

According to the present invention, a memory of a bit unit is used and a write enable signal is controlled for each bit to simplify the circuit of the memory controller and improve the performance of updating data in a bit unit. An object is to provide an apparatus and a control device.

[0012]

A memory control device according to the present invention is a data memory of a control device capable of writing data to a data memory in units of words each consisting of a plurality of bits and writing data in units of bits. It is a control device. Further, it has write control means for transmitting a write enable signal to each bit of the data memory, and data control means for giving data to each bit of the data memory. The write control unit gives the write enable signal to all bits when writing data in the word unit, and writes data to the bit to be updated in the bit unit. The write permission signal is given only to the above. Further, the data control means gives the information of the word data as it is to each bit when writing the data in the word unit, and in the case of writing the data in the bit unit, to all the bits. I tried to give the same data.

Further, the control device according to the present invention stores a data memory, an arithmetic unit for accessing data to the data memory to execute arithmetic processing, and an arithmetic result in the arithmetic unit in the data memory. And the memory control device.

According to the present invention, when writing data in word units, a write enable signal is given to all the bits of the data memory, and word data is given to the corresponding bits so that a predetermined area is written. Data can be written in batch.

On the other hand, in the case of writing the data in bit units for updating only the predetermined 1 bit, the same value as the data to be updated is given to all the bits. Then, the write enable signal is given only to the bit to be updated. As a result, the given data is stored and updated in the bit to be updated. Further, since the write enable signal is not given to the other bits, even if the above data is given, they are not stored and are not updated. Therefore, the data can be updated only for the target bit.

As a result, not only writing data in word units but also writing data in bit units (change of only one bit of interest) can be performed by one memory access, thereby improving the throughput as a control system. You can

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a preferred embodiment of a PLC which is a control device according to the present invention. As shown in the figure, outside the ASIC 10, a program memory 11 in which a user program is stored, a high-speed operation data memory 12 as an external memory, and a low-speed operation data memory 13 are provided. Even if the battery 14 is connected and the main power supply of the PLC is cut off, the power supply from the battery 14 is received and the stored data is retained.

In the ASIC 10, the program memory 1
An arithmetic unit 15 that reads out a user program in 1 and executes a predetermined arithmetic process, and a high-speed internal memory 16 that is a high-speed arithmetic data memory that stores data used in the arithmetic process by the arithmetic unit 15 are provided. Regarding the memory access speeds of the above-mentioned three arithmetic data memories, the low speed arithmetic data memory 13 has the slowest memory speed (for example, 55 to 70n).
s), the high-speed built-in memory 16 is the fastest (for example, 7 to 10 ns). The speed of the high-speed arithmetic data memory 12 is intermediate (for example, 15 to 25 ns). The low-speed operation data memory 13 and the high-speed operation data memory 12 have the same capacity (for example, 1 to 4 Mbit), and the high-speed internal memory 16 has a smaller capacity (for example, 8 to 256 kbit).

In the ASIC 10, a memory timing controller 18 for actually reading / writing data from / to each of the memories 11 to 13 and 16 described above at a predetermined timing and three data memories 12, 13 and 16 are provided.
An access controller 17 for controlling data access is also provided. The memory timing controller 18 is provided corresponding to each memory and can operate independently. Further, in the present embodiment, the access controller 17 determines an access destination of the three data memories 12, 13, 16 in accordance with a request from the arithmetic unit 15 and is connected to the arithmetic data memory of the determined access destination. An operation command is sent to the memory timing controller 18. The memory timing controller 18 is
According to the received operation command, data is read / written from / to the connected arithmetic data memory.

As described above, since the memory timing controller 18 can operate independently, the memory timing controller 18 can also operate at the same timing. Therefore, for example, when there are a plurality of access destinations determined by the access controller 17, those Multiple memory timing controllers 18
Operate simultaneously, and data can be simultaneously written to a plurality of operation data memories. Further, the data memories 12, 13 and 16 are connected by independent and independent memory buses (one for high speed, one for low speed and one for ultra high speed).

The data stored in each of the data memories 12, 13, 16 is, for example, ON from an input device directly connected to the PLC or via a network.
There are ON / OFF information and ON / OFF information for the output device.

The memory device targeted by the present invention corresponds to any of the above-described high-speed operation data memory 12, low-speed operation data memory 13 and high-speed built-in memory 16. Hereinafter, when there is no need to distinguish them, they are referred to as "memory device 20". Of course, the illustrated example has three types of memories, but the present invention has one or two or four memories.
Of course, it can be applied to the one having more than one memory. In the case of a device having a plurality of memories, the present invention may be applied to at least one.

Here, in the present invention, the memory timing controller (memory controller: memory control device) 1
8 and memory device 20 read / written by the same
Is as shown in FIG. First, as a premise, one word in this embodiment is composed of 8 bits.

The memory device 20 is writable for each bit. That is, the write enable terminal W is provided for each of the 8-bit data input / output terminals D0 to D7. Thus, only when the write enable signal is input to the write enable terminal W, the data given to the data input / output terminal is actually written in the memory.

Therefore, all write enable terminals W
When a write permission signal is given to, a word write process for collectively writing data of 8 bits can be performed. Further, by giving a write enable signal only to the write enable terminal W of any one bit of 8 bits, it is possible to write only that bit. Therefore, data change in bit units can be performed by one memory access.

On the other hand, the memory timing controller 18
A write signal indicating a write operation, a bit access signal indicating a bit operation, a bit address signal indicating a bit position in a word, and word write data and bit write data are supplied to the upper control system. Then, based on these signals, data, etc., the memory timing controller 18 writes data in a predetermined area of the memory device 20.

Then, the memory timing controller 1
Reference numeral 8 has a data control section 22 for giving write data to the data input / output terminals D0 to D7, and a write control section 24 for giving a write enable signal to the write enable terminal W. Then, a bit access signal is provided to the data control unit 22 and the write control unit 24, and when the bit access signal is ON, a bit access for writing to a predetermined 1 bit is performed. If the bit access signal is OFF, a process for performing word access for writing in units of one channel (one word) is performed.

The data controller 22 is supplied with data (bit data signal or word data signal) to be written from the arithmetic unit 15 via the access controller 17. The data is given to the data control unit 22 via the predetermined signal lines S1 and S2, and at this time, the bit access signal is also given. As a result, the data control unit 22 knows which of the signal lines S1 and S2 the input signal is the data to be written.

Then, the data control unit 22 selects word data or bit data expanded to the word width by the bit access signal, and the write data to the memory is given to the memory device 20 via the data bus B1. That is, in the case of word data, since data for one channel is given through the signal line S2, each bit forming one channel is given to each data input / output terminal D0 to D7 of the corresponding memory device 20.

In the case of bit data, data to be written (1/1 /
0) is applied to all the data input / output terminals D0 to D7 of the memory device 20. That is, when the data to be written is "1", all the data input / output terminals D0 to D
Give “1” to 7. That is, the data (all the same value) obtained by expanding the 1-bit data to the word width for one channel (8 bits in this embodiment) is given to the memory device.

The data control unit 22 converts data in the case of word write and in the case of bit write. In the case of word write, the information of word data is directly output to the data bus B1 for the memory. In the case of bit write, as the write data to the memory, the value of bit data given via the signal line S1 for all bits is output.

In this way, the data control unit 22 functions as a multiplexer (selector 22a) that uses the bit access signal as a selection signal (switching signal) (see FIG. 4). It should be noted that although the bit data is expanded to have a word width, data in which the expanded one channel of the upper control circuit (arithmetic unit) has the same value is generated and supplied to the data control unit 22. (In that case, the data control unit 22 is realized by a simple multiplexer (selector) as shown in FIG. 3), and the data control unit 22 that has received 1-bit data to be written.
However, bit data expanded to the word width may be generated.

On the other hand, the write control section 24 receives a write signal given from the higher order and gives a write enable signal to the write enable terminal W of a predetermined bit. Specifically, when the bit access signal is OFF, that is, in the case of word access, the write enable signal is given to the write enable terminals W of all the bits. As a result, the data control unit 22 sends each data input / output terminal D0.
The data given to D7 are written to the memory.

When the bit access signal is ON, the write control unit receiving the write signal sets the desired 1
A write enable signal is given only to the write enable terminal W of one bit (bit for which data is updated).

That is, since the decoder 26 is provided with a bit address for specifying a bit for updating data, the decoder 26 recognizes which bit is to be written, and converts it into a selection signal for each bit. That is, when the n-th bit is the data update target, a selection signal in which the n-th bit becomes 1 and the other bits become 0 is generated.
In other words, the decoder 26 is a circuit that converts a given bit address into a bit selection signal in units of 1 bit. In this embodiment, since one word has 8 bits, the bit address is 3 bits and the bit selection signal is 8 bits.
Composed of it. The selection signal is given to the write control unit 24, and the write permission signal is given to the bit whose selection signal is "1".

With such a configuration, the write processing in word units can be performed by one memory access as in the conventional case by giving the write permission signal to all the bits. Then, when performing the writing process in bit units, by giving a write enable signal only to the write target bit, the data is updated at the same time. At this time, since the write enable signal is not given to the other bits, the data is not updated.
Therefore, since only the bit to be written is updated, it is not necessary to read the data that is not updated as in the conventional case, and the data can be written with one memory access. Therefore, the throughput of the control system can be increased.

Then, as an example of a concrete configuration of the write control section 24, it can be realized by a circuit as shown in FIG. That is, the two-input AND elements 24a and 24b are
One of the AND elements 24a and 24b is provided with a write signal, and the other input terminal is provided with a bit selection signal and a bit access (logical value is inverted by the knot element 24c). And the two AND elements 2
The outputs of 4a and 24b are two-input OR elements 24d.
To give a logic circuit.

With such a configuration, when writing the word data, the bit access is turned off, so that it is inverted by the knot element 24c and the input of one AND element 24a becomes "1". Therefore, when a write signal is input (1), the output of one AND element 24a becomes "1", so that the output of the OR element 24d becomes "1" regardless of the bit address, and for all bits. And a write enable signal is output.

On the other hand, contrary to the above, bit access is turned on.
In the case of (1), "0" is inverted and input to the input terminal of one AND element 24a, so that the output of the AND element 24a remains "0". Therefore, the output of the other AND element 24b becomes "1" only when the bit selection signal is "1" (when the write signal is input), which causes the output of the OR element 24d, that is, the write enable signal. It is output only for that bit.

Although FIGS. 3 and 4 show an example of the functions required to perform bit-wise writing, which is the main part of the present invention, of course, the word address (channel address) is also controlled by the higher order. Provided by the device. Word addresses are provided on a common bus for all memory devices. Although not shown, the same function as the conventional one is applied to the function for reading data.

Next, the operation of the above-mentioned device will be described using specific values. First, the bit address is specified by 3 bits as shown in FIG. When writing the word data (0100 — 0110), the bit access signal (6) becomes inactive, and the write enable signal becomes active for all bits.
Write data (0100 — 0110) is provided as word data provided from the signal line S2.

In this case, the upper 2nd bit will be described as an example with reference to FIG. The upper 2nd bit data is
It is "1". Therefore, the word data (n) is provided with data “1”. As the bit access signal, "0" is supplied from the upper control device for word access. The data control unit 22 is a selector 22a that selects bit data or word data (n) in response to a bit access signal in terms of bits. Since the bit access is "0", the word data (n) is selected, and "1" which is the value of the word data (n) is output as the write data to the memory.

In the write control section 24, since the bit access signal is "0", the logical product of the inversion of the write signal and the bit access signal becomes true, and the write enable signal is given to the write signal to the memory corresponding to the relevant bit. Is output. At this time, the bit selection signal (n) does not affect the control regardless of the value. This is the case in bit units. When viewed in word units, the value of word data is output as the data for the memory in FIG. 3, and the write enable signal is given to the write enable W of each bit of the memory device 20. It will be. Therefore 8bi
All the memory of t are word data (0100_011
0) is updated.

On the other hand, in the case of bit write, it is as follows. First, the case where the bit data “0” is written in the third bit is taken as an example. In this case, the write signal in FIG. 4 becomes active. The bit access signal also becomes active. The bit data is provided with write data “0”. In addition, the bit address contains 3
(101) showing the bit eye (6 bi counted from LEB
The value of t) is provided. Since the word data is ignored by the circuit in the subsequent stage, the data may have any value.

Since the bit to be written is the upper 3rd bit (the 6th bit counted from LEB3), the bit shown in FIG.
D5 becomes the circuit for the connected memory.
Bit access is active and "0" is provided for bit data. Since the bit access is active, the selector 22a for the corresponding bit of the data control unit 22 outputs the bit data to the data bus B1 as data for the memory.

In the write controller 24, the bit selection signal (n = 5) is active and the other AND element 2
As for the bit write control signal output from 4b, the state of the write signal is output as a write signal to the data memory 20 (output of the OR element 24d). Therefore,
Data of "0" is written to D5 of the 6th bit.

For the other bits, "0" is output to the data bus B1 as the data for each memory, which is the same as the sixth bit for the data, but the write control signal is active because the bit access is active. The word write control signal (the output of one AND element 24a) becomes inactive. Further, since the bit selection signal (n) is also inactive except for the corresponding bit, the bit write signal (output of the other AND element 24b) is also inactive. Therefore, since the write control signal is not output to the memory of other bits, the data of only the bit indicated by the bit address is updated.

[0048]

As described above, according to the present invention, not only the writing of data in units of words but also the writing of data in units of bits (only one bit of interest is changed)
Can be achieved with one memory access, and the throughput as a control system can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional example.

FIG. 2 is a diagram showing an entire system to which the present invention is applied.

FIG. 3 is a diagram showing a preferred embodiment of a memory control device according to the present invention.

FIG. 4 is a diagram showing an example of internal structures of a data control unit and a write control unit.

FIG. 5 is a diagram showing an example of a data structure of a data memory.

[Explanation of symbols]

10 ASIC 11 Program memory 12 High-speed operation data memory 13 Low-speed calculation data memory 14 battery 15 Operation part 16 high speed internal memory 17 Access controller 18 Memory Timing Controller 20 memory devices 22 Data control unit 24 Write Control Unit 26 Decoder

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Claims (2)

[Claims] 1. A data memory control device of a control device capable of writing data to a data memory in units of words made up of a plurality of bits and writing in units of bits, wherein each bit of the data memory is Write control means for transmitting a write enable signal, and data control means for giving data to each bit of the data memory, and the write control means, when writing data in the word unit, The write enable signal is given to all the bits, and when the data is written in the bit unit, the write enable signal is given only to the bit whose data is to be updated. When writing data in, the word data information is given to each bit as is, When writing data in the unit, a memory control device characterized by providing the same data to the all bits. 2. A data memory, an arithmetic unit for accessing data to the data memory to execute arithmetic processing, and an arithmetic result of the arithmetic unit stored in the data memory. A control device comprising a memory control device.