JP2003017961A - Gan control amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gain control amplifier whose output is converged a short time in spite of its long response time. SOLUTION: The gain control amplifier comprises a variable gain amplifier 1 that amplifies the amplitude of a received signal, an electric field strength detector 3 that detects the amplitude of the received signal, a comparator 4 that compares a level of the received signal with a reference level Vref, a gain control level generator 5 that increases/decreases a gain control level depending on the positive/negative polarity of a control signal, and a timing generator 6 that intermittently operates the gain control level generator 5. The timing generator 6 outputs a timing signal being at a high level for a prescribed time to control the operation of the gain control level generator 5. When the level of the timing signal is a high level, the gain control level generator 5 is in operation (1st mode). When the level of the timing signal is a low level, the gain control level generator 5 stops its operation (2nd mode).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control amplifier for automatically controlling gain according to an input signal level.

[0002]

2. Description of the Related Art Frequency hopping spread spectrum (F
In an HSS (Frequency Hopping Spread Spectrum) communication system, the state of the communication path may change for each hopping, so it is necessary to adjust the gain of the amplifier in the receiving system. Further, in a communication system with a short hopping interval, it is necessary to adjust the gain in a short time.

FIG. 16 shows a conventional gain control amplifier. The output amplitude is kept constant by detecting the amplitude of the received signal and providing the variable gain amplifier with a gain according to its magnitude. The gain control amplifier of FIG. 16 includes a variable gain amplifier 1 that amplifies the amplitude of the received signal, an electric field strength detector 3 that detects the amplitude of the received signal, and a comparator 4 that compares the potential of the received signal with the reference potential Vref. , A gain control potential generator 5 that raises or lowers the gain control potential according to whether the control signal is positive or negative.

[0004]

However, as shown in FIG.
In the negative feedback type gain control amplifier as shown in (3), since the response time is long, it takes time to converge. In addition, if the response time is shortened, the loop gain becomes high and oscillation may occur without convergence. When oscillating, if the oscillating cycle is close to the data rate, the error rate increases.

Further, since the load capacitance is required for smoothing the control potential, there is a problem that the circuit scale increases.

It is an object of the present invention to provide a gain control amplifier which converges within a short time even if the response time is large.

[0007]

A gain control amplifier according to the present invention comprises a variable gain amplifier for amplifying the amplitude of a received signal, and an electric field intensity detector for detecting the amplitude of the signal according to the output signal of the variable gain amplifier. A comparator for comparing a potential output from the electric field strength detector with a reference potential, and a gain control potential generator for generating a gain control potential according to a control signal of the comparator and supplying the gain control potential to the variable gain amplifier. A first mode for supplying a timing signal to the gain control potential generator, wherein the gain control potential generator outputs high or low in accordance with the timing signal and the control signal. And a second mode for keeping the output potential constant in accordance with the timing signal.

Further, the gain control amplifier according to the present invention is
A variable gain amplifier that amplifies the amplitude of the received signal, an electric field strength detector that detects the amplitude of the signal according to the output signal of the variable gain amplifier, and a potential that is output by the electric field strength detector and a reference potential are compared. , A comparator for generating first and second control signals, and a gain control potential generator for generating a gain control potential according to the first and second control signals and supplying the gain control potential to the variable gain amplifier. It is characterized by doing.

Further, the gain control amplifier according to the present invention is
A variable gain amplifier that amplifies the amplitude of a received signal, an electric field strength detector that detects the amplitude of a signal according to the output signal of the variable gain amplifier, a potential output by the electric field strength detector, and a first reference potential And a first comparator for generating a first control signal, and a second comparator for comparing a potential detected by the electric field intensity detector with a second reference potential to generate a second control signal. It is characterized by comprising a comparator and a gain control potential generator that generates a gain control potential according to the first and second control signals and supplies the gain control potential to the variable gain amplifier.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram of a gain control amplifier according to the first embodiment. The gain control amplifier according to the present embodiment includes a variable gain amplifier 1 that amplifies the amplitude of a received signal, an electric field intensity detector 3 that detects the amplitude of the received signal, and a comparator that compares the output of the detector and the reference potential Vref. 4, a gain control potential generator 5 for raising and lowering the gain control potential according to the positive / negative of the control signal, and a timing generator 6 for intermittently operating the gain control potential generator 5.

The variable gain amplifier 1 controls the gain according to the received signal and amplifies the received signal. In FIG. 1, the output signal of the variable gain amplifier 1 is supplied to the electric field intensity detector 3 via a delay element 2 of the loop, for example, a filter.

The electric field intensity detector 3 detects the amplitude of the output signal of the variable gain amplifier 1. Then, the electric field strength detector 3
The amplitude (potential) detected by is the reference potential Vr in the comparator 4.
ef is compared. The comparator 4 outputs a control signal according to the comparison result.

The gain control potential generator 5 changes the gain control potential according to the control signal from the comparator 4. If the control signal is high, the gain control potential is lowered, and if the control signal is low, the gain control potential is raised (first mode). The output signal (gain control potential) of the gain control potential generator 5 is supplied to the variable gain amplifier 1.

The timing generator 6 outputs a timing signal that remains high for a certain period of time to control the operation of the gain control potential generator 5. The gain control potential generator 5 operates while the timing signal is high (first mode). When the timing signal is low, the gain control potential generator 5 stops operating and the output maintains a constant potential (second mode).

Next, the operation of this embodiment will be described. The received signal is received and amplified by the variable gain amplifier 1. Then, the reception signal received by the variable gain amplifier 1 is supplied to the detector 3 via the delay element 2. In the electric field strength detector 3, the amplitude of this signal is detected. The comparator 4 compares the amplitude (potential) detected by the electric field intensity detector 3 with the reference potential Vref. When the output of the detector is higher than the reference potential Vref, the control signal output from the comparator 4 becomes high. On the other hand, when it is lower than the reference potential Vref, the control signal becomes low.

Then, the gain control potential generator 5 operates according to the control signal. When the control signal is high, the gain control potential generator 5 lowers the gain control potential assuming that the potential of the received signal is higher than the desired level. On the other hand, when the control signal is low, the potential is lower than the desired level, and the gain control potential generator 5 raises the gain control potential.

These operations of the gain control potential generator 5 are controlled by the timing generator 6. When the timing signal output from the timing generator 6 is high, the gain control potential generator 5 operates by receiving this signal, and the gain control is performed based on the control signal of the comparator 4. When the timing signal changes from high to low, the gain control potential of the gain control potential generator 5 is fixed to the gain control potential at the moment when the timing signal becomes low. While the timing signal is low, the gain control potential generator 5 stops operating and keeps its value.

The gain control potential obtained by the control signal is
It is supplied to the variable gain amplifier 1. Then, the variable gain amplifier 1 amplifies the received signal according to the gain control potential. The received signal is amplified when the gain control potential is high and is narrowed when it is low.

FIG. 2 shows an example of an operation timing chart in this embodiment. Now, assume that the potential of the received signal is lower than the desired level. When the timing signal goes high, the gain control potential generator 5 operates and the gain increases. The gain control potential approaches the desired level. When the timing signal becomes low after a fixed time, the gain control potential generator 5 stops operating and the gain control potential is fixed. The gain control potential is fixed at a value close to the desired level. The period when the timing signal output from the timing generator 6 is high needs to be set in advance in consideration of the gain control capability of the gain control potential generator 5.

FIG. 3 is a specific circuit diagram of the gain control potential generator 5, which is a charge pump circuit with a control terminal.
In the gain control potential generator 5, a constant current source I1, a PMOS transistor, an NMOS transistor, and a constant current source I2 are connected in series between the node supplied with the external power supply voltage and the ground. An output signal of a NAND gate to which the inverted signal of the control signal of the comparator 4 and the timing signal of the timing generator 6 are input is supplied to the gate terminal of the PMOS transistor. Further, the output signal of the AND gate to which the control signal of the comparator 4 and the timing signal of the timing generator 6 are input is supplied to the gate terminal of the NMOS transistor.

Then, a PMOS transistor and an NMOS
The connection node (drain terminal node) of the transistor is
It is connected to the output node OUT. This output node O
The gain control potential is output from the UT. A capacitor C is connected between the output node OUT and the ground.

Now, assume that the timing signal is high. When the control signal of the comparator 4 is high, both the outputs of the NAND gate and the AND gate are low. Therefore, since the PMOS transistor is turned on, the gain control potential is raised.

On the other hand, when the control signal of the comparator 4 is low, both the outputs of the NAND gate and the AND gate are high. Therefore, since the NMOS transistor is turned on, the gain control potential is lowered.

4 and 5 are diagrams specifically showing the delay element in FIG. FIG. 4 shows a variable gain amplifier 1
Variable gain low noise amplifier LNA (Low Noise Amplif
ii) and the frequency mixer MIX as the delay element 2. In addition, FIG. 5 includes a variable gain low noise amplifier LNA as the variable gain amplifier 1, a frequency mixer MIX and a frequency selection filter as the delay element 2. The received signal which is a high frequency signal from the outside is amplified by the variable gain low noise amplifier LNA and frequency-converted into a low frequency signal by the frequency mixer MIX. Moreover, a signal in a desired frequency band is obtained by the frequency selection filter. The response time is increased by interposing these delay elements.

In the present invention, since the gain control potential generator is controlled by the timing generator, the gain control potential can be stabilized at a desired level in a short time even in the negative feedback type having a long response time. Also, when the timing signal is low, the gain control potential generator is stopped, and the gain control potential generator holds the gain control potential when the timing signal changes from high to low, so that the gain control potential is stable, Does not oscillate. (Second Embodiment) The gain control amplifier according to the second embodiment presets a period in which the timing signal output from the timing generator in the first embodiment is high. On the other hand, the timing generator according to the second embodiment performs control to lengthen or shorten the high period of the timing signal according to the gain control potential output from the gain control potential generator.

FIG. 6 is a block diagram of a gain control amplifier according to the second embodiment. The gain control amplifier of the present embodiment is a variable gain amplifier 1 that amplifies the amplitude of a received signal.
An electric field strength detector 3 for detecting the amplitude of the received signal, and a comparator 4 for comparing the output of the detector with the reference potential Vref.
It comprises a gain control potential generator 5 for raising and lowering the gain control potential according to the positive / negative of the control signal, and a timing generator 6 for intermittently operating the gain control potential generator 5. The configuration different from that of the first embodiment is that the gain control potential, which is the output of the gain control potential generator 5, is supplied to the timing generator 6.

For example, assume that the output relationship between the gain control potential and the gain is as shown in FIG. When the gain change is insensitive to the change of the gain control potential (left side of the graph), the timing generator 6 lengthens the period in which the timing signal is high and is sensitive (right side of the graph). When it is, control is performed such that the period in which the timing signal is high is shortened.

In the present invention, since the gain control potential generator is controlled by the timing generator, the gain control potential can be stabilized at a desired level in a short time even in a negative feedback type having a long response time. Also, when the timing signal is low, the gain control potential generator is stopped, and the gain control potential generator holds the gain control potential when the timing signal changes from high to low, so that the gain control potential is stable, Does not oscillate.

Since the high period of the timing signal is adjusted according to the gain capability of the gain control potential generator, the gain control potential of a desired level can be obtained. (Third Embodiment) The gain control amplifier according to the third embodiment performs gain control by controlling the pump current according to the gain control potential output from the gain control potential generator. There is.

FIG. 8 is a block diagram of a gain control amplifier according to the third embodiment. The gain control amplifier of the present embodiment is a variable gain amplifier 1 that amplifies the amplitude of a received signal.
An electric field strength detector 3 for detecting the amplitude of the received signal, and a comparator 4 for comparing the output of the detector with the reference potential Vref.
It comprises a gain control potential generator 5 for raising and lowering the gain control potential according to the positive / negative of the control signal, and a timing generator 6 for intermittently operating the gain control potential generator 5. The configuration different from that of the first embodiment is that the gain control potential output from the gain control potential generator 5 is fed back and supplied to the gain control potential generator 5.

For example, assume that the output relationship between the gain control potential and the gain is as shown in FIG. Gain control potential generator 5
Shows that when the gain change is insensitive to the change of the gain control potential (left side of the graph), the amount of current flowing to the pump current is increased, and when it is in the sensitive range (right side of the graph), the current is increased. Control such as reducing the amount is performed.

FIG. 9 is a specific circuit diagram of the gain control potential generator 5 according to the third embodiment. The gain control potential generator 5 is composed of a charge pump circuit with a control terminal, the output of the gain control potential generator 5 is input to a newly provided current source control device, and the current source is variable.

In the gain control potential generator 5 of FIG. 9, a variable current source I3, a PMOS transistor, an NMOS transistor, and a variable current source I4 are connected in series between a node supplied with the external power supply voltage and the ground. An output signal of a NAND gate to which the inverted signal of the control signal of the comparator 4 and the timing signal of the timing generator 6 are input is supplied to the gate terminal of the PMOS transistor. Further, the comparator 4 is connected to the gate terminal of the NMOS transistor.
The output signal of the AND gate to which the control signal of 1) and the timing signal of the timing generator 6 are input is supplied.

Then, the PMOS transistor and the NMOS
The connection node (drain terminal node) of the transistor is
It is connected to the output node OUT. This output node O
The gain control potential is output from the UT. A capacitor C is connected between the output node OUT and the ground.

Further, a current source controller 7 is connected to the output node OUT. The current source control device 7 controls the variable current sources I3 and I4 according to the gain control potential.
If the gain control potential is small, the amount of current flowing through the variable current sources I3, I4 is increased, and if the gain control potential is large, the amount of current is reduced.

In the present invention, since the gain control potential generator is controlled by the timing generator, the gain control potential can be stabilized at a desired level in a short time even in a negative feedback type having a long response time. Also, when the timing signal is low, the gain control potential generator is stopped, and the gain control potential generator holds the gain control potential when the timing signal changes from high to low, so that the gain control potential is stable, Does not oscillate.

Since the amount of current flowing in the gain control potential generator is adjusted according to the gain capability of the gain control potential generator, it is possible to obtain the desired level of gain control potential in a short time. (Fourth Embodiment) The gain control amplifier according to the fourth embodiment controls the gain time (the period when the timing signal output from the timing generator is high) by the timing control device.

FIG. 10 is a block diagram of a gain control amplifier according to the fourth embodiment. The gain control amplifier of this embodiment has a timing control device 8 in addition to the first embodiment.

The timing controller 8 controls the period during which the timing signal of the timing generator 6 is high. The information of the device (transmitting side) that sends the received signal, for example, the information at the time of the previous communication is stored in the timing control device or in the memory, and the timing signal of the timing generator 6 is high based on this. Adjust the period.

In the present invention, since the gain control potential generator is controlled by the timing generator, the gain control potential can be stabilized at a desired level in a short time even in a negative feedback type having a long response time. Also, when the timing signal is low, the gain control potential generator is stopped, and the gain control potential generator holds the gain control potential when the timing signal changes from high to low, so that the gain control potential is stable, Does not oscillate.

Even if the device on the transmitting side that sends the received signal is different, the period in which the timing signal is high is adjusted according to the information on the transmitting side, so that the gain control potential can be converged in a short time. it can.

The timing control device may control the current source control device 7 of FIG. 9 shown in the third embodiment. In this case, the amount of current is adjusted based on information on the transmitting side. As a result, the amount of current flowing in the gain control potential generator is adjusted according to the information on the transmission side even if the device on the transmission side that sends the received signal is different, so that the gain control potential can be converged in a short time. You can (Fifth Embodiment) FIG. 11 is a block diagram of a gain control amplifier according to the fifth embodiment. The gain control amplifier of the present embodiment compares the variable gain amplifier 1 for amplifying the amplitude of the received signal, the electric field strength detector 3 for detecting the amplitude of the received signal, the output of the detector and the reference potential Vref, and 2
Comparator 4 that outputs two control signals, and gain control potential generator 5 that raises or lowers the gain control potential according to whether the control signal is positive or negative
Consists of.

The comparator 4 has two control signals (UP signal,
DN signal) is output. FIG. 12 shows a comparator input potential difference and a control signal (UP signal, DN signal) in the present embodiment.
It is a figure which shows the relationship of. If the difference between the potential detected by the electric field intensity detector 3 and the reference potential Vref is smaller than -ΔV, the UP signal becomes high and the DN signal becomes low. On the other hand, if the difference between the detected potential and the reference potential Vref is larger than + ΔV, the UP signal becomes low and the DN signal becomes high. If the input potential difference of the comparator 4 is within ± ΔV, both the UP signal and the DN signal are low.

The gain control potential generator 5 changes the gain control potential according to the control signal from the comparator 4. If the UP signal is high and the DN signal is low, the gain control potential is raised (first mode). If the UP signal is low and the DN signal is high, the gain control potential is lowered (first mode). If both the UP signal and the DN signal are low, the gain control potential generator 5 stops operating and the UP signal or DN signal is stopped.
Maintain the gain control potential when the signal is high (second
Mode).

Next, the operation of this embodiment will be described. The received signal is received and amplified by the variable gain amplifier 1. Then, the received signal is supplied to the electric field intensity detector 3. Although not shown, the output of the variable gain amplifier 1 may be supplied to the electric field intensity detector 3 via a delay element as in the first embodiment.

The electric field strength detector 3 detects the amplitude of the received signal. Then, the comparator 4 compares the amplitude (potential) detected by the electric field strength detector 3 with the reference potential Vref.

When the detected amplitude is lower than the desired level range, that is, Vref-ΔV or less, the UP signal output from the comparator 4 is high and the DN signal is low. On the other hand, when it is higher than the desired level range, that is, when it is Vref + ΔV or more, the UP signal is low
The signal goes high. Also, if within the desired level,
That is, when it is within Vref ± ΔV, UP signal and DN
Both signals go low.

Then, the gain control potential generator 5 operates according to the UP signal and the DN signal. UP signal is high, DN
When the signal is low, the gain control potential generator 5 raises the gain control potential on the assumption that the potential of the received signal is lower than the desired level range. When the UP signal is low and the DN signal is high, it is determined that the potential is higher than the desired level range, and the gain control potential generator 5 lowers the gain control potential. When both the UP signal and the DN signal are low, it is within the range of the desired level, and the gain control potential generator 5 stops its operation.

The gain control potential when the operation of the gain control potential generator 5 is stopped is the gain control potential generator when the UP signal changes from high to low or when the DN signal changes from high to low. 5 is fixed at the gain control potential when the UP signal or the DN signal is high. UP
While the signal and the DN signal are both low, the gain control potential generator 5 stops operating and keeps its value.

In the present invention, the gain control potential generator is controlled according to the control signal of the comparator. Therefore, when the gain control potential is not at the desired level, the gain control potential generator is operated to operate the gain control potential. Is within the desired level range, that is, when both the UP signal and the DN signal become low, the operation of the gain control potential generator can be stopped and the gain control potential of the desired level can be obtained.

When the gain control potential generator is stopped, the gain control potential generator outputs the gain control potential when the UP signal changes from high to low or when the DN signal changes from high to low. Since it is held, the gain control potential can be stabilized. (Sixth Embodiment) FIG. 13 is a block diagram of a gain control amplifier according to the sixth embodiment. The gain control amplifier of the present embodiment compares a variable gain amplifier 1 that amplifies the amplitude of the received signal, an electric field intensity detector 3 that detects the amplitude of the received signal, and the output of the detector with the reference potential Vref−ΔV. Comparator 4-1 and the potential of the received signal and the reference potential Vre
A comparator 4-2 for comparing f + ΔV and a gain control potential generator 5 for raising / lowering the gain control potential according to the positive / negative of the control signal.
Consists of.

In this embodiment, two comparators are arranged in parallel. The comparator 4-1 detects the detected potential and the reference potential Vr.
ef + ΔV are compared and the UP signal, which is a control signal, is output. The other comparator 4-2 compares the detected potential with the reference potential Vref-ΔV and outputs a DN signal which is a control signal.

The gain control potential generator 5 includes two comparators 4
Control is performed according to the UP signal and DN signal output from -1, 4-2. When the detected potential falls within the range of Vref ± ΔV, the output potential of the gain control potential generator 5 does not change. The operation of the gain control potential generator 5 is the same as that of FIG. 12 shown in the fifth embodiment.

In the present invention, the gain control potential generator is controlled according to the control signal of the comparator. Therefore, when the gain control potential is not at the desired level, the gain control potential generator is operated to operate the gain control potential. Is within the desired level range, that is, when both the UP signal and the DN signal become low, the operation of the gain control potential generator can be stopped and the gain control potential of the desired level can be obtained.

When the gain control potential generator is stopped, the gain control potential generator outputs the gain control potential when the UP signal changes from high to low or when the DN signal changes from high to low. Since it is held, the gain control potential can be stabilized. (Seventh Embodiment) FIG. 14 is a block diagram of a gain control amplifier according to the seventh embodiment. In addition to the fifth embodiment, the gain control amplifier of the present embodiment has a timing generator 6 and controls the gain control potential generator 5.

Since this embodiment uses feedback control, a delay occurs in the received signal. Therefore, the reception signal received by the variable gain amplifier 1 and the reception signal controlled by the gain control potential generator 5 may be out of timing.

For example, it is assumed that the gain control potential generator 5 receives the control signal generated based on the received signal and controls the gain control potential to increase. This gain control potential is supplied to the variable gain amplifier 1. However, due to the delay, the received signal received by the variable gain amplifier 1 is different from the gain-controlled received signal. Therefore, the reception signal received by the variable gain amplifier 1 receives the increased gain control potential, and may be larger than the desired level range. Then, with respect to the received signal which becomes larger than the range of the desired level, the gain control potential generator 5 again controls to lower the gain control potential. This control is repeated, and the gain control potential may not converge and may oscillate.

Therefore, in this embodiment, the timing generator 6 controls the gain control potential generator 5. The gain control potential generator 5 is operated for a fixed time and then stopped. Since the oscillation occurs within the range Vref ± ΔV of the almost desired level, even if the gain control potential generator 5 is stopped, the gain control potential of the desired level or a level close thereto can be obtained. Further, the oscillation can be stopped.

Even if the sixth embodiment has a timing generator and the gain control potential generator 5 is controlled, the same effect can be obtained.

Although not shown, the sixth and seventh
Also in the embodiment, the output signal of the variable gain amplifier may be supplied to the electric field intensity detector via the delay element.

The period in which the timing signal of the timing generator 6 in the seventh embodiment is high is set to the second
Alternatively, similarly to the fourth embodiment, the gain control potential of the gain control potential generator or the timing control device may be used for control.

Further, also in the fifth to seventh embodiments, the amount of current of the gain control potential generator may be adjusted as in the third embodiment.

Of course, various modifications can be made without departing from the scope of the invention.

[0064]

According to the present invention, since the gain control potential generator is controlled by the timing generator, the gain control potential can be stabilized at a desired level in a short time even in the case of the negative feedback type having a large response time. it can. Also, when the timing signal is low, the gain control potential generator is stopped, and the gain control potential generator holds the gain control potential when the timing signal changes from high to low, so that the gain control potential is stable, Does not oscillate.

In addition, since the high level of the timing signal or the amount of current flowing in the gain control potential generator is adjusted according to the gain capability of the gain control potential generator, the gain of a desired level can be obtained in a short time. A control potential can be obtained.

Further, since the gain control potential generator is controlled according to the control signal of the comparator, the gain control potential generator is operated when the gain control potential is not at the desired level.
When the gain control potential is within the desired level range, that is, U
When both the P signal and the DN signal become low, the operation of the gain control potential generator can be stopped and the gain control potential of a desired level can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a gain control amplifier according to a first embodiment.

FIG. 2 is an operation timing chart diagram in the first embodiment.

FIG. 3 is a specific circuit diagram of the gain control potential generator according to the first embodiment.

FIG. 4 is a diagram specifically showing a delay element according to the first embodiment.

FIG. 5 is a diagram specifically showing the delay element according to the first embodiment.

FIG. 6 is a block diagram of a gain control amplifier according to a second embodiment.

FIG. 7 is a diagram showing an output relationship between a gain control potential and a gain.

FIG. 8 is a block diagram of a gain control amplifier according to a third embodiment.

FIG. 9 is a specific circuit diagram of the gain control potential generator according to the third embodiment.

FIG. 10 is a block diagram of a gain control amplifier according to a fourth embodiment.

FIG. 11 is a block diagram of a gain control amplifier according to a fifth embodiment.

FIG. 12 is a diagram showing a relationship between a comparator input potential difference and a control signal.

FIG. 13 is a block diagram of a gain control amplifier according to a sixth embodiment.

FIG. 14 is a block diagram of a gain control amplifier according to a seventh embodiment.

FIG. 15 is an operation timing chart diagram in the seventh embodiment.

FIG. 16 is a block diagram of a conventional gain control amplifier.

[Explanation of symbols]

1 ... Variable gain amplifier 2 ... Delay element 3 ... Electric field strength detector 4,4-1,4-2 ... Comparator 5 ... Gain control potential generator 6 ... Timing generator 7 ... Current source control device 8 ... Timing control device

Claims (21)

[Claims] 1. A variable gain amplifier for amplifying the amplitude of a received signal, an electric field strength detector for detecting the amplitude of a signal according to the output signal of the variable gain amplifier, and an amplitude output by the electric field strength detector. A comparator for comparing reference potentials, and generating a gain control potential according to a control signal of the comparator,
A gain control potential generator for supplying the variable gain amplifier; and a timing generator for supplying a timing signal to the gain control potential generator, wherein the gain control potential generator provides the timing signal and the control signal. Accordingly, the gain control amplifier has a first mode for outputting high or low, and a second mode for keeping the output potential constant according to the timing signal. 2. The second mode of the gain control potential generator is characterized in that the gain control potential is held when the timing signal changes from high to low while the timing signal is low. The gain control amplifier according to claim 1. 3. The gain control amplifier according to claim 1, wherein the timing generator outputs a timing signal which is high for a certain period of time. 4. The timing generator receives a gain control potential from the gain control potential generator and controls the timing signal.
A gain control amplifier according to claim 1. 5. The timing generator lengthens a high period of the timing signal when the gain control potential is small, and shortens a high period of the timing signal when the gain control potential is large. 5. The gain control amplifier according to claim 4, wherein: 6. The gain control amplifier according to claim 1, further comprising: a timing control device that controls a timing signal of the timing generator based on information on a transmission side that transmits the reception signal. 7. The gain control potential generator has a first constant current source connected to an external power source, a source terminal connected to the first constant current source, and a gate terminal inverted signal of the control signal. And the PMO to which the output signal of the NAND gate to which the timing signal is supplied is supplied.
An S transistor, an NMOS transistor whose drain terminal is connected to the drain terminal of the PMOS transistor, and an output signal of an AND gate whose gate terminal is supplied with the control signal and the timing signal; and a source terminal of the NMOS transistor. 7. The gain control amplifier according to claim 1, further comprising a second constant current source connected between the ground and a ground. 8. The gain control amplifier according to claim 1, wherein the gain control potential generator controls a current amount based on the gain control potential which is an output. 9. The gain control potential generator increases the amount of current when the gain control potential is small, and decreases the amount of current when the gain control potential is large. A gain control amplifier as described. 10. The gain control potential generator has a first variable current source connected to an external power source, a source terminal connected to the first variable current source, and a gate terminal inverted signal of the control signal. And the PM to which the output signal of the NAND gate to which the timing signal is supplied is supplied
An OS transistor and a drain terminal connected to the PMOS transistor,
An NMOS transistor having a gate terminal supplied with the output signal of the AND gate having the control signal and the timing signal supplied thereto, a second variable current source connected between the source terminal of the NMOS transistor and the ground, and the PMOS. A current source control device that is connected to a connection terminal of a transistor and an NMOS transistor and controls the amount of current flowing through the first and second variable current sources based on the gain control potential that is an output. The gain control amplifier according to claim 8 or 9. 11. The gain control potential generator further comprises a timing control device that controls the current source control device based on information on a transmission side that transmits the reception signal. 10. The gain control amplifier according to item 10. 12. A variable gain amplifier for amplifying the amplitude of a received signal, an electric field strength detector for detecting the amplitude of a signal according to the output signal of the variable gain amplifier, and a potential output by the electric field strength detector. A comparator for comparing reference potentials to generate first and second control signals, and a gain control potential for generating a gain control potential according to the first and second control signals and supplying the gain control potential to the variable gain amplifier. A gain control amplifier, comprising: a generator. 13. A variable gain amplifier for amplifying the amplitude of a received signal, an electric field strength detector for detecting the amplitude of a signal according to the output signal of the variable gain amplifier, and a potential output by the electric field strength detector. A first comparator that compares the first reference potential and generates a first control signal, compares the amplitude detected by the electric field intensity detector with the second reference potential, and outputs the second control signal. A gain comprising: a second comparator that generates the gain control potential and a gain control potential generator that generates a gain control potential according to the first and second control signals and supplies the gain control potential to the variable gain amplifier. Control amplifier. 14. The gain control potential generator operates to increase the gain when the first control signal is high, and lowers the gain when the second control signal is high. 14. The gain control amplifier according to claim 12, wherein the output potential is made constant when both the first and second control signals are low. 15. The gain control potential generator includes a second control when the first and second control signals are both low, when the first control signal changes from high to low, or a second control. The gain control amplifier according to claim 14, which holds a gain control potential when a signal changes from high to low. 16. The gain control amplifier according to claim 12, further comprising a timing generator that supplies a timing signal to the gain control potential generator. 17. The gain control potential generator is configured to output a high mode or a low mode according to the timing signal and the first and second control signals, and output according to the timing signal. The gain control amplifier according to claim 16, which has a second mode in which the potential is constant. 18. A second mode of the gain control potential generator is characterized in that the gain control potential when the timing signal changes from high to low is held during a period in which the timing signal is low. The gain control amplifier according to claim 17. 19. The gain control amplifier according to claim 1, wherein the output signal of the variable gain amplifier is supplied to the electric field intensity detector via a delay element. . 20. The gain control amplifier according to claim 19, wherein the delay element comprises a frequency mixer. 21. The gain control amplifier according to claim 19, wherein the delay element comprises a frequency mixer and a frequency filter.