JP2003017569A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a normal semiconductor integrated circuit chip except for a capacitor breaking insulation of a gate oxidation film cannot be relieved. SOLUTION: Separation circuits 4, 5, 6 being in a continuity state or a non- continuity state in wiring at the side of a power source 50 or GND 60 securing decoupling capacities 1, 2, 3 are provided, the decoupling capacities 1, 2, 3 judge quality by operation from a tester during a wafer test process of products, and inferiority can eliminate leak current due to the decoupling capacity even for the decoupling capacity which has gate oxidation film short-circuiting by invalidating the decoupling capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of repairing a normal semiconductor integrated circuit chip other than a capacitor in which insulation of a gate oxide film is destroyed.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing the structure of a capacitor formed of a gate oxide film in a semiconductor integrated circuit chip according to the prior art. In FIG. 5, 1, 2 and 3 are individual capacitors, 50 is a power supply, and 60 is GND.
(Ground). Normally, power supply-GND (ground)
The capacitors having a function as a decoupling capacitor arranged between them are arranged in such a dispersed manner because of layout convenience in the semiconductor integrated circuit chip.

Next, the operation will be described. Capacitors 1, 2 and 3 shown in FIG. 5 are decoupling capacitors arranged between the power supply and GND in order to secure noise countermeasures and operation stability in the microcomputer system. The capacitor secures the capacity by a thin gate oxide film which is an insulating film.

However, due to manufacturing defects in the process,
Dielectric breakdown may occur due to the presence of foreign matter in the gate oxide film, and a leak path may flow between the power supply and GND.

As a result of the process defect, when any one of the capacitors 1, 2 and 3 operates, but the current value exceeds the value specified as the standard in the product and test process. , It is usually discarded as a defective product.

[0006]

Since the conventional semiconductor integrated circuit is configured as described above, the gate of the semiconductor integrated circuit chip that is discarded as such a defective product is the gate causing the defect. As for normal capacitors other than capacitors whose oxide film insulation is destroyed, there is a problem that such semiconductor integrated circuit chips will also be discarded, even if they can be commercialized if there is no cause for their defects. It was

The present invention is intended to solve the above problems and provides a semiconductor integrated circuit capable of relieving a normal semiconductor integrated circuit chip other than a capacitor in which the insulation of the gate oxide film is destroyed. The purpose is to

[0008]

A semiconductor integrated circuit according to the present invention is provided with a decoupling circuit which is in a conducting state and a non-conducting state in a power source or a GND side wiring which secures the decoupling capacitance, and the decoupling capacitance is During the wafer test process of the product, it is judged whether the product is good or bad by the operation from the tester and invalidates the capacity for the bad.

In the semiconductor integrated circuit according to the present invention, the decoupling circuit has a P-channel transistor and a gate control circuit for supplying a control signal to the gate of the P-channel transistor, and the decoupling circuit is responsive to the value of the control signal of the gate control circuit. The P-channel transistor is made conductive or non-conductive to control the conductive or non-conductive state of the disconnection circuit.

In the semiconductor integrated circuit according to the present invention, the disconnecting circuit has a fuse and an ammeter for outputting a signal representing the value of the current flowing through the fuse, and the fuse is connected and disconnected. By making either of them, the conductive state and the non-conductive state of the disconnection circuit are controlled.

In the semiconductor integrated circuit according to the present invention, the gate control circuit comprises a non-volatile memory, the value stored in the non-volatile memory is output as a control signal for the gate control circuit, and the non-volatile memory of the non-volatile memory is used when a test is performed. A mode is provided in which the value can be switched and the current value can be measured.

In the semiconductor integrated circuit according to the present invention, the gate control circuit comprises an external input signal receiving circuit provided with a fuse, and when the fuse is cut off, the P-channel transistor becomes non-conductive and the fuse is connected. , The P-channel transistor is made conductive or non-conductive depending on the value of the external input signal, and by specifying the P-channel transistor to be made conductive by the external input signal, which decoupling is performed. It is to determine whether the current flowing through the ring capacitance is abnormal.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a diagram showing a configuration of a first embodiment according to the present invention. In FIG. 1, reference numerals 1, 2, and 3 are individual capacitors that form decoupling capacitances, and reference numerals 4, 5, and 6 are connected to the capacitors 1, 2, and 3, respectively. It is a disconnection circuit having means for disconnecting the corresponding capacitor. 50 is a power supply and 60 is a GND (ground).

Next, the operation will be described. The capacitors 1, 2, and 3 that form the decoupling capacitance are designed in a chip and a test so that a good / defective judgment can be made by an operation from a tester during a wafer test process of a product. After the chip design and the test design, a wafer test process is performed, and a capacitor determined to be defective in the wafer test process is a disconnection circuit (4, 4) connected to the defective capacitor as a defective capacitor.
5,6) is enabled and the defective capacitor is the power supply-GDN.
It is separated from and invalidated.

As described above, in the semiconductor integrated circuit according to the first embodiment, the gate oxide film is used as the dielectric material for the power supply-GND.
In a semiconductor integrated circuit having decoupling capacitors 1, 2, and 3 built in between (ground), a conducting state and a non-conducting state in a wiring on the power supply 50 side or the GND 60 side that secures the decoupling capacitances 1, 2, and 3. The decoupling capacitors 1, 2, and 3 are equipped with the decoupling circuits 4, 5, and 6 to judge whether the decoupling capacitors 1, 2, and 3 are good or bad by the operation from the tester during the wafer test process of the product, and invalidate the capacity for the bad. It is possible to eliminate the leak current due to the decoupling capacitance even for the decoupling capacitance having the gate oxide film short circuit by making it invalid.

As described above, according to the first embodiment, one or more of the capacitors 1, 2, and 3 are determined to be defective capacitors because the current value increases due to a defective gate oxide film or the like. In this case, by disconnecting the disconnecting circuit, the defective capacitor is disconnected and invalidated, so that the semiconductor integrated circuit chip can be treated as a normal product and the yield of the product can be improved. Is obtained.

Embodiment 2. FIG. 2 is a diagram showing a disconnection circuit using a P-channel transistor according to the second embodiment of the present invention. In FIG. 2, 4 is a disconnecting circuit, and 7 is a P-channel transistor whose source side terminal is connected to the power supply 50 and whose drain side terminal 9 is connected to the capacitor of FIG. 8 is a flash memory whose output terminal is connected to the gate of the P-channel transistor 7 and constitutes a non-volatile memory, 9 is a drain-side terminal of the P-channel transistor 7, and this drain-side terminal 9
Are connected to the capacitor of FIG. 50 is a power supply.

In the second embodiment, the disconnecting circuit 4
Has a P-channel transistor 7 and a gate control circuit including a flash memory 8 for supplying a control signal to the gate of the P-channel transistor 7.

Further, in the second embodiment, the P-channel transistor 7 may be replaced with an N-channel transistor to form a gate control circuit.

Next, the operation will be described. The value of the flash memory 8 can be set to either 0 or 1 if the internal circuit of the semiconductor integrated circuit incorporating this flash memory operates. The value of the flash memory 8 is input to the gate of the P-channel transistor 7 as a control signal.

Therefore, a step of changing the value of the flash memory 8 is added so that the value of the flash memory 8 can be changed during the test step.

The flow of the test process is as follows.
First, the value of all the flash memories 8 is set to "L" to make the P-channel transistor 7 conductive and the disconnection circuit 4 invalid (all capacitors effective), and the semiconductor integrated circuit chip The current characteristic of is evaluated. At that time, if it is not an abnormal value, it is directly sent to the next process test.

If there is a defect in the current characteristic evaluation process, the value of the flash memory 8 is switched to "H" for each of the capacitors 1, 2 and 3, and the current value is measured. Confirm whether to enter. This corresponds to finding out which one of the capacitors 1, 2, and 3 has the abnormal current.

Thus, of the capacitors 1, 2, 3
After identifying which one is defective, the flash memory 8 connected to the defective capacitor is set to “H” to make the P-channel transistor 7 non-conductive to enable the disconnection circuit 4 (as a capacitor). (Invalid state) and proceed to the next step.

In order to ensure the quality of the product, it is necessary to determine in advance how many capacitors may be disabled.

As described above, the semiconductor integrated circuit of the second embodiment is the same as the semiconductor integrated circuit of the first embodiment.
The disconnection circuit 4 has a P-channel transistor 7 and a gate control circuit (nonvolatile memory 8) that supplies a control signal to the gate of the P-channel transistor 7, and the P-channel transistor is provided in accordance with the value of the control signal of the gate control circuit. The conductive state and the non-conductive state of the disconnection circuit 4 are controlled by setting the transistor 7 to the conductive state or the non-conductive state.

Further, in the semiconductor integrated circuit of the second embodiment, the gate control circuit is composed of the nonvolatile memory 8,
The value stored in the non-volatile memory 8 is output as a control signal of the gate control circuit, and the value of the non-volatile memory 8 is switched at the time of testing to provide a mode in which the current value can be measured.

As described above, according to the second embodiment, the decoupling circuit includes the P-channel transistor and the gate control circuit that supplies the control signal to the gate of the P-channel transistor. Since the P-channel transistor is turned on or off depending on the value of, the conduction and non-conduction states of the disconnection circuit are controlled. When the current value of one or a plurality of capacitors increases due to a defective gate oxide film or the like, it is possible to obtain the effect of being able to select the capacitors and make them non-defective in the test process.

Further, according to the second embodiment, the gate control circuit is composed of a non-volatile memory, and the value stored in the non-volatile memory is output as a control signal of the gate control circuit, so that the non-volatile memory is used when performing a test. Since the mode in which the current value can be measured by switching the memory value is provided, when the current value of one or more of the capacitors 1, 2 and 3 increases due to a defective gate oxide film, etc., in the test process, It is possible to obtain the effect that the product can be made good at the same time as the selection.

Embodiment 3. 3 is a diagram showing a disconnecting circuit using a fuse according to a third embodiment of the present invention. In FIG. 3, 4 is a disconnecting circuit, and 10 is a fuse whose one terminal is connected to the power source 50 and whose other terminal is connected to the ammeter 11. Reference numeral 11 denotes an ammeter such as a sense amplifier, one terminal of which is connected to the fuse 10 and the other terminal, which is a low-voltage side terminal 12, is shown in FIG.
Connected to the capacitor. A determination signal 13 is output from the ammeter 11, and “H” and “L” are inverted according to the current flowing through the ammeter 11. Reference numeral 12 is a low-voltage side terminal of the ammeter 11, and this low-voltage side terminal 12 is connected to the capacitor of FIG. 50 is a power supply.

In the third embodiment, the disconnecting circuit 4
Has a fuse 10 and an ammeter 11 that outputs a determination signal 13 representing the value of the current flowing through the fuse 10.

Next, the operation will be described. The ammeter 11 is a circuit that determines whether or not a current is flowing through itself. Since the ammeter 11 is only connected to the capacitors 1, 2 and 3, if the capacitors 1, 2 and 3 are normal, no current will flow after the power supply potential is stabilized after the power is turned on.

Therefore, if a current constantly flows through the ammeter 11, it can be determined that the product is defective.

When current is flowing through the ammeter 11,
The information is output as the determination signal 13 of the ammeter 11 as digital data, and this data is set at the time of the test so that it can be read by the tester. The means is
The determination signal 13 of the ammeter 11 is directly output to the test PAD (pad: pad), or written in the register so that the written data can be read.

The test flow is as follows. Initially, all the fuses 10 are connected, so that all the capacitors are valid. In this state, the current characteristics of the semiconductor integrated circuit chip are evaluated. At that time,
If it is not an abnormal value, it is sent to the test of the next process as it is.

Therefore, if there is a defect, each ammeter 11
The determination signal 13 of No. 1 is confirmed by a tester, and the capacitor in which the determination signal 13 of the ammeter 11 is abnormal, that is, the capacitor through which the current is flowing is identified. Thus, the capacitor 1,
After identifying which of the capacitors 2 and 3 is defective, the fuse 10 connected to the capacitor is cut off.

When there are a plurality of fuses to be blown, the fuses 10 may be blown together.

Thus, in a state where no abnormal current flows through the ammeter 11, that is, in a state where the defective capacitor is invalidated,
Go to the next step. Also, in order to secure the quality of the product, it is necessary to determine in advance how many capacitors may be disabled.

As described above, the semiconductor integrated circuit of the third embodiment is the same as the semiconductor integrated circuit of the first embodiment.
The disconnection circuit 4 has the fuse 10 and the ammeter 11 that outputs the signal 13 representing the value of the current flowing through the fuse 10, and brings the fuse 10 into either the connected state or the disconnected state. The conduction state and the non-conduction state of the disconnection circuit 4 are controlled.

As described above, according to the third embodiment, the disconnecting circuit has the fuse and the ammeter that outputs the signal indicating the value of the current flowing through the fuse, and the state in which the fuse is connected and Since the conducting state and the non-conducting state of the disconnection circuit are controlled by making the circuit into any one of the disconnected states, the capacitors 1, 2, 3
When the current value of any one of the capacitors or a plurality of capacitors increases due to a defective gate oxide film or the like, it is possible to obtain the effect of being able to select the capacitors and to make them non-defective in the test process.

Fourth Embodiment Fourth Embodiment FIG. 4 is a diagram showing a disconnection circuit using a P-channel transistor and a fuse according to a fourth embodiment of the present invention. In FIG. 4, reference numeral 4 is a disconnecting circuit. 14 is a P-channel transistor,
The source side terminal is connected to the power supply 50, and the drain side terminal 15 is connected to the capacitor of FIG. Reference numeral 15 is a drain-side terminal of the P-channel transistor 14. 16
Is an inverter, the output terminal of which is connected to the gate of the P-channel transistor 14 and the input terminal of which is the inverter 17
Is connected to the output terminal of. Reference numeral 17 denotes an inverter, the output terminal of which is connected to the input terminal of the inverter 16 and the gate of the P-channel transistor 18, and the input terminal of which is connected to the drain-side terminal of the P-channel transistor 18 and the high-voltage side terminal of the fuse 19. There is.

Reference numeral 18 denotes a P-channel transistor, the source side terminal of which is connected to the power supply 50, the drain side terminal thereof is connected to the input terminal of the inverter 17, and the gate thereof is connected to the output terminal of the inverter 17. Reference numeral 19 is a fuse whose high-voltage side terminal is the P-channel transistor 2
1 is connected to the drain side terminal and the low voltage side terminal is N
It is connected to the source-side terminal of the channel transistor 20. 20 is an N-channel transistor, the source side terminal is connected to the low voltage side terminal of the fuse 19,
The drain side terminal is connected to the ground (GND), and the gate is connected to the output terminal of the NAND circuit 22.
21 is a P-channel transistor, the source side terminal is connected to the power supply 50, and the drain side terminal is the fuse 1
9 is connected to the terminal on the high voltage side, and the gate is connected to the output terminal of the NAND circuit 22.

A NAND circuit 22 has a test mode signal 23 input to one of two input terminals, a select signal 24 input to the other input terminal, and an N-channel transistor 20 and a P-channel output terminal. It is connected to the gate of the transistor 21. Reference numeral 23 is a test mode signal, and 24 is a select signal. It is assumed that the select signal 24 is directly connected to the PAD so that it can be input during the test. In addition, the terminal 15 on the drain side
Are connected to the capacitors 1, 2 and 3 of FIG. Fifty
Is a power source, and 60 is a GND (ground).

An external input signal receiving circuit 25 receives the test mode signal 23 and the select signal 24 as external input signals, and the NAND circuit 22, the P channel transistor 21, and the N channel transistor 20 are input.
, Fuse 19, P-channel transistor 18,
It is composed of an inverter 17 and an inverter 16.

In the fourth embodiment, the separation circuit 4
Includes a gate control circuit including an external input signal receiving circuit 25 including a fuse 19, and a P-channel transistor 14.

In the fourth embodiment, the P-channel transistor 14 may be replaced with an N-channel transistor to form a gate control circuit.

Next, the operation will be described. First, the case where the fuse 19 is connected will be described. The mode signal 23 is a signal set to be "L" during normal use. N when the mode signal 23 is "L"
Since the value of the output of the AND circuit 22 becomes "H" regardless of the value of the select signal 24, the P-channel transistor 2
1 becomes non-conductive, and N-channel transistor 20 becomes conductive.

Therefore, when the fuse 19 is connected, the terminal on the high voltage side of the fuse 19 becomes the ground potential, and the value of the signal input to the input terminal of the inverter 17 becomes "L". Then, the value of the output signal of the inverter 17 becomes "H", this output signal is input to the inverter 16, and the value of the output signal from the inverter 16 is "L".
Becomes Since the signal of the value “L” from the inverter 16 is input to the gate of the P-channel transistor 14,
The P-channel transistor 14 becomes conductive.

Therefore, when the fuse 19 is connected and the mode signal 23 is set to "L", the potential of the gate of the P-channel transistor 14 becomes L level, and the P-channel transistor 14 becomes conductive. .

Next, at the time of the test, the mode signal 23 is set to "H". When the mode signal 23 is "H", NA
The value of the output signal of the ND circuit 22 becomes "H" when the value of the select signal 24 is "L", and becomes "L" when the value of the select signal 24 is "H".

When the value of the select signal 24 is "L", N
Since the value of the output signal of the AND circuit 22 becomes "H", as in the case where the value of the output signal of the NAND circuit 22 becomes "H" when the value of the mode signal 23 described above is "L", P
The channel transistor 14 becomes non-conductive.

On the other hand, when the value of the select signal 24 is "H", the value of the output signal of the NAND circuit 22 becomes "L",
N-channel transistor 20 becomes non-conductive, and P-channel transistor 21 becomes conductive. Therefore, the high-voltage side terminal of the fuse 19 is connected to the power supply 50 via the P-channel transistor 21, and the potential of the high-voltage side terminal becomes “H”. The signal of the value “H” from the high voltage side terminal of the fuse 19 is input to the input terminal of the inverter 17, and as a result, the signal of the value “H” is output from the output terminal of the inverter 16, and the P-channel transistor Input to 14 gates. Thus, the P-channel transistor 14 whose gate is supplied with the signal of the value "H"
Becomes non-conductive.

As described above, in the test mode, the mode signal 23 is set to "H", the potentials of the gates of the P-channel transistor 21 and the N-channel transistor 20 change according to the value of the select signal 24, and the capacitor to be tested is changed. By setting the corresponding select signal 24 to "H", the potential of the gate of the P-channel transistor 14 corresponding to the capacitor can be set to "H". P-channel transistor 14 whose gate potential is "H"
It becomes possible to disconnect the capacitor connected to the drain side terminal 15 from the circuit.

Next, the case where the fuse 19 is blown will be described. When the fuse 19 is cut off, the high-voltage side terminal of the fuse 19 is connected to the N-channel transistor 2
It means that it is disconnected from the source side terminal of 0.
Therefore, the value of the output signal of the NAND circuit 22 is “H”.
When the N-channel transistor 20 becomes conductive and the P-channel transistor 21 becomes non-conductive, the high-voltage side terminal of the fuse 19 is disconnected from the source-side terminal of the N-channel transistor 20. The electric potential of the high voltage side terminal of the fuse 19 becomes equal to that of the power source 50.

On the other hand, when the value of the output signal of the NAND circuit 22 becomes "L", the N-channel transistor 20 becomes non-conductive and the P-channel transistor 21 becomes conductive, the terminal of the fuse 19 on the high voltage side. Is electrically connected to the power supply 50 through the P-channel transistor, the potential of the high-voltage side terminal of the fuse 19 is equal to the power-source voltage.

Thus, when the fuse 19 is blown, the gate potential of the P-channel transistor 14 becomes "H" regardless of the values of the mode signal 23 and the select signal 24, and the P-channel transistor 14 is non-conductive. It becomes a state.

The test flow is as follows. Initially, all the fuses are connected, so that all the capacitors are valid. At this time,
The mode signal 23 is not set to "H" that designates the test mode, but the mode signal 23 is set to "L" to activate all the capacitors and the current characteristics of the semiconductor integrated circuit chip are evaluated. At that time, if there is no abnormality, send it to the test of the next process as it is.

In the current characteristic evaluation, when the capacitors are defective, the mode signal 23 is set to "H" and the select signals 24 corresponding to the capacitors 1, 2 and 3 are sequentially set to "H" to disable each capacitor. It will turn into. If the invalid current disappears due to the invalidation of the capacitor, it is specified that the invalidated capacitor is defective.

After identifying which of the capacitors 1, 2, and 3 is defective in this way, the fuse 19 corresponding to the capacitor is cut off. When there are a plurality of fuses to be blown, the fuses may be blown together.

Thus, in a state where no abnormal current flows through the ammeter 11, that is, in a state where the defective capacitor is invalidated,
Go to the next step. Also, in order to secure the quality of the product, it is necessary to determine in advance how many capacitors may be disabled. For example, in the case where the current value of the capacitor 1 is abnormal in FIG. 5, even if the capacitor 1 is cut, if the minimum capacity between the power supply and the GND that is desired to be secured in advance can be secured, by cutting only the capacitor 1 The yield can be improved.

As described above, the semiconductor integrated circuit of the fourth embodiment is the same as the semiconductor integrated circuit of the first embodiment.
The disconnecting circuit 4 includes a P-channel transistor 14 and a P-channel transistor 14.
A gate control circuit (external input signal receiving circuit 25) for supplying a control signal to the gate of the channel transistor 14, and the P-channel transistor 14 is in a conductive state or a non-conductive state according to the value of the control signal of the gate control circuit. By setting either of the above, the conducting state and the non-conducting state of the disconnection circuit 4 are controlled.

In the semiconductor integrated circuit according to the fourth embodiment, the gate control circuit is composed of the external input signal receiving circuit 25 having the fuse 19, and when the fuse 19 is cut off, the P-channel transistor 14 is non-conductive. When the fuse 19 is connected, the P-channel transistor 14 is turned on or off depending on the value of the external input signals 23 and 24, and turned on by the external input signals 23 and 24. By designating the P-channel transistor 14 to be turned on, it is possible to determine which decoupling capacitance the current flowing through is abnormal.

As described above, according to the fourth embodiment, the decoupling circuit has the P-channel transistor and the gate control circuit for supplying the control signal to the gate of the P-channel transistor. Since the P-channel transistor is turned on or off depending on the value of, the conduction and non-conduction states of the disconnection circuit are controlled. When the current value of one or a plurality of capacitors increases due to a defective gate oxide film or the like, it is possible to obtain the effect of being able to select the capacitors and make them non-defective in the test process.

According to the fourth embodiment, the gate control circuit comprises an external input signal receiving circuit having a fuse. When the fuse is blown, the P-channel transistor becomes non-conductive and the fuse is connected. The P-channel transistor is turned on or off depending on the value of the external input signal,
By designating the P-channel transistor that is made conductive by the external input signal, it is possible to determine which decoupling capacitor the current flowing is abnormal. Therefore, one of the capacitors 1, 2, 3 or When the current value of the plurality of capacitors increases due to a defective gate oxide film or the like, it is possible to obtain the effect of being able to perform the screening as well as the non-defective product in the test process.

[0065]

As described above, according to the present invention, when one or more of the capacitors are judged to be defective due to an increase in current value due to a defective gate oxide film or the like, a disconnection circuit is provided. By cutting
Since the defective capacitor is separated and invalidated, the semiconductor integrated circuit chip can be treated as a normal product, and the yield of products can be improved.

According to the present invention, the decoupling circuit has the P-channel transistor and the gate control circuit for supplying the control signal to the gate of the P-channel transistor, and the P-channel transistor is provided in accordance with the value of the control signal of the gate control circuit. Since the disconnection circuit is configured to control the conduction state and the non-conduction state depending on whether it is in the conduction state or the non-conduction state, one or more of the capacitors may have a defective gate oxide film or the like. When the current value increases due to, in the test process, there is an effect that the product can be selected and the product can be made good at the same time.

According to the present invention, the disconnecting circuit has the fuse and the ammeter for outputting the signal indicating the value of the current flowing through the fuse, and the fuse is connected to either the connected state or the disconnected state. The disconnection circuit is configured to control the conduction state and the non-conduction state by performing the test process when the current value of any one or more of the capacitors increases due to a defective gate oxide film. In the above, there is an effect that the product can be made good at the same time as the selection.

According to the present invention, the gate control circuit is composed of the non-volatile memory, and the value stored in the non-volatile memory is output as the control signal of the gate control circuit, and the value of the non-volatile memory is switched when performing the test. Therefore, if one or more of the capacitors have an increased current value due to a defective gate oxide film, etc., in the test process,
There is an effect that a good product can be obtained simultaneously with the selection.

According to the present invention, the gate control circuit is composed of the external input signal receiving circuit provided with the fuse, and when the fuse is blown, the P-channel transistor becomes non-conductive and the fuse is connected. when,
The P-channel transistor is made conductive or non-conductive depending on the value of the external input signal, and by designating the P-channel transistor to be made conductive by the external input signal, the current flowing in which decoupling capacitor is changed. Since it is determined whether it is abnormal, if one or more of the capacitors have an increased current value due to a defective gate oxide film, etc., in the test process, the selection is performed and the product is made good at the same time. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a diagram showing a capacitor configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a disconnection circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a disconnecting circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a disconnection circuit of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a capacitor configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1,2,3 capacitors, 4,5,6 disconnection circuit,
7 P-channel transistor, 8 Non-volatile memory, 9
D-side terminal of P-channel transistor, 10
Fuse, 11 ammeter, 12 ammeter low voltage side terminal, 13 judgment signal, 14 P-channel transistor,
15 P-channel transistor drain side terminal, 1
6,17 Inverter, 18 P-channel transistor, 19 fuse, 20 N-channel transistor, 2
1 P-channel transistor, 22 NAND circuit, 2
3 Test mode signal, 24 select signal, 25 external input signal receiving circuit, 50 power supply, 60 ground.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2G132 AH07 AK11                 4M106 AA01 AA08 AB08 AC08 BA20                       CA04 CA11 CA14                 5F038 AC03 AC20 AV15 AV17 CD02                       CD03 DF04 DF05 DT12 DT15                       EZ20                 5F064 BB05 BB07 BB09 BB12 BB31                       CC23 DD44 FF27 FF36

Claims (5)

[Claims] 1. A power supply-GN using a gate oxide film as a dielectric.
In a semiconductor integrated circuit having a built-in decoupling capacitance between D (ground), a power supply or GN that secures the decoupling capacitance.
The D side wiring is equipped with a disconnecting circuit that makes it conductive and non-conductive. The decoupling capacitance is judged to be good or bad by the operation from the tester during the wafer test process of the product, and the decoupling capacitance is invalid for the defect. A semiconductor integrated circuit characterized by the following: 2. The disconnection circuit has a P-channel transistor and a gate control circuit for supplying a control signal to the gate of the P-channel transistor, and the P-channel transistor is provided according to the value of the control signal of the gate control circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the conductive state and the non-conductive state of the disconnection circuit are controlled by making the conductive state and the non-conductive state. 3. The disconnecting circuit has a fuse and an ammeter that outputs a signal indicating the value of the current flowing through the fuse, and sets the fuse to either a connected state or a disconnected state. 2. The semiconductor integrated circuit according to claim 1, wherein a conduction state and a non-conduction state of the separation circuit are controlled by the. 4. The gate control circuit comprises a non-volatile memory, and the value stored in the non-volatile memory is output as a control signal of the gate control circuit, and the value of the non-volatile memory is switched when a test is performed. The semiconductor integrated circuit according to claim 2, wherein a mode capable of measuring a current value is provided. 5. The gate control circuit comprises an external input signal receiving circuit having a fuse, when the fuse is cut off, the P-channel transistor becomes non-conductive, and when the fuse is connected, , Which P-channel transistor is made conductive or non-conductive depending on the value of the external input signal, and which decoupling capacitance is specified by designating the P-channel transistor which is made conductive by the external input signal. 3. The semiconductor integrated circuit according to claim 2, wherein it is determined whether or not the current flowing through is abnormal.