JP2003017541A - Yield estimation method, yield estimation program, and yield estimation system for thin film product - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a higher-precision and more rational technique for analyzing the yield caused by occurred defects by using layout data in the field of manufacturing thin film product. SOLUTION: The determination of how critical a defect on a layout of a thin film product is performed by calculating the distance of a coordinate of the occurred defect from a graphical vector on the layout. A minimum distance connecting to two different graphics at the same time is determined as a critical defect dimension, and the determination result is stored, thus when a request is made for estimation and computation of the yield of defect cause, a critical probability of defect dimension is calculated from a ratio indicating a certain defective dimension which most probably causes a defect, and the yield estimation result is provided in real time from a defect distribution. The aforementioned estimation of the yield of defect cause in an easy way before product manufacturing allows changing to a layout designed to be resistant to defect, and managing quantitatively the relationship between cleanliness and yield of manufacturing process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing yield prediction method for a thin film device such as an LSI, a program for executing the yield prediction, and a yield prediction system using the program.

[0002]

2. Description of the Related Art In recent years, thin-film products such as semiconductor products have become finer, and defects such as short-circuiting of wiring and short-circuit defects due to the adhesion of minute foreign matter have become increasingly problematic. There is. If it is possible to predict the defect occurrence frequency due to the defect size and its occurrence density before manufacturing the product, it is possible to change the design to a layout that is resistant to defects.
In addition, the relationship between the in-line inspection result, which is the result of measuring the number of defects generated on the product wafer, its coordinates, and the size, and the yield is quantitatively managed, and measures are focused on processes that have a large impact on the yield. It also becomes possible. As a technique for predicting the frequency of occurrence of defective defects in this way, there is a technique called critical analysis that predicts the yield in consideration of the occurrence frequency (defect grain size distribution) for each size of defect and its fatal probability. This method uses the actual measurement result of the defect grain size distribution generated in the manufacturing process and the design layout to determine the fatal probability when defects randomly occur in the critical area of the entire LSI chip Yield is calculated as the product of the fatal probability and the number of occurrences for each defect size after the center coordinates of the shape defect are calculated as the area ratio of the area that becomes a fatal defect such as a wiring short circuit when existing at that location. Is a method of calculating.

Two calculation methods are known as known techniques for calculating the critical area. Each calculation method is assumed to be a circular conductive foreign substance having a radius r as a defect, and the yield due to a short circuit between wirings is taken as an example.
This will be described below.

Wiring Width Expansion Method (Geometry Method) This method is obtained by expanding the wiring on the layout by the radius r and utilizing the fact that the overlapping portion of these expanded wirings corresponds to the critical area. Is. This wiring expansion method is not practical because the calculation time becomes huge when a large-scale real layout pattern is calculated with high accuracy.

Monte Carlo method This method scatters foreign matter having a radius r to the coordinates on the layout determined based on a random number, calculates the number of this foreign matter that short-circuits with a plurality of wirings on the layout, and drops all of them. This is a method of calculating the fatal probability from the ratio in the number of foreign substances. (JP-A-48-40376)

[0006]

In the calculation simulation using the Monte Carlo method which is currently put into practical use as a critical area analysis method for the entire chip, a defect size (a circle having a radius r in the prior art example) is set in advance. If a defect of that size overlaps two different figures on the layout, it is determined to be a fatal defect. Therefore, when performing the critical area analysis simulation, for example, r1, r2,
Defects of a specific dimension having a discrete value such as r3 are generated on the layout, and the fatality of the defect dimension other than the defect generation interval is irrespective of whether the defect dimension is a constant interval or a non-constant interval. Cannot be calculated.

In the conventional Monte Carlo method, the fatal probability calculated from the critical area analysis depends on the defect size interval and the calculation target area. For this reason, the critical area analysis simulation and the yield prediction calculation using the determination result are premised on the use of a common defect dimension interval and area, and a method of continuously performing calculation processing on both is adopted. Although the Monte Carlo method takes less processing time than the wiring width extension method, it can perform hundreds of megabytes to several gigabytes, but critical area analysis simulation is performed by generating thousands to tens of thousands of defects on design layout data. Requires several hours or more for the calculation process. Therefore, the yield prediction calculation is performed by, for example, r1 described above,
When performing based on a certain value between r2, it is necessary to change the set value and then perform the critical area analysis simulation again for several hours each time.

As described above, the calculation result of the critical area analysis simulation cannot be treated as a general-purpose result that can be used for all defect dimension intervals and calculation target areas. Therefore, when changing the defect dimension intervals or areas, , I had to recalculate all the processing, and the operability was very poor. In addition, since there is such a process that takes a long time to calculate, it is incorporated into a system such as a WEB system that requires real-time performance, unless a pre-registered existing calculation result is referred to. It was not possible to build a system for obtaining the yield prediction result.

[0009]

According to the present invention, a determination is made as to the lethality that a defect occurring on the layout of a thin film product becomes defective is calculated by calculating the distance between the defect occurrence coordinate and the graphic vector on the layout. Yield prediction method characterized by determining the minimum distance to connect two figures at the same time as fatal defect size, and yield characterized by simulating distance calculation by generating defects at arbitrary coordinates on design layout data. It is a prediction program.

Further, according to the present invention, by using the generated defect coordinates and the fatal defect size at the coordinates, from the ratio of defects in a specific defect size among the generated defects,
The yield prediction method is characterized by calculating the fatal probability of the defect size, and the fatal probability is calculated by using the result of storing the defect coordinates generated and the fatal defect size at the coordinates in the memory of the computer or the external storage device. It is a yield prediction program characterized by simulation.

Further, according to the present invention, a yield-causing yield prediction calculation is performed from a defect occurrence coordinate stored in a memory or an external storage device, a fatal probability calculated from a fatal defect size at the coordinate, and a defect distribution situation of a manufacturing process. The yield prediction program is characterized by performing the calculation and providing the calculation result. Further, the present invention comprises a data input unit, a critical area analysis unit, a yield prediction calculation unit, and a yield prediction result display unit, and provides a yield prediction result due to a defect.
It is a yield prediction system characterized by being compatible with B. Further, the present invention considers that the figures overlapping each other on the layout are considered to have the same potential, and the figures having the same potential are judged to be the same figure, so that even if they are connected at the same time due to a defect, they do not become a fatal defect. The yield prediction program is characterized by being switchable between the case of performing the lethal determination and the case of performing the lethal determination without considering the same potential. Further, according to the present invention, one computer divides an operation target area on a layout, sets an area in which the divided areas are combined with another one or more computers, and allocates the arithmetic processing to each target area. It is a yield prediction system characterized by performing processing.

Further, according to the present invention, when the layout data is drawn, when the layout data in the drawing target area is extracted, the reading of the layout data corresponding to an arbitrary rectangular area having a specific size or less is omitted, and the size of the omitted size is omitted. Layout drawing method characterized by performing high-speed drawing by drawing only figures, and reading of layout data is omitted and skipped if it corresponds to a specific size rectangular area of layout data in the drawing target area. The layout drawing program is characterized in that the layout data drawn on the screen of the computer is not drawn.

Further, according to the present invention, when the area to be calculated is set, the image is drawn by a layout drawing program or the layout image stored in advance in an external storage device is read. The yield prediction system is characterized in that the area to be set as the calculation target is set by enclosing it on the image using an input device such as a mouse, or the set area with coordinate values is drawn on the layout image. is there.

Further, according to the present invention, the critical area analysis section input by the data input section, the layout data drawing section,
An input content relating to one or more processes of the yield prediction calculation unit, and a setting of whether to start the process when the preceding process content ends or when a preset date and time is reached is stored in an external storage device, The yield prediction system is characterized by starting a process corresponding to the stored process content at a set predetermined timing.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION With reference to the drawings, a yield prediction method using layout data, a program for executing yield prediction, and a yield using the program will be described below in the field of manufacturing thin film products such as semiconductor products. An example of the prediction system will be described.

FIG. 1 is a conceptual diagram showing the flow of yield prediction according to the present invention. Layout data to be analyzed 1
a and calculation condition 1b for performing critical area analysis
The data input section 1 and the critical area analysis calculation section 2
To enter. What is critical area analysis in the present invention?
Randomly generated sufficient virtual defects on the layout to satisfy the calculation accuracy (that is, generated by Monte Carlo method)
Then, the Monte Carlo simulation 21 for calculating the fatal defect size in the case where the defect is laid on two different wirings and both wirings are connected and short-circuited to be defective
And the processing of the fatality determination result storage 22 for storing the data on the chip coordinates of the generated defect and the fatal defect size, which are the calculation results, in the memory of the computer or in the external storage device. Next, using the fatality determination result data, the calculation function selection 1c and the calculation condition 1d for performing various calculations related to the yield prediction are provided to the data input unit 1.
Then, the data is input to the yield prediction calculation unit 3. The yield prediction calculation in the present embodiment is a yield prediction calculation 31 for individually performing four calculations related to yield prediction, which will be described later,
This is a method of performing the process of the yield prediction result storage 32 that stores the calculation result data on the memory of the computer or in the external storage device. The yield prediction calculation result as described above can be provided to the user by the process of the yield prediction result display 41 corresponding to the yield prediction result display unit 4. In this embodiment, the fatal defect size is not extracted from the discrete numerical values, but the accurate distance is calculated and the fatality determination result is held, so that the user does not have to perform the yield prediction calculation or the like. Even when various calculation conditions are set, it is not necessary to repeat the critical area analysis of this embodiment. That is,
The critical area analysis simulation based on the layout data 1a of a certain semiconductor product only has to be performed once, and the convenience for the user is dramatically improved. The above is the outline of the present invention, and the details will be described below.

FIG. 2 shows a Monte Carlo simulation 2
FIG. 3 is a diagram showing a concept of a fatal dimension, which is implemented in No. 1 and in which defects randomly generated on the layout are simultaneously connected to different wirings to cause a short circuit defect. First, different layout figures 201 are arranged on the layout of the calculation target area.
a, 201b, 201c. The defect generated at the defect generation coordinate 202 on the layout causes a short circuit because the distance between the defect generation coordinate (the coordinate of the center point when the fatal defect is a circle) and the layout graphics 201a to 201c is a vector. 2nd shortest among 203a-c
A circle having a radius of 03b, that is, a fatal defect 20
This is the case of 4. In the case of a defect smaller than the fatal defect 204, two different figures are not connected to each other, so that a short circuit failure does not occur. On the contrary, if the defects are larger than the fatal defect 204, all of them are short defects. This method is different from the conventional method of determining whether or not to connect two different figures for each size by generating defects of a specific size discretely determined by a constant interval or a non-constant interval. Since they are different, it is possible to uniquely obtain the critical defect size at the defect occurrence coordinates.

FIG. 3 is a diagram showing an embodiment of the processing flow of the critical area analysis / calculation unit 2 executed on the computer. The data input unit 1 sets the data name and mask name of the layout file as the layout data 1a to be simulated (301). In case of GDSII format which is the standard format of LSI design layout,
Enter all layer numbers required to create the set mask. The mask can be set by the combination of the layer numbers. Further, as the calculation condition 1b, the defect generation area on the chip coordinate system, the total number of defects N to be generated,
The maximum defect size Rmax is set (301) and the Monte Carlo simulation process 302 is started. First, layout data of a corresponding defect occurrence area is extracted from a layout data file registered in advance (303). Next, defect coordinates are generated in the area by random numbers (30
4), the distance between the defect and the graphic vector described in FIG. 2 is calculated (305), and the distance between the different graphic vector is compared,
To select the second smallest distance and treat the defect size as a diameter, the selected size is doubled to be the critical defect size (306). The above processes from 304 to 306 are repeated until the total number of defects becomes N (307), and finally, the data of the defect occurrence coordinates and the fatal defect size stored in the memory of the computer are filed as the fatality determination result data. (308). Here, the calculation of the fatality determination result data is performed according to the calculation condition 1b (for example, the total number of defects N
It may take a long time, but even if the calculation condition setting is changed in the processing such as defect distribution curve calculation and predicted yield calculation, which will be described later, the fatality determination result data can be used as it is. It is possible to realize the processing when the user uses it in a short time.

In the process 305, it is possible to use the maximum defect size Rmax as shown in FIG. 4 in order to reduce the time required to calculate the distance between the defect and the graphic vector.

As an example of the processing using the Rmax, first, two coordinate data of vertices on one diagonal of a quadrangle (range in which wiring exists) surrounding each figure vector on the layout data are calculated for each figure vector. The figure existence range data is calculated when the layout data is extracted.
This figure existence range data can be registered in the layout data itself in advance. In the example of FIG. 4, there are different graphic existence ranges 401a to 401d on the layout of the simulation calculation target area, and when a defect is generated at the defect occurrence coordinates 402 on this layout, all previously calculated graphic vectors and the defect occurrence are generated. The calculation amount of the fatal defect size calculation (distance calculation) is reduced by not using the distance calculation with respect to the coordinate 402 but determining whether or not the figure vector is the target of distance calculation first using the maximum defect size Rmax. Can be made. Specifically, a quadrangle 404 (a length of one side is the maximum defect dimension Rmax) surrounding a maximum defect dimension particle size 403 having a diameter Rmax centering on the defect generation coordinate 402 is calculated as a distance calculation target figure existing range, and a figure is calculated. Existence range 4
Among 01a-d, the figure overlapping this quadrangle 404 is determined. In this way, the calculation process can be simplified by treating the rectangles as overlapping determinations. In the example of FIG. 4, a figure whose figure existence range is 401a is not subject to distance calculation.

However, the value of the maximum defect size Rmax cannot be calculated in a region where the layout is rough unless the size is a certain size, whereas when the size is too large in the region where the layout is dense, the size of the fatal defect is calculated. The layout data is affected by the density of the layout data so that the number of target data items and the calculation amount increase. Therefore, the maximum defect dimension Rmax set in the process 301 holds a value considering the minimum wiring interval of the layout data as a default value, and the process 30
When calculating the critical defect size in 5, first, the quadrangle 404 shown in FIG. 4 is set by using this default value, and if there is no figure to be calculated in the quadrangle of this size, the existing To the maximum defect size Rmax of
The quadrangle is expanded to a range added with 10.0 micrometers, and it is determined whether or not the calculation target figure exists. In this way, by sequentially expanding the calculation target range by ΔR until the desired fatal defect dimension can be calculated, it is possible to calculate the fatal defect dimension with the maximum defect dimension Rmax according to the density condition of the layout.

In the present embodiment, a graphic (wiring) that overlaps a square having one side of the maximum defect dimension Rmax is processed by the algorithm using the graphic existence range data (diagonal vector) described above. Even processing by an algorithm is within the scope of the present invention. Further, it is not always necessary to use the above-mentioned square having one side of Rmax, and the case of using a circle having the diameter of Rmax is also within the scope of the present invention.

In process 303, the layout data extraction of the defect occurrence area is divided into areas obtained by dividing the simulation calculation object area 501 in the horizontal direction (X direction) and the vertical direction (Y direction) as shown in FIG. By doing so, it is possible to speed up the processing of a huge amount of layout data.
The example of FIG. 5 shows a case where areas S11 to S24 are created by dividing the area into two in the X direction and into four in the Y direction. A critical area analysis calculation is performed for each divided area as in S11. For example, 8000 in the simulation calculation target area 501.
When simulating the total number of defects (N = 8000), first, the layout data of the area S11 is read and set to 1
000 defects are generated, the size of the fatal defect is calculated, and then the layout data of the area S12 is read to 1000
The defect is generated, the size of the fatal defect is calculated, and the processing is repeated to simulate up to the area S24. By the arithmetic processing by the division, only a small amount of layout data needs to be dealt with, so that the processing can be speeded up. At this time, the layout data extraction region 502 is a region in which four sides are larger than the defect generation region 503 by ½ of the maximum defect dimension Rmax. This is necessary in order to consider the case where defect coordinates are generated on the area line of the defect generation area 503.

FIG. 6 shows an example of file registration contents of the fatality determination result registered in the process 308. It is composed of calculation condition data 601, divided area data 602, and generated defect critical dimension data 603. Occurrence defect critical dimension data 6
In 03, the generated defect coordinates grouped for each divided area and the critical dimension thereof are registered. In the present embodiment, an embodiment will be described in which the number of generated defects sufficient to satisfy the calculation accuracy is registered, and then the yield prediction calculation is performed using this fatal determination result data file.

FIG. 7 shows an embodiment of the processing flow of the yield prediction calculation unit 3 which performs various calculations related to yield prediction. First, the data input unit 1 is used to specify the name of the fatality determination result data file to be calculated (701), and all the relevant data is read on the computer (702). Then 4
Select which operation is to be performed from among various types of operations (a) defect distribution curve calculation, (b) average fatal rate calculation, (c) predicted yield calculation, (d) fatal rate distribution calculation by generated defect size,
Set the calculation condition parameters required for each calculation (70
3). The operations (a) to (d) can be individually activated, but the average fatality rate calculation (706) uses the defect distribution curve calculation (705) result and the predicted yield calculation (70).
7) uses the average fatality rate calculation (706) result. The fatal rate distribution calculation by generated defect size (708) is also a summary of the results of the average fatal rate calculation (705) divided for each area. Since the calculation results are related to each other in this way, the calculation condition parameter needs to be the same parameter as the preceding calculation. In this embodiment, if there is no change, the same value as the preceding calculation is used. Hereinafter, specific calculation condition parameters and calculation method of the yield prediction calculation 704 will be described. However, in the description of the calculation condition parameters, only newly required parameters are shown.

(A) Defect distribution curve calculation calculation condition parameters: calculation area, generated defect size interval Δ
R, minimum defect size Rmin. As the minimum defect size, it is possible to set the minimum value of the fatal defect size in the fatality determination result data. Calculation method: Targeting the defect coordinate data generated in the calculation area,
From the minimum defect size Rmin to the maximum defect size Rmax, "the number of defects equal to or less than the defect size / the total number of defects in the calculation area" is calculated for each ΔR interval. This corresponds to the fatal probability when the defect size is R.

(B) Average fatality rate calculation calculation condition parameter: Defect distribution index n (determined by cleanliness of the production line) Calculation method: Normalized occurrence frequency (defect grain size distribution) for each defect dimension R in the production line and the [formula 1] (n-1) · Rmin (n-1) / R n [ formula 1], by integrating the product of the critical probability obtained in (a) defect distribution curve calculation, an average fatality rate θ calculate.

(C) Predicted yield calculation calculation condition parameter: defect occurrence density Do [pieces / cm ² ]
(Determined by the cleanliness of the manufacturing line.) Calculation method: Yield Y is calculated using Poisson distribution [Equation 2] based on the calculation area area A and the average fatality rate θ obtained in (b) Average fatality rate calculation. To do.

Y = exp (-Do.A..theta.) [Equation 2] (d) Calculation condition parameter of fatal rate distribution for each defect size: Parameter number of division of operation area (X direction, Y direction), drawing target Generated defect size. Calculation method: The calculation area is divided in the X and Y directions by the number of divisions, and (a) defect distribution curve calculation is performed for each divided area. As the fatal rate distribution drawing result, the divided areas in the calculation area are color-coded according to the fatal probability of the defect size to be drawn, and the fatal probability of each area is displayed in a visually distinguishable manner.

The calculation result of the yield prediction calculation 704 is registered in a file (709), and each calculation result data and a line graph or fatal rate distribution drawing data are created and displayed (710). As described above, in the processing of 703 to 710, while referring to the same fatality determination result file,
It can be processed repeatedly.

FIG. 8 shows an example of (a) calculation result display of defect distribution curve calculation. As shown in the figure, a calculation condition parameter 801, calculation result data 802, and a line graph 803 created based on the calculation result data are displayed. The display of the calculations (b) to (d) can be realized in the same manner as this display screen.

FIG. 9 shows an embodiment of a functional block diagram for implementing the yield prediction method described so far. The overall function is composed of a critical area analysis main function 901, a user application calculation function 902, and a user application providing function 903. The critical area analysis main function 901 includes a layout data storage unit 904,
Data input unit (1a, 1b) 905, critical area analysis calculation unit 906, fatality determination result data storage unit 90
Have 7. User application calculation function 902
Has a yield prediction calculation unit 908 and a yield prediction result data storage unit 909. The user application providing function 903 has a data input unit (1c, 1d) 910 and a yield prediction result display unit 911. The functions 901 to 903 can be operated on the same computer.
It is also possible to run more than one function on another computer. WEB user application calculation function 902
User application providing function corresponding to the server 9
By using 03 as a WEB client (supporting WEB viewer software), it is possible to provide the user with a calculation result of the yield prediction calculation unit that requires less calculation time than the critical area analysis calculation in real time.

FIG. 17 shows an embodiment of a system configuration when the functional configuration of FIG. 9 is operated on a plurality of computers via a network. FIG. 17A shows the server machine 1.
This is a configuration example in which the critical area analysis main function 901 is operated on the 701, and the user application calculation function 902 and the user application providing function 903 are operated on one or more client machines 1702 connected to this server machine via a network. . Further, in FIG. 17B, the user application calculation function 902 corresponds to a WEB server, and the user application providing function 903 is a WEB client (supporting WEB viewer software), so that the critical area analysis main function 901 is set to the server machine 1703. The user application calculation function 902 on the WEB server machine 1704.
3 is a configuration example in which 3 is operated on one or more WEB client machines 1705. By implementing the configuration via the network in this way, yield prediction that requires less calculation time than the critical area analysis calculation for users of different departments such as design and manufacturing or multiple factories manufacturing the same product It is possible to provide the calculation result of the calculation unit in real time.

FIG. 10 shows another embodiment in which the calculation / synthesis 1e is incorporated as new data input into the data input section (1c, 1d) 910 of the functional block diagram of FIG. The yield prediction calculation unit 908 executes the yield prediction calculation for each calculation region in mask units. For example, M1, M2, and M of a certain product are calculated.
The predicted yield Y (all) of the three masks may be required in some cases. In this case, the synthesis of the predicted yield results is represented by [Equation 3], where the predicted yields of M1 to M3 are Y (M1), Y (M2), and Y (M3).

Y (all) = Y (M1) .Y (M2) .Y (M3) [Equation 3] First, in the calculation synthesis 1e, the finally required result is M1 to
The total yield up to M3 is set as a calculation synthesis parameter. Yield prediction result synthesis display unit 1002
Are predicted yields Y (M1), Y (M1) of M1 to M3.
2), Y (M3) is the yield prediction result data storage unit 909.
Is searched for, and if there is unregistered data, the yield prediction calculation unit 908 newly executes calculation,
The result of Y (all) is displayed as the result of executing [Equation 3]. By incorporating the synthesis processing method for various results as described above, it is possible to implement a system including synthesis of yield prediction results.

Next, FIG. 11 shows the equipotentialization of overlapping graphic vectors on the layout. In FIG.
The graphic vectors 1101a to 1101d on the layout are registered as individual graphics on the layout data. However, graphic vectors 1101a and b, graphic vector 11
Since 01b and c overlap each other, the graphic vectors 1101a, 110b, and 110c actually have the same potential. In consideration of the same potential, 11 of the generated defects 1102a and 1102b are generated.
02a does not become a short circuit at the same potential, and therefore does not become a fatal defect that causes a short circuit defect. Therefore, when performing the critical area analysis calculation, the yield prediction calculation result also differs depending on whether or not the calculation process for determining whether or not the same potential is obtained. In the present invention, it is possible to select whether to consider the same potential before performing the critical area analysis calculation.

FIG. 12 shows an example of the flow of the overlap determination processing of graphic vectors performed as the same potential determination processing, which is performed as the preprocessing of the critical area analysis calculation. In the data input unit 1, a layout data file name and a mask name are set as layout data to be processed, and the number of divisions or division dimensions for dividing the entire chip area in the X and Y directions is set as a calculation condition (1201). . In the electrification determination processing 1202, first, a rectangular range of a divided area is calculated (1203) and one divided area Sxy is set as a target (1204). The layout data of the target divided area Sxy is extracted (1205), two undetermined figures in the calculation area are selected (1206), and it is determined whether the figures overlap (1207). At this time, the figure existing area data shown in FIG. 4 is used. While there is an undetermined figure in the current target divided area Sxy (1208), 1206 to 1
The processing of 207 is repeated. Based on the result of the overlap determination processing of the figures in the divided areas, the same potential determination labeling N is applied to all the figure vectors in the layout data for each divided area.
o is registered (1209), and the processing from 1204 to 1209 is repeated until the determination of all divided areas is completed (1210). Finally, the layout data same-potential determination labeling numbers of all calculation target regions are merged (1211), the same-potential determination labeling NO is additionally registered in the layout data (1212), and the same-potential determination processing ends. The processing time is shortened by reducing the amount of calculation by dividing the entire chip.

When the same potential is taken into consideration when performing the critical area analysis calculation, the same potential additionally registered in the labeling data is calculated when the fatal defect dimension is calculated from the result of the distance calculation processing between the defect occurrence coordinates and the graphic vector. By using the labeling NO for determination, it is possible to consider that the figures of the same potential are the same figure.

The Monte Carlo simulation processing of the critical area analysis operation and the equipotential determination processing of the layout data described above are intended for the design layout data which may be several hundred megabytes to several gigabytes, and the thousands or more.
Since tens of thousands of defects are generated, the usual method requires a huge amount of calculation processing time. In this embodiment, the method of dividing the target area and reducing the calculation target figure to reduce the processing time is described. Further, as a method of shortening the processing time, it is possible to perform the parallel processing by dividing the processing on a plurality of computers by utilizing the division processing for each area. FIG. 13 shows a conceptual diagram of parallel processing when the layout data equipotential determination processing is performed.

FIG. 13 shows parallel processing by N computers consisting of computer A (1301A) to computer N (1301N). Assuming that the parent computer for instructing and monitoring the parallel processing is the computer A (1301A), first, the layout data file name, the mask name, and the calculation are set as the layout data to be processed, which is set (1302) in the data input unit 1. As a condition, the computer A sets a region in which the divided regions are combined according to the number of divisions or the division size for dividing the entire chip region in the X direction and the Y direction, and the computer B to N (1301B to 1301B ... N)
Is set, and each computer is instructed to start processing (1
303). Each computer has a labeling No process (13) for layout data equipotential determination of all requested calculation target regions.
04B to N), and when the processing of all areas to be calculated is completed, the completion report is individually sent to the parent computer A (1305).
B-N). The parent computer A monitors the processing end for each computer after the processing start instruction is issued (1306), and when the processing of all the divided areas is completed (1307), the layout data for each divided area registered by each of the computers B to N is copied. The potential determination labeling number is used to perform the merge processing of the determination result in the entire chip area (1308), and finally the same potential determination labeling number is registered in the layout data (1309), and the process is terminated. Although not shown in FIG. 13, the parent computer A
The device itself may share the same potential determination process for the target divided region.

In this embodiment, the calculation target area on the layout data coordinates is set as the calculation condition parameter for the critical area analysis calculation and the yield prediction calculation. However, besides the target area setting, the yield prediction is performed. A function of drawing the contents of the layout data on the screen of the computer and confirming the graphic information is effective, for example, when referring to the layout condition of the wiring on the layout data from the result. In the conventional layout data drawing process, the drawing process takes time because all of the huge amount of layout data is referenced. In the present invention, attention is paid to the fact that the layout data structure is generally a hierarchical structure composed of a group of figures called cells, and the figure existing area data described in FIG. 4 is registered in advance in the layout data itself for each cell figure. When the layout data drawing process is executed by using the figure existing area data of the registered clear, the reading of the layout data corresponding to the rectangular area of an arbitrary specific dimension is omitted, and only the figure of the omitted corresponding dimension is drawn. Therefore, a layout drawing method capable of high-speed drawing is provided. By such an omission drawing method, for example, in comparison with the case where the omission drawing of the data search for one pixel or less on the screen is performed,
When the data of pixels or less is omitted and drawn, the drawing processing time can be shortened to about 1/10.

FIG. 14 shows an embodiment of a processing flow of layout omitted drawing. First, in the data input unit 1, a layout data file name, a mask name for drawing, a drawing area (entire chip area when omitted) as a drawing condition, and an omitted dimension or an omitted pixel number on the screen as an omitted drawing unit (1
401). In the drawing process, the display magnification is converted from the drawing area coordinates according to the drawing window size (140
2) If the abbreviated unit is the number of pixels designated (1403), it is converted to the corresponding dimension in the display magnification (1404), and the abbreviated unit dimension is set (1405). Next, the layout data is searched for an unextracted upper layer cell graphic (140
5) The figure existing area data is extracted (1407), and it is determined whether or not it corresponds to a cell figure existing in the drawing area (1408). If it exists in the drawing area, it is determined whether it is less than the omitted unit size (1409). If it is less than the omitted unit size, a rectangle corresponding to the omitted unit is drawn (141).
0), the extraction of the hierarchical lower cell graphic from the cell graphic is omitted. If it is larger than the omitted unit size, it is judged whether there is any unextracted hierarchical structure lower cell figure (141).
1) If there is a lower cell graphic, the graphic existing area is extracted (1412), and it is again judged whether the size is equal to or less than the omitted unit size (1409). Only when there is no lower cell graphic, the layout graphic vector is determined. It is drawn (1413).

FIG. 15 shows an embodiment of a functional configuration diagram in which a layout drawing function capable of layout omitted drawing is incorporated in the functional structure for implementing the yield prediction method described in FIG. The overall functions are the critical area analysis main function 1501 and the user application calculation function 150.
2. The user application providing function 1503. This critical area analysis main function 1501
A data input unit (1f, 1g) 1504, a layout drawing unit 1505, and a layout drawing result storage unit 1506 are incorporated in the above. Also, the user application providing function 15
The layout drawing result display unit 1507 is incorporated in the area 03. When the area to be calculated is set by these additional functions, the area to be calculated is set on the drawing result screen of the layout drawing unit 1505 or the layout image reading screen registered in the layout drawing result storage unit 1506 in advance. It is possible to provide a yield prediction system in which a region is set by surrounding the image with an input device such as a mouse, or a set region in which coordinate values are designated is superimposed and drawn on a layout image.

Further, FIG. 16 shows an embodiment of another functional block diagram for improving the operability of FIG. Critical area analysis main function 1601, user application calculation function 1602, user application providing function 1
Regarding the processing of the critical area analysis calculation section 1604 and the layout drawing section 1605 of the critical area analysis main function 1601 in 603, the method of shortening the processing time has been described in the present embodiment. The processing time tends to increase depending on the amount of data. Therefore, in order to reduce the user restraint time, the automatic processing data storage unit 1606 is incorporated, and the input contents of the data input unit (1a, 1b, 1f, 1g) included in the user application providing function 1603 and the preceding processing contents are completed. Whether to perform the process or when the preset date and time is reached is registered. The automatic processing management unit 1607 can provide a yield prediction system that realizes automatic processing by managing the processing start and end of each registered content at any time according to this registered content.

In the above description, a short-circuit defect in which different wirings are short-circuited due to a defect has been described. However, even in the case of an open defect caused by a non-conductive foreign substance that breaks the wiring, a critical dimension for cutting the wiring. It is possible to predict the yield by a similar method.

[0046]

INDUSTRIAL APPLICABILITY The present invention provides a defect generation yield defect prediction technique using layout data for manufacturing thin film products such as semiconductor products as a new analysis method of critical area analysis simulation by the known Monte Carlo method. A method for uniquely determining the occurrence critical dimension from the distance calculation between the coordinates and the graphic vector of layout data is provided. Further, by storing the analysis result as the fatality determination result data, it becomes possible to provide the yield prediction calculation result in real time. The conventional critical area calculation tool has not been established as a utilization technology because it takes a long time to process one yield prediction calculation and has very poor operability, but the processing time made possible by the present invention. By using a yield prediction system that is shorter and has improved operability, it is possible to improve the accuracy and rationalization of yield analysis.

As a result, it becomes possible to change to a design layout that is resistant to defects by easily predicting the size of defects and the frequency of occurrence of defects due to their density before manufacturing the product. In addition, it is possible to quantitatively manage the relationship between the cleanliness of the manufacturing process and the yield, and focus on the steps that have a great influence on the yield.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a flow of yield prediction according to the present invention.

FIG. 2 is a diagram showing an analysis method of Monte Carlo simulation according to the present invention.

FIG. 3 is a diagram showing an embodiment of a processing flow of a critical area analysis / calculation unit according to the present invention.

FIG. 4 is a diagram showing a method of utilizing a figure existing range according to the present invention.

FIG. 5 is a diagram showing a method of dividing a calculation target region of Monte Carlo simulation according to the present invention.

FIG. 6 is a diagram showing an example of file registration contents of a fatality determination result according to the present invention.

FIG. 7 is a diagram showing an example of a processing flow of a yield prediction calculation unit according to the present invention.

FIG. 8 is a diagram showing an embodiment of a calculation result display of defect distribution curve calculation according to the present invention.

FIG. 9 is a diagram showing an embodiment of a functional configuration diagram for implementing the yield prediction method according to the present invention.

FIG. 10 is a diagram showing an embodiment of a functional configuration diagram for implementing the yield prediction method according to the present invention.

FIG. 11 is a diagram showing equalization of overlapping graphic vectors on the layout according to the present invention.

FIG. 12 is a diagram showing an embodiment of the same potential determination processing flow according to the present invention.

FIG. 13 is a conceptual diagram of parallel processing when carrying out layout data equipotential determination processing according to the present invention.

FIG. 14 is a diagram showing an embodiment of a processing flow of layout omitted drawing according to the present invention.

FIG. 15 is a diagram showing an embodiment of a functional configuration diagram for implementing the yield prediction method according to the present invention.

FIG. 16 is a diagram showing an example of a functional configuration diagram for implementing the yield prediction method according to the present invention.

FIG. 17 is a diagram showing an example of a system configuration for implementing the functional configuration according to the present invention.

[Explanation of symbols]

1 Data input section 2 Critical area analysis calculation unit 3 Yield prediction calculation unit 4 Yield prediction result display section 21 Monte Carlo simulation 22 Memory of fatality determination result 31 Yield prediction calculation 32 Yield prediction result memory 41 Yield prediction result display 1a Layout data 1b Calculation conditions 1c Calculation function selection 1d Calculation conditions

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naofumi Iwata             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Yuichi Hamamura             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Takaaki Kumazawa             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory F-term (reference) 4M106 AA01 BA20 CA70 DH60 DJ20                       DJ21 DJ23                 5F064 EE14 GG03 HH02 HH07 HH09                       HH10 HH12 HH13 HH14 HH15

Claims (17)

[Claims] 1. A design layout data of a thin film product is read from a storage means, a distance between a defect occurrence coordinate generated and a graphic vector based on the design layout data is calculated by a calculation processing means, and two different layout graphics are simultaneously obtained. A yield prediction method, characterized in that the minimum distance to be connected is stored in a storage unit as a fatal defect dimension, and a predicted value of the yield of the thin film product is calculated based on the stored fatal defect dimension result. 2. The yield prediction method according to claim 1, wherein the defect coordinates generated and the fatal defect size at the coordinates are used, and when the defect size is a specific defect size. A yield prediction method, wherein a fatal probability of the defect size is calculated from a defect rate, and a result of calculating the fatal probability for each specific defect size is displayed in a graph. 3. The yield prediction method according to claim 1, wherein the defect coordinates generated and the fatal defect size at the coordinates are used, and when the defect size is a specific defect size. From the rate of failure, the fatal probability of the defect size is calculated, using the result of calculating the fatal probability for each specific defect size, the average fatal rate is calculated, and the average fatal rate is displayed. Yield prediction method. 4. The yield prediction method according to claim 1, wherein the layout area is divided into a plurality of areas, and defect coordinates generated and fatal defect dimensions at the coordinates are divided for each of the divided areas. Using, from the rate of failure in the case of a specific defect size in the number of defects generated, calculate the fatal probability of the defect size, the result of calculating the fatal probability for each specific defect size, the A yield prediction method characterized by displaying each divided region. 5. The yield prediction method according to claim 1, wherein the figures that overlap each other on the design layout have the same potential, and if the figures have the same potential, it is determined that they are the same figure. A yield prediction method characterized by performing a fatal determination in consideration of not causing a fatal defect even if they are simultaneously connected. 6. The yield prediction method according to claim 1, wherein the figures that overlap each other on the design layout have the same potential, and if the figures have the same potential, it is determined that they are the same figure. A yield prediction method characterized in that it is possible to switch between a case where a fatal judgment is made in consideration of not causing a fatal defect even if they are simultaneously connected and a case where a fatal judgment is made without considering the same potential. 7. The yield prediction method according to claim 1, wherein the calculation target area on the design layout is divided by one computer, and the divided areas are combined with another one or more computers. A yield prediction method characterized by performing parallel processing in which an area is set and arithmetic processing is allocated to each target area. 8. A step of reading design layout data of a thin film product from a storage means, a step of calculating a distance between a generated defect occurrence coordinate and a graphic vector based on the design layout data by an arithmetic processing means, and two different steps. Performing a step of storing in a storage means a minimum distance that is simultaneously connected to a layout figure as a fatal defect dimension, and a step of calculating a predicted value of the yield of the thin film product based on the stored result of the fatal defect dimension. Yield prediction program featuring 9. The yield prediction program according to claim 8, wherein the defect coordinates generated and the fatal defect size at the coordinates are used to determine a specific defect size among the generated defects. A yield prediction program characterized by executing a step of calculating a fatal probability of the defect size from a defective rate, and a step of displaying a result of calculating the fatal probability for each specific defect size in a graph. 10. The yield prediction program according to claim 8, wherein the defect coordinates generated and the fatal defect size at the coordinates are used to detect a specific defect size among the number of generated defects. From the rate of failure, calculating the fatal probability of the defect size, using the result of calculating the fatal probability for each specific defect size, calculating an average fatal ratio, displaying the average fatal ratio A yield prediction program characterized by performing the steps of 11. The yield prediction program according to claim 8, wherein the layout area is divided into a plurality of areas, and the defect coordinates generated at each of the divided areas and a fatal defect size at the coordinates. Using the step of calculating the fatal probability of the defect size from the defective rate in the case of a specific defect size among the generated defects, and the fatal probability was calculated for each specific defect size. A yield prediction program, comprising: displaying the result in a graph for each of the divided areas. 12. The yield prediction program according to claim 8, wherein the figures that overlap each other on the design layout have the same potential, and if the figures have the same potential, it is determined that they are the same figure. A yield prediction program characterized by executing a switching step between a case where a fatal judgment is made in consideration of not causing a fatal defect even if they are simultaneously connected and a case where a fatal judgment is made in which the same potential is not taken into consideration. 13. The yield prediction program according to claim 8, wherein the step of dividing the calculation target area on the design layout by the processing of one computer, and the division for one or more other computers. A yield prediction program characterized by executing a step of setting an area in which areas are combined and a step of performing parallel processing for allocating arithmetic processing for each target area. 14. A storage means for holding design layout data of a thin film product, a distance calculation between a generated defect coordinate and a graphic vector based on the design layout data read from the storage means, and two different layout graphics. And a calculation processing unit that calculates a minimum distance that is simultaneously connected to a critical defect size as a fatal defect size, and calculates a predicted value of the yield of the thin film product based on the critical defect size result. . 15. The design layout data of the thin film product is read from the storage means, the distance between the generated defect coordinates and the graphic vector based on the design layout data is calculated by the arithmetic processing means, and two different layout graphics are simultaneously obtained. The minimum distance to be connected is stored in the storage means as a fatal defect size, the stored fatal defect size result is transmitted to the client device via the network, and the yield of the thin film product is predicted based on the fatal defect size result. Yield prediction method characterized by supporting the 16. A design layout data of a thin film product is received from a client device via a network, and a distance between a defect occurrence coordinate generated and a graphic vector based on the design layout data is calculated by an arithmetic processing means. The minimum distance that is simultaneously connected to one layout figure is stored in the storage unit as a fatal defect dimension, based on the stored fatal defect dimension result, a predicted value of the yield of the thin film product is calculated, and the yield predicted value is a network. Yield prediction method, characterized in that the data is transmitted to the client device via the. 17. The minimum distance for simultaneously connecting two different layout figures is determined by calculating the distance between the generated defect occurrence coordinates and the figure vector based on the design layout data of the thin film product, thereby determining the fatal defect size. As a result, the fatal defect dimension data is read from the storage unit that holds the result calculated in advance and is transmitted to the client device. Based on the transmitted fatal defect dimension data, the yield of the thin film product is calculated by the arithmetic processing unit on the client side. A yield prediction method characterized by calculating a predicted value of.