JP2003008441A - Digital/analog converter, and data driver for driver monolithic display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data driver for a driver monolithic liquid crystal display device capable of enhancing video display quality and to provide a digital/analog converter used for the data driver. SOLUTION: The data driver is provided with; 1st capacitor arrays C0 , C1 for setting a selected analog output voltage on the basis of bit data of a received digital data signal; switches SWM, SWL, and Swbus that set a precharge period for pre-charging the 1st capacitor arrays C0 , C1 and an external Cbusl connected to them; a switch SWH that selects the 1st capacitor arrays C0 , C1 on the basis of the bit data, charges them, and sets a conversion period from determining an analog output voltage with a capacitance ratio of the total capacitance of the 1st capacitor arrays C0 , C1 to the capacitance of the external CbusL and 2nd capacitors Cph, Cpm, Cp1 connected in parallel with reference power supply wiring terminals of the switches SWH, SWM, SWL to reduce the impedance of the reference power supply wires.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter suitable for gradation display of a liquid crystal panel and the like, and a data driver of a driver monolithic display device using the D / A converter.

[0002]

2. Description of the Related Art In a driver monolithic liquid crystal display device, when a data driver circuit is formed monolithically on an inexpensive silicon substrate such as Poly-Si (polycrystalline silicon), a TFT formed in the monolithic data driver circuit ( When a D / A conversion amplifier is composed of thin film transistors, the characteristic variation of the TFT is much larger than that when single crystal Si is used, the variation of the amplifier output is suppressed, and the D / A conversion (digital data signal to analog It is extremely difficult to perform stable conversion after conversion into a data signal).

Therefore, when the D / A converter is formed in the data driver circuit of the driver monolithic liquid crystal display device, a capacitance division type (capacity array charge redistribution type) D / A is used without using an amplifier in the output section. A converter may be adopted. This is suitable for monolithic integration because the on resistance of the switch for switching the charge of each capacitor does not cause an error and the accuracy is determined by the ratio of the capacitors, not the absolute accuracy of the capacitors. .

Next, the operation of the capacitance division type D / A converter will be described with reference to FIGS. Figure 4
11 to FIG. 11 show D which constitutes a conventional data driver circuit.
The circuit configuration of the / A converter and the switching state of the circuit configuration according to the control signal are shown. SWHn, SWMn, and SWLn in the figure are Nch TFTs.
Shows the analog switch formed by, SWHp, S
WMp and SWLp are analog switches formed by Pch TFTs.

That is, the analog switch formed by the Nch TFT is turned on (= 1) when a Hi level signal input is applied to its gate terminal and turned off (= 1) when a Low level signal input is applied to the gate terminal. = 0). Further, the analog switch formed by the Pch TFT is turned on (= 1) when a Low level signal input is applied to its gate terminal, and turned off (= 0) when a Hi level signal input is applied to its gate terminal. ) Do. Nch TFT, Pch
By providing each analog switch formed by TFT complementarily, redundancy is increased and reliability is improved.

In order to simplify the following description, the D / A
The digital data signal input to the converter is 2 bits (the figure shows the case of Bit 0 = 1 and Bit 1 = 1). Hereinafter, the processing of the capacitance division type D / A converter will be described. As shown in FIGS. 4 to 11, data signals Bit 0 and Bit 1, control signals VRH and SEN, and reference voltages VH, VL, and VM are input to the D / A converter. Here, the period when the VRH signal is Hi is the precharge period, and the period when the VRH signal is Low is the DAC.
The period (D / A conversion period). 12 and 13
The output calculation explanation of this D / A converter based on the charge (voltage) to each capacitance (capacitor) in the precharge period and the DAC period is shown in FIG.

First, as shown in FIGS. 4 and 5, during the precharge period (switch state A), SWMn, SWMp and SWLn, SWLp are ON (= 1), so C0,
A potential difference of (VM-VL) is generated at both ends of C1 (first capacitance array).

Subsequently, as shown in FIGS. 6 and 7, when SEN becomes active (Hi) and SWbus1 becomes ON, C
A potential difference of VM-GND = VM occurs at both ends of bus1 (external capacitance). The precharge to C0 and C1 (first capacitance array) is performed regardless of the input state (bit (bit) data) of the data signals Bit0 and Bit1.

That is, the sum Q _{A of the} charge amounts stored in C 0, C 1 (first capacitance array) and C bus 1 (external capacitance) during the precharge period is Q _A = (2 ¹ +2 ⁰ ) × C × (VM
−VL) + Cbus1 × VM, which is represented by the following general formula (see FIG. 13A).

[0010]

[Equation 1]

* (C: minimum capacitor capacity in D / A converter formation = capacity of least significant bit N: bit of D / A converter, 0 and 1 in this example) Next, referring to FIGS. As shown, in the DAC period (switch state C), SWMn, SWMp and SWLn, SWL
p is OFF (= 0), SWHn and SWHp are ON
(= 1). Bus line 1 potential in this case is Vout
Then, the general formula of the total sum Q _B of the charge amounts stored in C0, C1, and Cbus1 is as follows (FIG. 13 (b)).
reference).

[0012]

[Equation 2]

* (C: minimum capacitor capacity unit for forming D / A converter = capacity of least significant bit, BitN:
Bit of Input ON State of D / A Converter) When Bit 0 = 1 and Bit 1 = 1 of this embodiment are applied to the above general formula, the following formula is obtained.

Q _B = (2 ¹ +2 ⁰ ) × C × (Vout −V
H) + {(2 ¹ +2 ⁰ ) − (2 ¹ +2 ⁰ )} × C × (V
out-VL) + Cbus1 x Vout = 3 x C x (Vout-V
H) + Cbus1 × Vout At this time, since SWMn and SWMp are OFF, the total amount of charge stored in each capacitance C0, C1 (first capacitance array) and Cbus1 (external capacitance) does not change, so Q _A
= Q _{B has} a relationship.

That is, as a general formula,

[0016]

[Equation 3]

When the bus line potential Vout is obtained from the above equation, the following equation is obtained.

[0018]

[Equation 4]

Then, as shown in FIGS. 10 and 11, SE
N becomes inactive (SWbus1 is OFF), and the potential of bus line 1 holds Vout. As explained above,
Vout is C0, C1 selected by Bit 0, Bit 1
(First capacity array) capacity total and bus line capacity Cbus1
It is determined by the capacity ratio of (external capacity).

If multi-gradation output is required, C
Should be finely divided. For example, in the case of 8 bits, C0 to C7 (first capacitance array) are prepared, and the respective capacitances C0 to C7 are 2 ⁰ , 2 ¹ , 2 ² as shown in FIG.
... It may be divided by a capacity ratio of 2 ⁷ . FIG. 12 shows an image showing changes in the bus line potential in the D / A conversion process.

As described above, the processing shown in FIGS. 4 to 12 is repeated to convert the digital data signal into an analog data signal which is an analog output voltage for gradation display and output the D / A conversion. I do.

However, by using the above-mentioned D / A converter, for example, a base for driving a liquid crystal display device having a display resolution of XGA (1024 × 768) and a refresh rate of 60 Hz, a data driver circuit constituting the liquid crystal display device. Therefore, the area of the peripheral driver with respect to the display region becomes large, or the number of elements forming the data driver circuit increases, resulting in various problems such as a decrease in the yield of the data driver circuit.

That is, assuming that the display resolution is XGA (1024 × 768) and the refresh rate is 60 Hz,
The maximum total conversion time required for the D / A converter is 1
/ 60/768/1024 = 20 ns. (Actually, the total conversion time is further shortened due to the vertical blanking time and the horizontal blanking time.) The Cbus (external capacitance) of the D / A converter described above is the source bus line of the display unit of the liquid crystal display device. The capacity is assumed, and the source bus line capacity Cbus is assumed.
Is 10 pF, and the range of voltage levels applied to the liquid crystal layer is 11 V at maximum and 3 V at minimum. (Because characteristic deterioration such as polarization occurs unless a voltage with positive / negative polarity inversion is applied to the liquid crystal layer. It is assumed that ± 4 V is applied with 7 V as the center value of the video signal).

The amplitude of the reference power supply voltages VH and VL is set to 1V.
.About.9V, VM = 7V (assuming that the voltage amplitude applied to the control terminal of the analog switch is about 10V, the reference voltage range at which the analog switch can be turned ON / OFF is assumed to be about 1V to 9V). According to the formula of Vout, the capacitance of C0, C1 (first capacitance array) and C0 + C1 = Call (2 bits are assumed in this case) requires 10 pF. This is based on the following reasons.

That is, Vout positive electrode = Call / (Call +
Cbus) × (9-1) + 7 = 10 pF / (10 pF + 1
0pF) × (9-1) + 7 = 11V Vout negative electrode = Call / (Call + Cbus) × (1-9)
+ 7 = 10 pF / (10 pF + 10 pF) × (1-9)
+ 7 = 3V Here, about half of the maximum total conversion time of 20 ns allowed for D / A conversion is a precharge time (10 n
s), Call + Cbus = 20 pF
The ON resistance Ron required for the analog switch to charge up to 99% of the reference voltage is 0.22kΩ
Becomes This is (Call + Cbus) x Ron x 4.5 =
It is calculated from 20 pF × Ron × 4.5 = 20 ns, and the time required for 99% charging is about 4.5τ (time constant).

The high Ron of 0.22 kΩ is due to the single crystal S
TF using Poly-Si (polycrystalline silicon), which has a lower mobility than i or the like, or continuous grain boundary crystal Si (which has a higher mobility than Poly-Si but is lower than single crystal Si), etc.
T requires a relatively large size TFT.

In order to perform the above-mentioned XGA display, the capacitance C such as C0 and C1 and the TF for analog switch are used.
A D / A converter having T has a horizontal pixel count (1024
The number of the data driver circuits constituting the liquid crystal display device becomes very large. For this reason,
The area of the peripheral driver circuit with respect to the display area becomes large (the display area becomes relatively small), or the number of elements forming the data driver circuit increases and various problems such as a decrease in the yield of the data driver circuit occur. .

Therefore, the following measures have been proposed to solve the above-mentioned problems. FIG. 14 shows the configuration of a driver monolithic liquid crystal display device capable of reducing the above-mentioned problems. The liquid crystal display device includes a digital data driver circuit 41 and a scan driver circuit 42.
And a display unit 43 driven by them. The display unit 43 has pixels 43a including liquid crystals and TFTs 43b for driving the pixels 43a in a matrix. Therefore, in the display unit 43, each bus line (denoted as bus in the drawing) connected to the digital data driver circuit 41 apparently has the above-mentioned Cbus.
(External capacity) is connected respectively.

As shown in FIG. 14, the data driver circuit 41 is a sampling pulse generation circuit, LAT (latch).
1 circuit 1 to LAT 1 circuit 256, LAT 2 circuit 1 to LAT
2 circuits 256 and DAC circuit 1 to DAC circuit 256 and Bu
D / having s Selecter1-4 ~ Bus Selecter1021-1024
It is composed of an A converter 41a _{1 to a} D / A converter 41a ₂₅₆ .

In the data driver circuit 41, video data (Video Data) A0 to A7 and B0 to B which are digital data signals.
7, CO-C7, D0-D7 and various control signals SP, C
K, CKB, RES, LAT2, SE0-3, VRH,
And VH which is the reference power supply voltage for the D / A converter,
VL and VM are input.

As can be seen from FIG. 14, the LAT1 circuit and the L circuit are provided for every four Bus wirings that constitute the display section 43 of the liquid crystal display device.
One set of AT2 circuit and D / A converter is assigned. That is, one set of LAT1 circuit, LAT2 circuit, and D / A converter is shared by four Bus wirings that function as external capacitors.

The operation of the data driver circuit 41 of the above-mentioned driver monolithic liquid crystal display device will be described below with reference to FIGS. 14 and 15.

As the video data input to the data driver circuit 41, as shown in FIGS. 15 and 16, four-phase data of A to D is converted into the original data rate (1/60/768 /
4 times 1024 = 20ns (20ns × 4 = 80n)
s) is expanded in the time axis (actually, since there is a blanking time between each phase, it is not quadrupled, but it is set to blanking time = 0 ns for simplification of description) and input in parallel.

As is apparent from FIG. 15, Data series A to D
Is for one horizontal period with 256 data as one phase
Bus (pixel) data of A to D4 series is divided into four phases and input. Also, the Bu of each Data series
s As for the data input order, as shown in FIG. 15, the data series of A to D are input in parallel by skipping 4 data at the same time, and the data input order of the same series is input by skipping 16 data. The inter-phase data is input by shifting one data.

The video data input in each phase is temporarily output by the LAT1 circuits 1 to 1 by the sampling signals Samp 1 to 64 sequentially output by the clock signal CK from the sampling pulse generating circuit which operates as shown in FIG.
It is stored in 256. The SP signal, which is a start pulse input to the sampling pulse generation circuit, is input at the output timing of the first video data of each phase, and the final data of the nth phase (for example, 1009, 1013 in the case of the first phase). , 1017, 1021) are stored in the LAT1 circuit 256 by the sampling pulse Samp 64, a LAT2 signal is output, and the data stored in the LAT1 circuit n is transferred to the LAT2 circuits 1-256.

That is, while sampling the image data of the nth phase, the LAT2 circuits 1 to 256 keep the (n-th)
1) The video data sampled in the phase continues to be output (however, the first phase is the Data sampled in the fourth phase). Bus Selecter during the nth phase
Selects the Bus corresponding to the Bus data acquired in the (n-1) th phase, and the D / A converters 41a _{1 to} 41a
a ₂₅₆ and the Bus line capacity Cbus (external capacity) perform D / A conversion.

In the above-mentioned example, the D / A conversion time = 1 horizontal period / 1024, but by performing the data processing as described above, the D / A converter 41a is ¼ of one horizontal period. _Since data is input to _{1 to} 41a ₂₅₆ , the D / A conversion time can be greatly expanded. In addition to enabling the D / A conversion time to be extended by such a measure, the data driver circuit 4
The number of circuits of the D / A converters 41a _{1 to} 41a ₂₅₆ provided in _{1 is} only 1/4 of one horizontal resolution (1024), and the number of circuit elements forming the data driver circuit 41 can be reduced.

Of course, if the number of input video data streams is increased, it is possible to further reduce the number of D / A converters provided in the data driver circuit 41 and reduce the required D / A conversion speed.

[0039]

However, when the above measures are used, the following problems occur.

D / A converters 41a ₁ -41 shown in FIG.
41a ₂₅₆ operates at the same time in 1/4 horizontal period, so D
/ A41a ₁ ~41a ₂₅₆ converter DAC circuits 1
It is necessary to charge and discharge the capacity of 256 C lines and 256 Bus lines in the precharge period.

Now, consider the impedance of the reference voltage power supply input to the D / A converter. As shown in FIG. 4, the reference power supply voltage of the D / A converter is supplied from an external drive circuit. Although the power source output impedance of the external drive circuit is sufficiently low, the reference power source wiring in the monolithically formed data driver circuit 41 of the liquid crystal display device is routed with a wiring having a small line width. The wiring resistance R of the wiring has a size that cannot be ignored.

Therefore, the impedance of the power supply wiring inside the data driver circuit 41 becomes high, and during D / A conversion, sufficient charges cannot be supplied within the precharge period, and the analog output voltage from the D / A converter is not supplied. This causes deterioration in display quality.

Further, as shown in FIG. 18A, when a display having different display gradations (for example, window display 43c) in one horizontal period is performed, a portion 43d (window display) where the display gradation does not change in the horizontal period is displayed. (The upper and lower portions of 43c) and a portion 43e where the display gradation changes in the horizontal period, a difference occurs in the display gradation, which causes a horizontal crosstalk 43f as shown in FIG. 18 (b).

This is the part 4 where the display gradation does not change.
Charge in the precharge period when performing D / A conversion of the horizontal line corresponding to 3d, and charge in the precharge period when performing D / A conversion of the horizontal line corresponding to the portion 43e where the display gradation changes This occurs because the amounts are different and C and Cbus (external capacitance) cannot be charged to the VM level within the precharge period.

That is, the total capacitance of C (first capacitance array) selected in one horizontal period is different at each of the portions 43d and 43e, and in the case of FIG. 18A, the portion 43e where the display gradation changes. Has a larger total capacity of C. This is because there is a black display area in the area 43e where the display gradation changes, and the total number of charged capacities increases.

As described above, due to the insufficient wiring of the output voltage setting capacitance forming the D / A converter due to the wiring impedance inside the data driver circuit 41, the black level of the liquid crystal display device floats and the horizontal crosstalk 43f occurs. This causes problems such as deterioration of display quality.

[0047]

In order to solve the above-mentioned problems, the D / A converter of the present invention has a first analog output voltage setting that is selected based on the bit data of the input digital data signal. A capacitor array and a reference power supply line for supplying charges to the first capacitor array, and a pre-charge for pre-charging the first capacitor array and an external capacitor connected to the first capacitor array for initial setting. The capacitance of the first capacitance array is selected based on the charge period and the bit data described above, the selected capacitance is charged with an analog setting charge, and the analog output is performed according to the capacitance ratio of the total capacitance of the first capacitance array and the external capacitance. In a D / A converter having a conversion period for determining a voltage, a precharge capacitor for initial setting is provided between a terminal of the first capacitor array and a reference power supply line. Switching elements are provided for controlling, it is characterized in that the second capacitor to lower the impedance of the reference supply wiring line is provided in parallel with the reference power supply line up to the switching element.

According to the above configuration, since the second capacitor is provided, when the D / A conversion is performed, a sufficient charge is generated within the precharge period with respect to the first capacitor and the external capacitor to be charged during the precharge period. Can be supplied.
Therefore, in the above configuration, during the precharge period,
It is possible to avoid deterioration in display quality due to insufficient charge supply.

In the above-mentioned D / A converter, the second capacitor is composed of the first conductive layer forming the reference power supply line and the second conductive layer formed with the insulating layer separated from the first conductive layer. It is preferable that a potential different from the reference power supply wiring potential is applied to the formed second conductive layer.

In the above D / A converter, the potential level applied to the second conductive layer may be set to the center potential of the voltage range of the analog output voltage.

In the above D / A converter, the potential level applied to the second conductive layer may be set to the GND potential.

In the above D / A converter, the potential level applied to the second conductive layer may be set to the reference power source potential or the D / A converter driving power source potential different from the above potential level.

According to the above structure, the potential level applied to the second conductive layer is different from the central potential or the GND potential of the voltage range of the analog output voltage output by the D / A converter, or the above-mentioned potential level. Potential or D /
By setting the power supply potential for driving the A converter,
It becomes easier to form the second capacitor for reducing the impedance of the reference power supply wiring described above.

In the above-mentioned D / A converter, it is desirable that the second capacitor is provided close to the reference power supply wiring side terminal of the switch element. According to the above configuration, the second capacitor is provided in the vicinity of the reference power supply wiring side terminal of the switch element, so that it is possible to enhance the impedance reduction effect of the reference power supply wiring.

The data driver of the driver monolithic display device of the present invention is characterized by having the D / A converter described in any of the above in order to solve the above problems.

According to the above configuration, by including the D / A converter according to any one of the above, it is possible to avoid the deterioration of the display quality as described above.

In the above data driver, D / A
The converter is Poly-Si or continuous grain boundary crystal S.
It is preferably monolithically formed on the substrate made of i.

According to the above configuration, the D / A converter is
By monolithically forming on a substrate made of Poly-Si or continuous grain boundary crystal Si, a driver monolithic display device can be reliably realized at low cost.

By the way, Japanese Unexamined Patent Publication No. 11-122111 discloses a method for discharging (resetting) the electric charge of the output setting capacity which constitutes the D / A converter. However, the invention described in the above publication is D /
The aim is to reduce the power consumption of the A converter and to operate at high speed. On the other hand, the present invention relates to precharging, not to discharging the charges accumulated in the first capacitance array, but to charging, which is different from the gist of the invention described in the above publication.

In Japanese Patent Laid-Open No. 11-122111, the wiring resistance (impedance) of the reference voltage wiring is also used.
Due to this, the charging of the input capacitance group (corresponding to the first capacitance array) is restricted, and the above-mentioned problem occurs.

[0061]

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 shows an embodiment of the present invention.
The following is a description with reference to FIG.

The D / A converter according to the embodiment of the present invention will be described below with reference to FIG. The difference from the conventional D / A converter shown in FIGS. 4 to 17 is that a capacitance Cp (second capacitance) for reducing the impedance of the reference power supply wiring (VM, VH, VL) is provided. In the embodiment of the present invention, other configurations are similar to the configurations shown in FIGS. 4 to 17, and therefore description thereof is omitted.

The capacitance Cp for impedance reduction is D /
Analog switches SWMn, S for capacitance charging / discharging control provided between the capacitance C _n (first capacitance array) for setting the analog output voltage that constitutes the A converter and the reference power supply line.
WMp, SWHn, SWHp, SWLn, and SWLp (switch elements) are provided as capacitors Cpm, Cph, and Cpl, respectively, close to (close to) the terminals on the reference power supply wiring side, and one of these terminals is the reference of the analog switch. It is connected to the power supply side terminal.

On the other hand, the other terminals (that is, the analog switches SWMn, SWMp, S for controlling the charging / discharging of the D / A converter capacity) of the respective capacities Cpm, Cph, Cpl.
As is apparent from FIG. 1, the terminals located on the side opposite to the terminals connected to WHn, SWHp, SWLn, and SWLp) are connected to the driver internal wiring GND set to a voltage different from that of the reference power source.

In FIG. 1, to simplify the explanation, 1 Bit
Only the amount is shown, but in reality, each capacitance Cpm, Cp
h and Cp1 are all D / A converters 41a _{1 to} 41a
Analog switches SWMn, SWMp, SWHn, SWHp, SW for charge / discharge control of all capacities constituting ₂₅₆
Capacitors Cp for reducing the impedance of the reference power supply wiring are provided in the vicinity of the terminals of the Ln and SWLp on the reference power supply wiring side.

That is, as shown in FIGS. 4 and 14, no matter how low the impedance of the output portion of the reference power source of the external driving circuit for driving the liquid crystal display device is suppressed, the inside of the driver (or the liquid crystal as shown in FIG. (Inside of display device) D / A converters 41a _{1 to} D / A converters 4 depending on wiring resistance R
The impedance of the driver internal wiring in the reference power supply wiring for supplying the charge to the capacitance C of 1a ₂₅₆ cannot be lowered.

However, according to the present embodiment, the impedance reduction arranged like a bypass capacitor in the internal reference power supply wiring of the D / A converter 41a of the data driver circuit (data driver) 41 of the driver monolithic liquid crystal display device. The charge / discharge charge of the D / A converter 41a is temporarily supplied from the capacitors Cpm, Cph, and Cpl described above by the capacitor Cp (second capacitor) for use.

As a result, in the present embodiment, the apparent internal reference power supply wiring impedance of the D / A converter 41a can be reduced, and sufficient charge can be supplied within the precharge period. It is possible to prevent display quality deterioration due to lateral crosstalk and D / A converter output voltage drop that occur because C (first capacitance array) and Cbus (external capacitance) cannot be charged to the VM level within the period. .

In this embodiment, the capacitors Cpm and Cp are
Analog switches SWMn, SWMp, SWHn, and SWH for charge / discharge control of the D / A converter capacity of h and Cpl
Terminals connected to p, SWLn, and SWLp (reference power supply potential)
The terminal located on the side opposite to is connected to the driver internal wiring GND set to the GND potential, but the terminal is not limited to the GND potential, and each of the capacitors Cpm, Cph,
Cpl analog switches SWMn, SWMp, SWH
n, SWHp, SWLn, and SWLp may be connected to a wiring set to a potential different from the terminal voltage (potential different from VM, VH, and VL in this embodiment) connected to the terminal voltage.

For example, the terminal on the side opposite to the analog switch side of the capacitance Cpm is connected to the GND wiring in FIG. 1, but if the wiring is other than VM, the capacitance Cpm functions as a bypass capacitance, so the VH wiring and VL. It may be connected to the wiring, or power supply wiring other than that shown in FIG. 1 may be prepared, and the wiring potential may be set to the center potential of the voltage range to be output by the D / A converter and connected to them. .

FIG. 2 shows a specific wiring example of the embodiment of the present invention. Hereinafter, each capacitance Cp described above
A concrete method of realizing m, Cph, and Cpl will be described. As is apparent from FIG. 2, the internal wiring forming the data driver circuit 41 uses several conductive layers and intersects each other with an insulating layer interposed therebetween (multilayer wiring).
By positively utilizing the intersection of these conductive layers, each capacitance Cp
m, Cph, Cpl can be realized simultaneously with other members without any additional steps.

In FIG. 2, a GND wiring is provided in the D / A converter 41a constituting the data driver circuit 41, and the capacitance (Cpm) is utilized by utilizing the intersection (cross portion) with the wiring.
Cph and Cpl are formed.

That is, as shown in FIG. 2A, the capacitors Cpm, Cph, and Cpl are located at the positions of the electrode portions 2c, Cp, Cph, and Cpl at positions close to the corresponding analog switches on the reference power supply wirings reaching the analog switches. It is formed of the electrode portion 2c and the different layer electrode portion 2d, and the dielectric layer 2e closely sandwiched between the electrode portion 2c and the electrode portion 2d. The electrode portion 2c is
It is provided with an electrode surface having an area corresponding to the required capacitance, and is provided in the same layer as the reference power supply wiring. On the other hand, the electrode portion 2d
Are provided in the GND wiring, which is in a different layer and intersects with the reference power supply wiring, at a position facing the electrode portion 2c and having substantially the same area. The dielectric layer 2e is formed of an insulating layer (for example, AlN) in the multilayer substrate.

Further, as shown in FIG. 3, each reference power supply wiring 2f connected to a corresponding analog switch,
Wirings 2i, 2j, 2k are arranged so as to intersect with respective reference power supply wirings different from 2g, 2h, and if necessary, an electrode surface similar to the above-mentioned electrode portion 2c and electrode portion 2d is formed. The capacitors Cpm, Cph, and Cpl may be formed by. At this time, for example, in order to electrically connect the wiring 2h and the wiring 2i, a through hole 2m is formed in the thickness direction in the dielectric layer 2e between them, and the wiring 2h is connected via the through hole 2m. The wiring 2i may be electrically connected.

As an application example of the D / A converter as described above, the above-mentioned D / A converter is Poly-type.
A digital driver monolithic type liquid crystal display device can be realized by monolithically forming (embedding) together with a driver that configures the liquid crystal display device with Si or continuous grain boundary crystal Si.

Although the liquid crystal display device has been described as an example of the display device in the above, it is necessary to convert a digital data signal into an analog data signal as in the case of gradation display, for example, a plasma display, a light emitting diode (LED). ) Display, electroluminescent display,
Obviously, it can be applied to a display device such as a laser display.

[0077]

As described above, the D / A converter of the present invention has the first capacitance array for setting the analog output voltage selected based on the bit data of the input digital data signal and the first capacitance. In a D / A converter having a reference power supply line for supplying charges to the array and a conversion period for determining an analog output voltage, an initial setting is made between a terminal of the first capacitance array and the reference power supply line. A switch element for controlling precharge to the capacitor is provided, and a second capacitor for reducing the impedance of the reference power supply wiring is provided in parallel with the reference power supply wiring up to the switch element.

Therefore, the above-mentioned configuration is provided with the second capacitance for reducing the impedance of the reference power supply wiring, so that when the D / A conversion is performed, the first capacitance to be charged during the precharge period. It is possible to supply sufficient charges to the array during the precharge period, and it is possible to prevent the display quality from deteriorating due to insufficient charge supply during the precharge period.

The data driver of the driver monolithic display device of the present invention has a configuration having any one of the above-mentioned D / A converters in order to solve the above-mentioned problems.

Therefore, the above-described structure has the above-described D / A converter, and as described above, it is possible to avoid the deterioration of the display quality.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a D / A converter according to a first embodiment of the present invention.

FIG. 2 is a specific example of the D / A converter,
(A) is a circuit diagram of a main part, and (b) is a schematic configuration diagram of a capacitance Cp for impedance reduction.

FIG. 3 is a modification of the D / A converter,
(A) is a circuit diagram of a main part, and (b) is a schematic configuration diagram of a capacitance Cp for impedance reduction.

FIG. 4 is an operation explanatory diagram (switch state A) of a conventional capacitance division type D / A converter.

FIG. 5 is a timing chart related to the operation explanatory diagram (switch state A).

FIG. 6 is another operation explanatory diagram (switch state B) of the D / A converter.

FIG. 7 is a timing chart relating to the operation explanatory diagram (switch state B).

FIG. 8 is a diagram for explaining still another operation of the D / A converter (switch state C).

FIG. 9 is a timing chart relating to the operation explanatory diagram (switch state C).

FIG. 10 is a diagram for explaining still another operation of the D / A converter (switch state D).

FIG. 11 is a timing chart relating to the operation explanatory diagram (switch state D).

FIG. 12 is a schematic explanatory diagram related to the operation of the D / A converter, in which (a) shows an example of a change in the potential of the bus line during the precharge period and the DAC period, and (b) shows a case where the above change occurs. The operation of each switch is shown.

13A and 13B are explanatory diagrams of charge charging for the analog output voltage of the D / A converter, wherein FIG. 13A shows charge charging Q _A during a precharge period, and FIG. 13B shows charge charging Q during a DAC period. _{Shows B.}

FIG. 14 is a schematic configuration diagram of a conventional digital driver monolithic liquid crystal display device.

FIG. 15 is an explanatory diagram of an input order of video data input to a data driver circuit of the liquid crystal display device.

FIG. 16 is a timing chart of drive signals input to the data driver circuit.

FIG. 17 is an explanatory diagram showing the operation of the sampling pulse generation circuit of the data driver circuit, where (a) is a block diagram and (b) is a timing chart of the operation.

FIG. 18 is an explanatory diagram of an example of occurrence of horizontal crosstalk during window display on the display unit of the liquid crystal display device,
(A) shows a window display, and (b) shows lateral crosstalk.

[Explanation of symbols]

C0, C1 capacitance (first capacitance array) Cbus1 capacitance (external capacitance) SWH, SWM, SWL, SWbus switch (switch element) Cph, Cpm, Cpl capacitance (second capacitance) VH, VL, VM Reference power supply wiring

Continued front page    F-term (reference) 2H093 NC02 NC11 NC24                 5C006 AA16 AF50 AF51 AF83 BB16                       BC12 BC20 BF26 BF34 EB05                       FA37                 5C080 AA10 BB05 DD03 DD28 EE29                       FF11 JJ03 JJ04 JJ05                 5J022 AB07 BA01 CB01 CE01 CF07                       CG01

Claims (8)

[Claims] 1. A first capacitor array for setting an analog output voltage selected based on bit data of an input digital data signal, and a reference power supply wiring for supplying electric charges to the first capacitor array. Then, the capacitance of the first capacitance array is selected based on the precharge period for precharging the initial capacitance to the first capacitance array and the external capacitance connected to the first capacitance array, and the capacitance of the first capacitance array based on the bit data. A D / A converter having a conversion period in which the generated capacitance is charged with an analog setting charge and the analog output voltage is determined by the capacitance ratio of the total capacitance of the first capacitance array and the external capacitance, And a reference power supply wiring, a switch element that controls precharge for the initial setting capacitance is provided, and the reference power supply until reaching the switch element D / A converter, wherein the second capacitor to lower the impedance of the reference power supply line in parallel with the line is provided. 2. The D / A converter according to claim 1, wherein the second capacitor is formed by a first conductive layer forming the reference power supply line and a second conductive layer separated from the first conductive layer by an insulating layer. A D / A converter characterized in that it is formed of a conductive layer, and a potential different from the reference power supply wiring potential is applied to the second conductive layer. 3. The D / A converter according to claim 2, wherein the potential level applied to the second conductive layer is set to the center potential of the voltage range of the analog output voltage. . 4. The D / A converter according to claim 2, wherein the potential level applied to the second conductive layer is set to the GND potential. 5. The D / A converter according to claim 2, wherein the potential level applied to the second conductive layer is set to a reference power source potential or a D / A converter driving power source potential different from the potential level. A D / A converter characterized in that 6. The D / A according to any one of claims 1 to 5.
In the converter, the second capacitor is provided in the vicinity of the reference power supply wiring side terminal of the switching element, and the D / A converter. 7. The D / A according to any one of claims 1 to 6.
A data driver for a monolithic display device, which has a converter. 8. The data driver for a driver monolithic display device according to claim 7, wherein the D / A converter is monolithically formed on a substrate made of Poly-Si or continuous grain boundary crystal Si. Data driver for monolithic display device.