JP2003008437A - Multi-input analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-input analog/digital converter that hierarchically couples multiplexers in multi-stages, selectively receives many analog signals and applies analog/digital conversion to the selected signals with an inexpensive configuration. SOLUTION: Outputs of (n+1) sets of 2nd stage multiplexers BO-Bn are connected to (n+1) sets of input terminals of a 1st stage multiplexer A, and an output of the multiplexer A is given to an analog/digital converter 1. A controller 2 generates a selection signal Sa to allow the multiplexer A to select one by one each of the input signals by each period of an input clock CL and generates a selection signal Sbj (j=0-n) of the multiplexer Bj so as to select an input signal to the multiplexer Bj whose output is selected synchronously with the timing when the multiplexer A starts selecting an output of the multiplexer Bj (j=0-n) on the basis of the selection signal Sa. Through the configuration above, since the multiplexer Bj reaches a state of selecting one input signal for the (n+1) period of the clock, a large settling time is not a problem and the multi-input analog/digital converter can employ inexpensive multiplexers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-input A / D converter for digitizing a large number of analog input signals.

[0002]

2. Description of the Related Art When there are a large number of measuring systems such as a gas meter and a control system that cyclically fetches the state quantities of a large number of measurement points of a controlled object in sequence, these measured values are also cyclical. In a measurement system, etc. that sequentially captures and records the data into a recording system, the outputs of the sensors and measuring instruments are sequentially selected by a multiplexer, and the multiplexer output is digitized by a single A / D converter, and then sent to a control system or measurement system. The method of multiplex transmission is used.

FIG. 2 shows the configuration of a "gas monitoring device" using the above A / D conversion method.
No. 324011. This device is an example in which multiplexers are connected in two stages.
First-stage multiplexer B21 closer to the converter C11
Is switched by the selection signal Sa to select one of the second-stage multiplexers B11 to B18. Then, the selected second-stage multiplexer is selected by a selection signal Sb (a common selection signal for the entire second-stage multiplexer).
By switching with, the analog input signals (gas sensor information) input to the second-stage multiplexer are sequentially selected and input, and input to the AD converter C11. That is, the multiplexer B11 is selected by the selection signal Sa, and in this state, the analog signals A1 to A8 are sequentially selected by the selection signal Sb. Next, the multiplexer B12 is selected by the selection signal Sa, and in this state, the analog signals A9 to A16 are sequentially selected by the selection signal Sb. Similarly, analog signals A1, A2, ... A64 are sequentially sampled and input to the AD converter.

Further, Japanese Laid-Open Patent Publication No. 5-110399 discloses a "multiplexer input switching device" having the same structure as that shown in FIG. The switching method is different. That is, in this known example, the multiplexer B21 of the first stage is switched every time one analog signal is input, and the multiplexers B11, B12 ... Of the second stage scan the input through the multiplexer B21 of the first stage. Switch to capture the next analog signal by the end. Thus
In the case of FIG. 4, analog signals A1, A9, ... A57, A
2, A10 ... A64 are input in this order to the AD converter C11. Further, in order to eliminate the switching time of the second-stage multiplexers B11, B12 ..., it is disclosed that the switching timing of the second-stage multiplexers is slightly shifted and controlled accordingly.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
According to the technique described in Japanese Patent Publication No. 1, a large number of analog signals can be digitized by one A / D converter, and a multiplexer is usually cheaper than providing an A / D converter for each input analog signal. Therefore, the cost of the entire device can be reduced. However, when the number of input analog signals is large and it is necessary to shorten the sampling cycle of each analog signal, the multiplexer as well as the A / D converter is required to operate at high speed.

In a switching circuit such as a multiplexer, its settling time, that is, the time required for the output to converge to an order enough to be regarded as a true value in response to an analog input, limits its operating speed. In order to increase the speed of the multiplexer, a multiplexer having a short settling time must be used, but the cost of one high-speed multiplexer may be higher than the cost of the high-speed AD converter. In the technique disclosed in Japanese Patent Laid-Open No. 6-324011, the first stage and the second stage need to have similar operating speeds.

On the other hand, in the method disclosed in Japanese Patent Laid-Open No. 5-110399, the second stage multiplexers B11, B are used.
12 ... If the number of inputs of the first stage multiplexer B21 is n, only one switching operation is required while n pieces of analog information are input to the A / D converter, and high speed operation is required for the first stage. Only the eye multiplexer B21 and the AD converter C11 allow an economical construction of a high-speed multi-input A / D converter. However, Japanese Patent Laid-Open No. 5-110399 discloses only the schematic operation of each multiplexer described above, and does not show the details of the specific control circuit configuration for realizing the operation or the switching timing of each multiplexer. . Further, when the number of inputs becomes large, it is necessary to connect multiple stages of multiplexers such as the third stage, the fourth stage, ...

An object of the present invention is to provide a switching control circuit of each multiplexer, which can be configured at high speed and at low cost, for digitizing a large amount of analog information by using multiplexers and A / D converters connected in multiple stages. Multi-input A / D
It is to provide a conversion device.

[0009]

According to the present invention, when p and q are integers of 2 or more, one of q analog signals is selected and output according to an input selection signal. Second-stage multiplexers, and one first-stage multiplexer that selects and outputs one of the p analog signals output from the p second-stage multiplexers according to the input selection signal , The first-stage multiplexer cyclically selects and outputs one of the p output analog signals from the p second-stage multiplexers one by one, and outputs the p second Each of the first stage multiplexers and each of the p second stage multiplexers cyclically select and output q analog signals one by one every p periods of the clock. A controller for generating that selection signals, in a multiple input A / D converter constituted from an A / D converter for digitizing takes in the output analog signal of the first stage multiplexer, the controller first
The selection signals supplied to the stage and second stage multiplexers are
The second stage multiplexer generates its output as a selection signal for switching the analog signal selected by the selected second stage multiplexer in synchronization with the timing at which the second stage multiplexer starts selecting one second stage multiplexer output. A multi-input A / D conversion device is disclosed.

In the multi-input A / D converter of the present invention, the controller counts the given clocks and cyclically outputs a value of 0 to p-1 every one clock. p counters, p q counters that count the clocks only when the enable signal is active, and cyclically output a value of 0 to q−1 every clock, and output values of the p counters And a decoder for controlling the enable signal of only the q counter corresponding to the output value thereof to be activated, and the output of the p counter is used as a selection signal to the first stage multiplexer, A multi-input A / D conversion device characterized in that each output of the q counter is output as each selection signal to the second stage multiplexer. Shimesuru.

Furthermore, in the multi-input A / D converter according to the present invention, the controller counts the given clocks and cyclically outputs a value of 0 to p-1 every one clock. The p counter that outputs a carry bit when the count value returns to 0 and this p counter
A q-counter that counts carry bits output from the counter and cyclically outputs a value of 0 to q-1, and an output value of the q-counter as an input, and the input value is synchronized with the clock and the input value is increased step by step. Q to shift
A shift register composed of a plurality of registers,
The count value output from the counter is used as a selection signal to the first stage multiplexer, and each output of q registers forming the shift register is used as a selection signal to the second stage multiplexer. Disclosed is a multi-input A / D conversion device.

Further, in the present invention, when P _{1 to} P _k and k are integers of 2 or more and P ₀ = 1, j =
For each of 2 to _k, one of the P _j analog signals is selected according to the input selection signal and the j-1 th
P _j-i-number of j-th multiplexer and, P ₁ inputs the selection signal to one of the analog signal output from the P ₁ amino second tier multiplexer to output as one input analog signal stage multiplexer 1-stage multiplexer for selecting and outputting according to the above, and P for every P _j-1 period of the clock given to each of j = 1 to k.
and a controller, each of the _j-1 or j-th stage multiplexer for generating a respective selection signal applied to the j-th stage multiplexer to sequentially selects and outputs cyclically one by one P _j pieces of input analog signals , A multi-input A / D conversion device comprising an A / D conversion device that takes in the output analog signal of the first stage multiplexer and digitizes the analog signal, The selection signal supplied to the j−1th stage multiplexer and the jth stage multiplexer is synchronized with the timing at which the j−1th stage multiplexer starts selecting one jth stage multiplexer output, and the jth stage multiplexer whose output is selected. Disclosed is a multi-input A / D conversion device characterized in that a selected analog signal is generated as a selection signal for switching.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. FIG. 1 is a block diagram showing a configuration example of a multi-input A / D conversion device according to the present invention. Generally, in a configuration in which multi-input signals are switched and input by a multi-stage multiplexer connection, one multiplexer in the first stage is provided at the closest position on the AD converter side and n2 multiplexer outputs in the second stage are selected. , Each second stage multiplexer selects n3 multiplexer outputs of the third stage ...
Each multiplexer in the final stage selects one of a plurality of inputs. The configuration of FIG. 1 is an example of two-stage connection, and each of the multiplexers B0 ... Bn of the second stage includes m + 1 input terminals I0 to Im, and output signals Bjout (j = 0) from their output terminals Z. To n) are input to the input terminals I0 to In of the first-stage multiplexer A. The output Aout of the multiplexer A is input to the A / D converter (ADC) 1 and digitized. The configuration of the multiplexer and the A / D converter shown in FIG. 1 is the same as that disclosed in the above-mentioned Japanese Patent Laid-Open No. 5-110399, but the multiplexers A, B0
To selection signals Sa, Sb0 ... Sb for performing switching control of Bn
n are output at different timings. Hereinafter, a configuration example of the controller 2 having such a function will be described.

FIG. 3 shows an example of the structure of the controller 2, which is applicable to the structure in which m = 3 and n = 3 in FIG. 2-bit counter 301, decoder 302,
The counter 301 includes two-bit counters 303 to 306. The counter 301 counts the clock CL, and the counter 303
The input to the enable signal end EN is "1"
Only when the clock CL is counted. The count output of the 2-bit counter 301 becomes the selection signal Sa of the multiplexer A and is input to the decoder 302. The output of the 2-bit counter 301 is "00" every clock.
It changes to "01", "10", and "11", and thereafter these four values are cyclically repeated. The decoder 302 decodes this 2-bit input, and outputs "00", "01", "1".
Z0, Z at the output end for 0 "or" 11 "input
"1" is output from 1, Z2, or Z3, and the corresponding 2
Enable signals (E
Output as N). Then, only the 2-bit counter connected to the decode output which has become the active level "1" has its count value updated in synchronization with the clock CL. The outputs of these 2-bit counters 303 to 306 are 2
Select signals Sb0 to Sb of the stage multiplexers B0 to B3
It is output as 3.

The selection signals Sa and Sb0 to Sb3 thus generated by the circuit of FIG.
When applied to B0-B3, each multiplexer selects the input signal corresponding to the value of the applied select signal. Since m = n = 3 in the present example, the multiplexer A,
All of B0 to B3 select one from the four input terminals I0 to I3, but regarding the relationship between the selected input and the selection signal, considering 2 bits of the selection signal as a binary number, it is a decimal number x = 0 to 0.
When represented by 3, it is assumed that the input Ix is selected with respect to the value x of the selection signal.

FIG. 4 is a time chart showing the operation of the multi-input A / D converter device of FIG. 1 when each multiplexer is controlled by the controller of FIG. In the first-stage multiplexer A, the selection signal Sa is switched by the counter 301 of FIG. 3 every cycle T of the clock CL, so that the input signal to the input terminal Ix is selected according to the value x of the selection signal Sa. ing. That is, the value of the selection signal Sa is “0”, “1”, “2”, “3”, in decimal.
Since it changes to “0”, “1”, ..., Input terminals I0, I2,
Input analog signals to I3, I0, I1 ... Are sequentially selected. On the other hand, the decoder 302 decodes the selection signal Sa, and when the value is x, only the output terminal Zx is made active “1”. Therefore, when x = 0 (Sa = “00”), the counter 303 displays x. = 1 (Sa = “01”), the counter 304, x = 2 (Sa = “10”), the counter 305, and x = 3 (Sa = “11”), the counter 306. The clock CL is counted and its output is changed. The outputs of the counters 303 to 306 change once every four clocks in this order, and the outputs are the selection signals Sb0 to Sb0 to the second stage multiplexers B0 to B3.
Since it is given as Sb3, multiplexers B0 to B
3 switches the selected input terminal once every four clocks.

However, the switching timing of the second stage multiplexer is set by the 2-bit counter 301 by the clock CL.
When a value of the selection signal Sa changes by one, the value of the selection signal Sa after the change is decoded by the decoder 302, and one of the 2-bit counters 303 to 306 is detected by the decoding result. Since it is enabled, the clock pulse counted by the enabled 2-bit counter becomes the clock pulse next to the clock pulse counted by the 2-bit counter 301. In the time chart of FIG. 4, the initial values of the counters 301 and 303 to 306 are all "0".
0 "), for example, at time t1, the counter 30
1 counts one clock pulse to select signal Sa
Is set to "01" and the multiplexer A selects the input signal of its input terminal I1, the decoder 302 decodes this selection signal Sa = "01" and sets the output terminal Z1 to "1", which enables the counter 304. Therefore, the pulse one clock later at the time t2 is the counter 30
4, the selection signal Sb1 changes from "00" to "01", and the multiplexer B1 receives its input terminal I
1 will be selected.

Here, each multiplexer switches the input terminal to be selected in accordance with the input selection signal, but after the selection signal is input and the input terminal is selected, the output value of the output terminal Z of the multiplexer is changed. It takes a so-called settling time to substantially match the input signal value applied to the input end. Therefore, it is preferable to select the timing of extracting the signal through each multiplexer and inputting it to the A / D converter 1 immediately before the input switching of each multiplexer is performed. In FIG. 4, for example, the selection signals of the multiplexers A and B0 at time t1. S0, Sb
At time so immediately before 0 changes, the input signal B0I0 to the input terminal I0 of the multiplexer B0 is taken out and sent to the A / D converter 1, and immediately before the selection signals Sa and Sb1 of the multiplexers A and B1 change at time t2. At time s1, the input signal B1I0 to the input terminal I0 of the multiplexer B1 is taken out and sent to the A / D converter. In this way, it is easy to control the signal extraction timing to the A / D converter,
As a result, the settling time of the first stage multiplexer A needs to be shorter than the clock cycle T, but the settling time of the second stage multiplexers B0 to B3 may be a little shorter than 4T. Thus, the multiplexer A needs to have a small settling time, that is, one capable of high-speed operation, while the multiplexers B0 to B3 can be inexpensive and have a large settling time.
In the above description, the 2-bit counters 301 and 303
Although all of to 306 are up counters, it goes without saying that these may be down counters.

FIG. 5 shows another example of the configuration of the controller 2 of FIG. 1, which is composed of a 4-bit counter 501 and 2-bit registers 502 to 505. The lower 2 bits (Q1, Q0) of the output of the 4-bit counter 501 are used as the selection signal Sa of the first stage multiplexer A, and the upper 2 bits (Q3, Q2) are input to the register 502. The outputs of the registers 502 to 504 are input to the registers 503 to 505, respectively, and form a shift register. The outputs of the registers are used as the selection signals Sb0 to sb3 of the second stage multiplexers B0 to B3. In this configuration, the 4-bit counter 50
The lower 2 bits of 1 output are the 2-bit counter 301 of FIG.
Similarly, the value is changed for each clock CL so that the outputs of the second stage and the multiplexers B0 to B3 are sequentially selected by the first stage multiplexer A, and the upper 2 bits are constant for 4 clocks. That is the sequential register 502
To 505 every one clock, and controls the selection signals of the multiplexers B0 to B3. Select signals Sa and Sb0 to sb3 generated by these operations
Switches each multiplexer at the same timing as shown in FIG. 4, and therefore the method and effect are the same as those of the circuit of FIG.

FIG. 6 shows another example of the configuration of the controller 2 of FIG. 1, which includes a sequencer or a processor (hereinafter simply referred to as a processor) 601 and a latch register 60.
2 to 606. The processor 601
Data DATAa and DATAb0 to DATAb3 are generated by a logical process equivalent to the circuit of FIG. 3 or FIG. 5, and these are generated as trigger signals TRGa and TRGb0 to TRGb.
The selection signals Sa and Sb0 to Sb3 are output to the respective multiplexers by latching them in the latch registers 602 to 606 by 3. According to this configuration, the processor 601
The output logical value and the output timing can be freely determined by the program inside, and it becomes easy to deal with the configuration change of the multistage multiplexer. The operation and effect are the same as in the case of FIGS. Although the clock CL is not explicitly shown in FIG. 6, when the sampling period of the A / D converter 1 may be determined by the processor 601, the clock period may be determined based on the internal clock thereof. Is. When the sampling period is given from the outside, the processing of the processor 601 is synchronized with this external signal.

As described above, the controller described with reference to FIGS. 3 to 5 is such that when m = 3 and n = 3 in FIG. 1, that is, four 4-input second-stage multiplexers are switched by the first-stage multiplexer. , The input signal is BxIy as shown in FIG.
There were 16 (x, y = 0 to 3). But this is 1
This is merely an example, and 32 analog inputs are possible when m = 7 and n = 3, for example. Generally, when each multiplexer in the second stage has m + 1 inputs and n + 1, and when the first stage multiplexer has n + 1 inputs, (m + 1) × (n + 1) inputs are possible. In this case, the number of the second stage multiplexers is n + 1, and the switching period is T (the sampling period of the A / D converter) of the first stage multiplexer.
N + 1 times as much. That is, the settling time required for the second-stage multiplexer is approximately n + 1 times that of the first-stage multiplexer. In any of these cases,
As described with reference to FIG. 4, in the second stage multiplexer, it is important that the read timing is controlled so that its output is read at a time close to the end of each switching cycle. The configuration of such a controller for general m and n values can be easily realized by any of the configuration methods shown in FIGS. 3, 5, and 6. For example, in the configuration method of FIG. 3, the 2-bit counter 301 is replaced with an n + 1 counter (a counter that counts from 0 when counting 0, 1, ..., N, and so on), and its output is used as a selection signal Sa, and the decoder 302 It is assumed that these n + 1 values are decoded,
The decode output sequentially selects n + 1 m + 1 counters (corresponding to the counters 303 to 306 in FIG. 3) and enables them, and the m + 1 counter output is selected signals Sb0 and Sb.
b1, ... Sbm + 1 may be set. Further, in the configuration method of FIG. 5, the 4-bit counter 501 is replaced with an n + 1 counter and an m + 1 counter that counts its carry signal.
The n + 1 counter output is used as the selection signal Sa, and the register 50
2 to 505 are replaced with n + 1 registers to form a shift register, and the output of each register is selected by a selection signal Sb while shifting the m + 1 counter output every one clock.
0, Sb1, ... Sbm. Further, in the configuration of FIG. 6, the configuration of the corresponding program and the latch register 603 are
It can be realized by setting m to 606.

In the above description, the output value of the p counter (p = n + 1 or m + 1) is "0", "1", "2", ... "P-1" in decimal every clock. It is said that the counter cyclically changes in this order. However, the order of the output values of this 1 cycle (= p clock) is not limited to the upper part, and p output values are always included once. Any circuit will do. For example, in the example of FIG. 3, the output value of each 2-bit counter (p = 4) may cyclically change to “0”, “3”, “1”, “2”. The order of the output values may be different for each p counter. The result of such an order change is that only the order of the input terminals selected by each multiplexer is changed, and (m + 1) × (n + 1) input terminals are generated every (m + 1) × (n + 1) clocks. It is always selected once.

Next, an example of the configuration of the multi-input A / D conversion device of the present invention when the multiplexers are connected in multiple layers in three stages will be described. 7 and 8 show examples of the configuration. FIG. 7 shows a multiplexer configuration and FIG. 8 shows an example of a controller circuit that performs switching control. First, second and third stages (A, B, C
The number of inputs of each multiplexer in each stage is 4 (n, m,
1 = 3). In this configuration, the timing control of the A stage and the B stage (first stage and second stage) may be exactly the same as in the case of FIG. 4, and is performed as shown by “A stage” and “B stage” in FIG.
On the other hand, the relationship of the control timings of the B stage and the C stage (the second stage and the third stage) may be basically regarded as the same as the relation of the A stage and the B stage. That is, the C stage is 4 times the l + 1 times the switching period of the B stage (here, 4 × T, T: clock period), that is, 4 × 4 ×.
The timing control may be performed so that it becomes T and the C stage is switched in response to the switching timing of each multiplexer of the B stage. At this time, the cycle in which the target input of the B stage is maintained is C
The last quarter of the cycle in which the corresponding input of the stage is selected
If the timing of the controller for switching control is adjusted so that it comes to the cycle, the settling time of each stage can be secured as long as possible, which is the best. For example, the analog input C00I1 shown at the end of FIG. 9 is from the I1 input of the C-stage multiplexer C00 to the I-input of the B-stage multiplexer B0.
It is indicated that it is connected to the A / D converter via the 0 input and the I0 input of the A-stage multiplexer.

FIG. 8 shows the third stage multiplexer Cyz (Y, Z = 0 to 0) as shown in the time chart of FIG.
Among the 3), multiplexers Cy0, Cy1, Cy2, Cy whose outputs are connected to the second stage multiplexer by
The controller circuit part for switching 3 is shown. This configuration example is similar to the circuit shown in FIG. 3, but the input to the decoder 801 is the selection signal Sby for the multiplexer by, and the decoded output is the 2-bit counter 80.
2 to 805 are used as enable signals, each output of the 2-bit counters 802 to 805 is a multiplexer Cyz.
The selection signal Scyz (Z = 0 to 3) to (Z = 0 to 3) is obtained. This operation is the same as that of FIG. 3 except that the input to the decoder 801 is changed, and switching is performed according to the time chart as shown in FIG. In the switching controller, the circuit of FIG. 8 has the selection signals Sb0 to Sb of FIG.
3 is provided as an input and operates similarly to FIG. 3, but as a result, the settling time required for the multiplexer Cyz is the second stage multiplexer By in this example.
It should be about 4 times as shown in. The switching control circuit of the third stage multiplexer is not limited to that shown in FIG.
It is obvious that the circuit can be configured similarly to the circuits shown in FIGS. 5 and 6. Further, even if multiple stages of multiplexers such as 4 stages, 5 stages, etc. are connected, only one multiplexer in the first stage is required to have high speed as high as the sampling cycle of the A / D converter. Similarly, it is easy to implement a switching control circuit that can be used with a low-speed multiplexer.

The controller circuits for switching multiplexers, which are the features of the present invention, have been described above. Here, the switching operation by these circuits will be compared with the prior art in detail. First, in the technique disclosed in Japanese Patent Laid-Open No. 6-324011 shown in FIG.
When the second stage multiplexer is selected, the selected multiplexer switches the input every one clock, and after that, the first stage multiplexer selects the next second stage multiplexer. The same operation is repeated thereafter, but the same selection signals are always applied to the second-stage multiplexers B11 to B18. Now, in the configuration of FIG. 1, m
= N = 3, and a time chart when these multiplexers are switching-controlled by the method of the above-mentioned Japanese Patent Laid-Open No. 6-324011 is shown in FIG. As can be seen from this figure, the switching cycle of the second stage multiplexer By is equal to the sampling cycle T of the A / D converter. Therefore, the second
The settling time of all the stage multiplexers B0 to B3 must be T or less, and high-speed analog-digital conversion is required. Also, the first stage multiplexer A
However, the time until the first input data (input signals B0I0 and B1I0 in FIG. 10) is read after the switching is still T.
Since it is the following, characteristics equivalent to those of the second stage multiplexer are required. Considering here the configuration example of FIG. 2, a multiplexer B2 having eight inputs in both the first and second stages
64 gas sensor information A using 1, B11 to B18
Connect 1 to A64 to one A / D converter C11 64
It is a chA / D conversion system. If the analog data to be handled is relatively low speed as shown in Japanese Patent Laid-Open No. 6-324011, this connection and the control method also enable multi-input A / D.
Although the converter can be economically realized, for example, if the analog input information is sound wave data of about 10 KHz, sampling of 160 KHz / information (in the case of 16 division sampling) is necessary to recognize the frequency, and In order to input 64 pieces of information (64 channels), about 10 MHz (160 KHz × 64) is required as the sampling frequency level of the A / D converter. That is, T = 100 ns, and it becomes necessary to operate all the multiplexers in each stage at a cycle of 100 ns. Currently 10 to 14 MHz 10MHz class A / D converter
Although it costs about 90,000 yen, a high-speed 8-channel multiplexer that satisfies the total settling time of 100 ns when connected in two stages (actually, each settling time of 50 ns or less is required and 20 to 30 ns is actually required considering various loss times). Is difficult to obtain, and even if you can get it, 10
It is very expensive, about 10,000 yen, and it is difficult to put it into practical use as a system.

On the other hand, according to the present invention, for example, in the first stage, 4
By using the input high-speed multiplexer and the four 16-channel low-speed multiplexers in the second stage, it is possible to realize input switching for 64 channels of sound wave data under the same conditions as described above. At this time, A /
The sampling frequency of the D converter is 10 MHz (T = 10
0 ns), the first stage multiplexer is 10 MHz (effective 5
(0 ns settling time), the second stage multiplexer can satisfy the required specifications if it has a performance of 2.5 MHz (settling time of slightly less than 400 ns). In terms of price, the first stage multiplexer is about 25,000 yen,
The cost of the second stage multiplexer is about 50 thousand yen, and the total number of parts is reduced, so that the performance of both price and compactness of mounting is greatly improved. As described above, the multiplexer tends to rapidly become expensive in response to the demand for high-speed performance and the demand for an increase in the number of channels, and the present invention is effective in constructing a highly practical system by absorbing its characteristics. .

Further, if the present invention is applied, each analog information can be kept waiting in the second stage multiplexer for T × n (n: the number of inputs of the first stage multiplexer) cycles at all times. There is also an effect that the total settling time of the first and second stages can be saved. FIGS. 11 and 12 are explanatory views of this. For example, taking the analog input signal B1I1 of FIG. 4 as an example, the multiplexer B1 is switched at time t2 (FIGS. 4 and 11), and the output voltage V thereof changes from time to time. It rises and approaches the value B1I1 of the input signal. The settling time of the multiplexer B1 is about 4T.
If the output voltage V is substantially close to the input value B1I1 after the lapse of 3T from the switching time t2, the multiplexer A is switched to select the output of the multiplexer B1 at this time t3. The multiplexer A can start the settling operation with respect to the analog input value which is close to the true value. Therefore, if the condition that the multiplexer A has a settling time smaller than T is satisfied, the total settling time of the first and second stage multiplexers is 4T or less.
As can be seen from this description, the multiplexer B1 is 4T
Practical use is possible if a slightly shorter (faster) settling time characteristic is used.

On the other hand, in the technique of Japanese Patent Laid-Open No. 6-324011, when the multiplexer B1 is switched to time t3 (FIGS. 10 and 12) as shown in FIG. After the output voltage V starts to rise and T has elapsed, the input value B1 is almost reached.
It becomes I1. In this case, the multiplexer A input is at time t3.
As compared with the case where the input value itself is input at the time of switching as in the case of FIG. 11, the actual output value rises slowly even if the settling time of the multiplexer A is the same. For example, as shown in FIG. 12, a dead time of α occurs (it requires a settling time of t + α). In this situation, multiplexer B
The same is true for any input of 0 to B3, and the first and second
This means that higher speed is required for both stage multiplexers.

By changing the switching method of Japanese Patent Laid-Open No. 6-324011, the selection signals Sa and Sb are exchanged, the second stage multiplexers are switched simultaneously by the selection signal Sa, and the first stage multiplexers are selected by the selection signal Sb. A switching method of changing so as to control switching is also conceivable. The operation at this time is as shown in FIG. 13, and the selection order of the analog input signals is the same as that of the present invention, but it is understood that the effect of the present invention cannot be obtained by simply replacing the selection signal. That is, for the input signals B0I0, B0I1 ...
Both 0 and A require settling time T or less, similarly multiplexer 2 requires 2T or less, multiplexer B2 requires 3T or less, and only multiplexer B3 requires the same settling time 4T or less as in the present application. It In the present invention, the switching timing of each of the second-stage multiplexers is individually controlled so that the settling time of any second-stage multiplexer is set to 4T or less. Incidentally, the above-mentioned Japanese Patent Laid-Open No.
No. 110399 describes that the switching timing of each of the second stage multiplexers is shifted in order to remove the switching overhead, but what kind of control means specifically controls how and how timing is controlled? It does not disclose anything, nor does it describe means for optimizing settling time.

Next, an application example of the multi-input A / D converter of the present invention will be described. FIG. 14 is a block diagram showing an application example thereof, and shows an example of an interface for fetching the output of the multi-input A / D converter into a processor such as a controller system via an I / O bus. The configuration will be described in detail below. However, here, the multi-input A / D conversion device of the present invention is a second-stage multiplexer 1401 which is a combination of the first-stage and second-stage multiplexers when m = n = 3 in FIG.
And a controller 1403 for switching and controlling this, A /
The controller 140 comprises a D converter 1402.
3 may be any of the configurations shown in FIGS. 3, 5, and 6. Figure 1
4, the A / D converter 1402 uses the clock ADC from the address controller (ADCCTL) 1404.
In response to CLK (sampling clock), the analog information selected by the two-stage multiplexer 1401 is taken into the input end I, digitally passed and output from the output end Z. The address controller 1404 is an A / D
The timing signal for controlling the operation of the converter 1402 is generated, but in this example, the same clock CL as the timing clock for multiplexer switching is sampled to the A / D converter 1402 directly or via the buffer BF. It is output as a clock. A buffer BF is provided to provide an appropriate delay, and this delay causes 2
By canceling some percentage of the delay when the input signal passes through the stage multiplexer 1401, it is possible to recover the settling time associated with the switching of the selection signal to some extent (gain the time required for settling).

Digital output data from the A / D converter 1402 is input to the data input terminal DT-A of the dual port RAM (or register file) 1405, and the address write clock WTCLK indicated by the address signal DPRADR from the controller 1406 is used. It is stored in response. The controller 1406 has selection signals Sa and Sb3 from the controller 1403 for controlling the multiplexer.
(Basically, any of Sb0 to Sb3 may be used) is latched in the flip-flop FF in synchronization with the address clock ADCCLK, and the address signal DPRADR
Is being generated. Also, the write clock WTCLK is
Data to the dual report RAM 1405 (DT-
A) and the address (ADR-A) need to be timing-controlled so that they are output when they are correctly established. In this example, from the address clock ADCCLK to the buffer BF
The write clock WTCLK is generated via
This buffer is used for timing logic and delay (ADC
(To compensate for the conversion delay of),
Also, a configuration without a buffer may be used. With these configurations, it is possible to construct a system in which analog information input one after another by the multistage multiplexer is sequentially converted into digital information and sequentially stored in corresponding storage locations.

The other port (port B) of the dual report RAM 1405 has at least a readable function, and if a bus interface circuit 1407 is provided and connected to a system bus such as an I / O bus 1408, it will be connected to that bus. Connected processor board 1409,
From 1410 or the like, read access can be performed as a shared resource like memory access. The configuration of the dual report RAM (or register), data access via the I / O bus, etc. are known techniques, and their details are omitted. And if you use the multi-input ADC board as shown here as a controller or intelligent measurement system for some process, you can carry out advanced arithmetic processing, real-time control processing, experiments and analysis in real time while handling a large amount of analog information at high speed. Hybrid processing, high-speed feedback control processing based on a lot of real-time information, etc. can be realized.

[0033]

According to the present invention, a multi-input A / D converter for digitizing a large number of high-speed analog information can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a multi-input A / D conversion device according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional multi-input A / D conversion device.

FIG. 3 is a circuit block diagram showing a configuration example of the controller of FIG.

4 is a time chart showing a multiplexer switching operation when the controller of FIG. 3 is used.

5 is a circuit block diagram showing another configuration example of the controller of FIG. 1. FIG.

FIG. 6 is a circuit block diagram showing still another configuration example of the controller of FIG.

FIG. 7 is a configuration example of a multi-input A / D conversion device when the multiplexer has a three-stage configuration.

8 is an example of a controller circuit for switching a third stage multiplexer of the three-stage configuration multiplexer shown in FIG.

9 is a time chart showing the operation of the apparatus of FIG.

10 is a time chart showing a multiplexer switching operation in the conventional apparatus of FIG.

11 is an explanatory diagram of settling characteristics of a multiplexer in the device of FIG.

12 is an explanatory diagram of settling characteristics of a multiplexer in the apparatus of FIG.

13 is a time chart showing the switching operation when the selection signals of the first-stage and second-stage multiplexers are replaced in the conventional device of FIG.

FIG. 14 is an example of an interface between the multi-input A / D converter of the present invention and a processor.

[Explanation of symbols]

1 A / D converter 2 controller 301 2-bit counter 302 decoder 303-306 2-bit counter 501 4-bit counter 502 to 505 registers 601 processor 602 to 606 latch register 801 decoder 802-805 2-bit counter A, B0-Bn multiplexer C00-C33 multiplexer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takao Konno             603 Jinmachi-cho, Tsuchiura-shi, Ibaraki Japan Co., Ltd.             Tate Manufacturing Industrial Machinery Systems Division F term (reference) 5J022 AA01 BA05 BA06 CD03 CE01                       CE05 CF08

Claims (4)

[Claims] 1. When p and q are integers of 2 or more, p second stage multiplexers for selecting and outputting one of q analog signals according to an input selection signal, One first stage multiplexer that selects and outputs one of the p analog signals output from the p second stage multiplexers according to the input selection signal, and one cycle of the given clock The first stage multiplexer cyclically selects and outputs the p output analog signals from the p second stage multiplexers, one by one, for each
And a first stage multiplexer and p second stage multiplexers so that each of the p second stage multiplexers cyclically selects and outputs q analog signals, one for each p period of the clock. And a controller for generating a selection signal to be given to each of the
In a multi-input A / D conversion device including a D converter, the controller starts selection of one second-stage multiplexer output from the first-stage multiplexer by a selection signal given to the first-stage and second-stage multiplexers. A multi-input A / D conversion device, characterized in that its output is generated as a selection signal for switching the analog signal selected by the selected second stage multiplexer in synchronization with the timing. 2. The multi-input A / D conversion device according to claim 1, wherein the controller counts the given clock and cyclically outputs a value of 0 to p−1 every one clock. p counters, p q counters that count the clocks only when the enable signal is active, and cyclically output a value of 0 to q−1 every clock, and output values of the p counters And a decoder for controlling the enable signal of only the q counter corresponding to the output value thereof to be activated, and the output of the p counter is used as a selection signal to the first stage multiplexer, Multi-input A characterized in that each output of the q-counter is output as each selection signal to the second stage multiplexer.
/ D converter. 3. The multi-input A / D conversion device according to claim 1, wherein the controller counts the given clock and cyclically outputs a value of 0 to p−1 every one clock. In addition, the p counter that outputs a carry bit when the count value returns to 0 and the carry bit output from this p counter are counted to 0.
A q counter for cyclically outputting the value of ~ q-1;
A shift register composed of q registers each of which receives the output value of the q counter and shifts the input value one stage at a time in synchronization with the clock, and outputs the count value output from the p counter to the first register. A multi-input A, wherein each of the outputs of the q registers forming the shift register is used as a selection signal to the second stage multiplexer.
/ D converter. 4. When P _{1 to} P _k and k are integers of 2 or more and P ₀ = 1 and for each of j = 2 to k, each one of P _j analog signals. P _j-i which selects one of the input signals according to the input selection signal and outputs it as one input analog signal of the j-1 th stage multiplexer
One j-th stage multiplexer and _{one first} P ₁ analog signal output from the P ₁ second stage multiplexer are selected and output according to the input selection signal.
Each of the stage multiplexers and P _{j−1 j-} th stage multiplexers outputs P _j input analog signals every P _j−1 period of the clock provided for each of j = 1 to k.
The j-th output should be selected cyclically one by one and output.
A multi-input A / D conversion device comprising a controller for generating a selection signal to be supplied to each of the stage multiplexers and an A / D conversion device for capturing and digitizing an output analog signal of the first stage multiplexer. For each of j = 2 to k, a selection signal to be supplied to the j−1th stage multiplexer and the jth stage multiplexer is
The stage multiplexer generates the output as a selection signal for switching the analog signal selected by the selected j-th multiplexer in synchronization with the timing of starting selection of one j-th multiplexer output. Multi-input A / D conversion device.