CN211791464U

CN211791464U - FPGA digital filter

Info

Publication number: CN211791464U
Application number: CN202020401972.2U
Authority: CN
Inventors: 王孝洪; 江树人; 周鑫东; 张波; 黄淇松
Original assignee: South China University of Technology SCUT
Current assignee: Foshan Hongwei Technology Co ltd; Guangzhou Hongwei Technology Co ltd
Priority date: 2020-03-26
Filing date: 2020-03-26
Publication date: 2020-10-27
Anticipated expiration: 2030-03-26

Abstract

The utility model discloses a FPGA digital filter, which comprises a triple integrator, a register group, an add-subtract combinational logic circuit, a timer and a data output circuit; the input end of the triple integrator is connected with an input signal, the output end of the triple integrator is connected with the input end of the register group, the output end of the register group is connected with the input end of the addition and subtraction combinational logic circuit, and the output end of the addition and subtraction combinational logic circuit is connected with the data output circuit; the register group comprises four registers connected in series, high-frequency clock signals are respectively connected with a timer, a data output circuit, the register group and a triple integrator, output signals of the timer are respectively connected with enabling ends of the four registers, and data are stored in the register group at the same time interval. The utility model discloses the wave filter resource occupies fewly, and the output can not have great delay.

Description

FPGA digital filter

Technical Field

The utility model relates to a digital filter field, concretely relates to FPGA digital filter.

Background

Sinc3 digital filters are widely used in servo control systems. Bandwidth is an important measure of servo system response speed and process capability. To improve the bandwidth, each delay element of the servo control period is reduced. The sinc3 digital filter, which is often used by servo, is also one of the sources of sample delay. There are two types of digital filters commonly used today.

The first is an IP core of FPGA provided by ADI company, which adopts a method of integration first and differentiation later.

The transfer function g (z) is decomposed as follows:

as can be seen, the digital filter can be divided into 1 pure proportion segment and 3 discrete accumulators 1/(1-z)^-1) And a differentiator (1-z) with 3 intervals DR equal to 32 sampling periods^-DR) Are connected in series to obtain.

The MCLKIN is adopted as an input clock of the FPGA circuit, and the input clock is generally 20 MHZ. WORD _ CLK is a decimated clock divided by MCLKIN software with a period of 32 times DR of MCLKIN. Assuming MCLKIN has a frequency of 20MHz and a period of 50ns, WORD _ CLK has a period of 1600ns, i.e., 1.6 us. Since registers are often used as sequential elements in FPGAs. There is a one beat lag (i.e., a one clock cycle delay in the transfer) in the inter-register transfer.

Implementation of such a digital filter would result in an additional increase of the pure delay time by a factor of 3 MCLKIN DR. If the ideal delay caused by the transfer function is added:

τ_Mfor MCLKIN cycle

Then at a decimation rate of DR-32, its total propagation delay (ideal transfer function propagation delay + designed digital controller delay) is 7.15 us. From the multiple relation, when DR is 64, the delay is 14us or more. This delay has a significant impact on the performance of the servo real-time control system (typically with a control frequency of 10 k).

As shown in fig. 4, the second method is a conventional FIFO (first in first out) transfer function implementation method (abbreviated as FIFO filter), which also has a significant disadvantage that the number of registers used is too large, when DR is 32, 3 DR is 96 register groups are needed, each register group in the IP core is generally composed of 37 registers, so that 96, 37, 3552 registers are used. When the DR extraction rate is high, the FPGA resource is greatly occupied.

In summary, the sinc3 filter of the original ADI company of the first method has a simple structure, but causes an excessive pure delay, and in the servo system, the pure delay in the loop has a great influence on the servo bandwidth. In the second method, the FIFO sinc3 filter does not cause extra pure delay, but causes large resource occupation, which is not favorable for reducing the production cost.

SUMMERY OF THE UTILITY MODEL

In order to overcome the shortcoming and the deficiency that prior art exists, the utility model provides a FPGA digital filter has the advantage of low sampling delay and low resource occupancy.

The utility model adopts the following technical scheme:

an FPGA digital filter comprises a triple integrator, a register group, an add-subtract combinational logic circuit, a timer and a data output circuit;

the concrete connection is as follows:

the input end of the triple integrator is connected with an input signal, the output end of the triple integrator is connected with the input end of the register group, the output end of the register group is connected with the input end of the addition and subtraction combinational logic circuit, and the output end of the addition and subtraction combinational logic circuit is connected with the data output circuit;

the register group comprises four registers connected in series;

the high-frequency clock signal is respectively connected with a timer, a data output circuit, a register group and a triple integrator, the output signal of the timer is respectively connected with the enabling ends of the four registers, and data are stored in the register group at the same time interval.

The triple integrator is formed by three accumulators connected in series.

The addition and subtraction combinational logic circuit comprises two adders with three inputs and a four-input addition and subtraction device.

The output ends of the two registers are connected with two three-input adders, and are amplified by three times and input into a four-input adder-subtractor together with output signals of the other two registers to obtain an output result.

The counter controls the time interval of data storage to be DR x T, and T is the period of the high-frequency clock signal.

A method for realizing FPGA digital filter includes using high frequency clock as driving clock by triple integrator to output accumulated signal value, connecting back-stage output of triple integrator to input end of series register set, using high frequency clock as driving clock by series register set, storing data in four registers of series register set in sequence by queue mode under control of enabling signal with equal time interval sent out by counter, inputting output signal of four registers of register set to addition-subtraction logic circuit and finally obtaining final filtered signal from addition-subtraction logic circuit.

The utility model has the advantages that:

the utility model discloses the wave filter resource occupies fewly, uses high frequency clock signal MCLKIN to export, and clock after not the frequency division, the output can not have great delay.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a structural connection diagram of an embodiment of the present invention;

FIG. 3 is a graph comparing the performance of the present invention with that of the prior art;

fig. 4 is a schematic diagram of a FIFO filter structure in the prior art.

Detailed Description

The present invention will be described in further detail with reference to the following examples and drawings, but the present invention is not limited thereto.

Examples

As shown in fig. 1 and fig. 2, an FPGA digital filter includes a triple integrator, a register set, an add-subtract combinational logic circuit, a timer, and a data output circuit;

the concrete connection is as follows:

the register group comprises four registers connected in series;

The triple integrator is formed by three accumulators connected in series.

The four registers are X0, X1, X2 and X3, wherein the outputs of the four registers are used as the inputs of the add-subtract logic circuit, wherein the outputs of X1 and X2 need to be increased by 3 times, so that the X1 and X2 signals are input to two 3-input adders respectively, and the obtained results are X1+ X1+ X1 ═ 3 × X1, and X2+ X2+ X2 ═ 3 × X2 respectively. And inputting the two results, X0 and X3 into a four-input adder-subtractor to obtain the final result, namely OUTPUT (OUTPUT), X0-3X 1+ 3X 2-X3.

The counter controls the time interval for data storage to be DR T, and the DR is generally 32.

The utility model discloses a working process does:

the triple integrator takes a high-frequency clock as a driving clock and outputs an accumulated signal value, the rear-stage output of the triple integrator is connected to the input end of a series register group, the series register group takes the high-frequency clock as the driving clock, data are successively stored in four registers of the series register group in a queue mode under the control of enabling signals with equal time intervals sent by a counter, output signals of the four registers of the register group are all input to an add-subtract logic circuit, and finally, a signal after final filtering is obtained through the output of the add-subtract logic circuit.

The utility model discloses the wave filter resource occupies rarely, adopts high frequency clock signal MCLKIN to export, and clock after not the frequency division, the output can not be by great delay.

As shown in fig. 3, the filter of the present invention compares the performance with two filters commonly used in the prior art, the hysteresis of the IP core of ADI company is most obvious, the output of the FIFO filter is closest to the ideal transfer function, and the filter of this document is equivalent to the FIFO filter being maintained at interval of DR × T of zero order.

The output clock of the output register DATA of the method is driven by a high-frequency signal MCLKIN (instead of using the divided WORD _ CLK), which is equivalent to that the DATA is output in the next MCLKIN period every time the value in the X0-3 register group changes. The delay of 3 x T cycles relative to the original ADI company is greatly improved. The registers used are only 4 groups instead of 3 × DR groups, which occupies less resources compared with the conventional FIFO method.

The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be equivalent replacement modes, and all are included in the scope of the present invention.

Claims

1. An FPGA digital filter is characterized by comprising a triple integrator, a register group, an addition and subtraction combinational logic circuit, a timer and a data output circuit;

the concrete connection is as follows:

the register group comprises four registers connected in series;

2. The FPGA digital filter of claim 1 wherein said triple integrator is comprised of three series accumulators.

3. The FPGA digital filter of claim 1 wherein said add-subtract combinational logic circuit comprises two three-input adders and a four-input add-subtract.

4. The FPGA digital filter of claim 3, wherein the output terminals of two registers are connected to two three-input adders, and the three-input adders are amplified by three times and input the amplified signals and output signals of the other two registers to a four-input adder-subtractor to obtain an output result.

5. The FPGA digital filter of claim 1 wherein the counter controls the storage of data for a time interval DR x T, T being the period of the high frequency clock signal.