JP2003007928A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003007928A
JP2003007928A JP2001194255A JP2001194255A JP2003007928A JP 2003007928 A JP2003007928 A JP 2003007928A JP 2001194255 A JP2001194255 A JP 2001194255A JP 2001194255 A JP2001194255 A JP 2001194255A JP 2003007928 A JP2003007928 A JP 2003007928A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor element
hole
heat dissipation
gel member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001194255A
Other languages
Japanese (ja)
Inventor
Mikio Naruse
幹夫 成瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2001194255A priority Critical patent/JP2003007928A/en
Publication of JP2003007928A publication Critical patent/JP2003007928A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device superior in heat dissipation performance from a semiconductor module to a cooler. SOLUTION: The semiconductor device is provided with the semiconductor module M where bus bars 11 and 12 on which semiconductor elements 21 and 22 are mounted by face-bonding, a bus bar 13 are integrated by a resin frame 1, and the semiconductor element 22 is sealed by filling an area S where semiconductor element is arranged with a gel member 4 so as to harden it; and with the cooler 2 where the semiconductor module M is fixed across a heat radiating sheet 3. A hole 100 passing from the area S where semiconductor element is arranged to a part facing the heat radiating sheet 3 of the semiconductor module M is formed in the connection part 1c of the resin frame 1. Consequently, the gel member 4 of the area S where semiconductor element is arranged intrudes into the gap among the bus bar 11, the bus bars 12 and 13 and the heat radiating sheet 3 through the hole 100.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子が実装
された複数のバスバーを樹脂モールドにより一体化する
とともに半導体素子をゲル等の封止剤で封止する半導体
モジュールを、放熱シートを挟んで冷却器に取り付けた
半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module in which a plurality of bus bars on which semiconductor elements are mounted are integrated by resin molding and the semiconductor elements are sealed with a sealing agent such as gel with a heat radiating sheet sandwiched therebetween. The present invention relates to a semiconductor device attached to a cooler.

【0002】[0002]

【従来の技術】トランジスター、IGBT、サイリスタ
ーなどの半導体素子を用いて直流電力を交流電力に変換
するインバーターや、交流電力を直流電力に変換するコ
ンバーターなどの半導体装置が知られている。これらの
半導体装置では、電力が大きくなるほど半導体素子から
の放熱量が多くなり、半導体素子に冷却器を取り付けて
冷却を行う必要がある。
2. Description of the Related Art Semiconductor devices such as an inverter for converting DC power into AC power by using semiconductor elements such as transistors, IGBTs and thyristors, and a converter for converting AC power into DC power are known. In these semiconductor devices, the amount of heat released from the semiconductor element increases as the power increases, and it is necessary to attach a cooler to the semiconductor element for cooling.

【0003】例えば、IGBTとダイオードとを用いて
直流P,Nを交流U,V,Wに変換する電力変換装置、
すなわちインバータの電力変換回路では、半導体素子
(IGBT、ダイオード)はハンダをによってバスバー
に直接接続されている。バスバーとしては、例えば、銅
板を剪断加工したものが用いられる。半導体素子が設け
られたバスバーは互いに間隔を設けて配置され、電気的
絶縁を確保するために樹脂でモールドされて一体とされ
る。通常、半導体素子の発熱対策として、樹脂で一体と
されたバスバーは放熱シートを介してヒートシンクに接
続され、各バスバーの裏面(すなわち、半導体素子が設
けられていない面)と放熱シートとは面接触する構造と
なっている。
For example, a power converter for converting DC P, N into AC U, V, W using an IGBT and a diode,
That is, in the power conversion circuit of the inverter, the semiconductor element (IGBT, diode) is directly connected to the bus bar by soldering. As the bus bar, for example, a sheared copper plate is used. The bus bars provided with the semiconductor elements are arranged at intervals from each other, and are molded with resin to be integrated so as to ensure electrical insulation. Normally, as a measure against heat generation of semiconductor elements, the bus bar integrated with resin is connected to the heat sink via a heat dissipation sheet, and the back surface of each bus bar (that is, the surface on which the semiconductor element is not provided) and the heat dissipation sheet make surface contact It has a structure that

【0004】[0004]

【発明が解決しようとする課題】しかしながら、バスバ
ーおよび放熱シートの表面は、ミクロ的に観察すると微
細な凹凸を有しており、厳密には面接触ではなく点接触
の集まりと見なすことができる。そして、両者が接触し
ていない隙間には熱伝導率が小さい空気が介在すること
になる。その結果、バスバーからヒートシンクへの熱伝
導性が低下するという問題があった。
However, the surfaces of the bus bar and the heat radiating sheet have fine irregularities when observed microscopically, and can be strictly regarded as a collection of point contacts rather than surface contacts. Then, air having a small thermal conductivity is present in the gap where they are not in contact with each other. As a result, there is a problem that the thermal conductivity from the bus bar to the heat sink decreases.

【0005】本発明の目的は、放熱シートを挟んで半導
体モジュールを冷却器に取り付ける半導体装置におい
て、半導体モジュールから冷却器への放熱性能に優れた
半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device in which a semiconductor module is attached to a cooler with a heat-dissipating sheet sandwiched between the semiconductor module and the cooler.

【0006】[0006]

【課題を解決するための手段】発明の実施の形態を示す
図2,3,8および9に対応付けて説明する。 (1)図2および図3に対応付けて説明すると、請求項
1の発明は、半導体素子21,22が面接合により実装
された複数のバスバー11,12とバスバー13とを樹
脂モールド部材1により一体化し、半導体素子配設領域
Sに液状封止剤4を充填して硬化させることにより半導
体素子21,22を封止した半導体モジュールMと、半
導体モジュールMが放熱シート3を挟んで固定される冷
却器2とを備える半導体装置に適用され、半導体素子配
設領域Sから半導体モジュールMの放熱シート3に対向
する部分へと貫通する孔100を少なくとも一つ形成し
たことにより上述の目的を達成する。 (2)請求項2の発明は、請求項1に記載の半導体装置
において、孔100を、半導体素子配設領域Sに含まれ
る樹脂モールド部材1cに形成したものである。 (3)図8に対応付けて説明すると、請求項3の発明
は、請求項2に記載の半導体装置において、樹脂モール
ド部材1cに高さHが半導体素子よりも高い突出部11
0を形成し、突出部110に孔100を形成したもので
ある。 (4)図9に対応付けて説明すると、請求項4の発明
は、請求項3に記載の半導体装置において、突出部11
0の高さHを封止剤4の表面よりも高くしたものであ
る。
An embodiment of the invention will be described with reference to FIGS. 2, 3, 8 and 9. (1) Explaining in association with FIG. 2 and FIG. 3, the invention of claim 1 uses a resin mold member 1 to form a plurality of busbars 11 and 12 on which semiconductor elements 21 and 22 are mounted by surface bonding and a busbar 13. The semiconductor module M, which is integrated, seals the semiconductor elements 21 and 22 by filling the liquid sealing agent 4 in the semiconductor element disposition region S and curing the same, and fixes the semiconductor module M with the heat dissipation sheet 3 interposed therebetween. The present invention is applied to a semiconductor device including a cooler 2 and achieves the above-mentioned object by forming at least one hole 100 penetrating from the semiconductor element disposition region S to a portion of the semiconductor module M facing the heat dissipation sheet 3. . (2) The invention of claim 2 is the semiconductor device according to claim 1, wherein the hole 100 is formed in the resin mold member 1c included in the semiconductor element disposition region S. (3) Describing in association with FIG. 8, the invention of claim 3 is the semiconductor device according to claim 2, wherein the resin mold member 1c has a protrusion 11 whose height H is higher than that of the semiconductor element.
0 is formed, and the hole 100 is formed in the protrusion 110. (4) Describing in association with FIG. 9, the invention of claim 4 is the semiconductor device according to claim 3, wherein the protrusion 11 is provided.
The height H of 0 is higher than the surface of the sealant 4.

【0007】なお、上記課題を解決するための手段の項
では、本発明を分かり易くするために発明の実施の形態
の図を用いたが、これにより本発明が発明の実施の形態
に限定されるものではない。
In the section of the means for solving the above problems, the drawings of the embodiments of the present invention are used to make the present invention easy to understand, but the present invention is limited to the embodiments of the present invention. Not something.

【0008】[0008]

【発明の効果】(1)請求項1の発明によれば、半導体
素子配設領域に充填された液状封止剤が孔を通して半導
体モジュールの放熱シート側に導かれ、半導体モジュー
ルと放熱シートとの隙間に浸入する。その結果、半導体
モジュールと放熱シートとの隙間に封止部材が充填され
て隙間空間が減少するので、半導体モジュールから冷却
器への放熱性能が向上する。 (2)請求項2の発明では、請求項1と同様の効果が得
られるとともに、孔を樹脂モールド部材に形成したの
で、電流経路を考慮する必要がなく容易に孔を形成する
ことができる。 (3)請求項3の発明では、請求項1および2と同様の
効果が得られるとともに、突出部の高さが半導体素子よ
りも高いので、液状封止剤充填時に孔から排出された気
泡が半導体素子に付着することがない。その結果、封止
部材による半導体素子の封止効果が低下することがな
い。 (4)請求項4の発明では、請求項1および2と同様の
効果が得られるとともに、液状封止剤充填時に孔から排
出された気泡は、半導体素子配設領域の液状封止剤中に
排出されることなく液状封止剤外に直接排出される。そ
の結果、気泡の半導体素子への付着を確実に防止するこ
とができる。
(1) According to the invention of claim 1, the liquid sealing agent filled in the semiconductor element disposition region is guided to the heat dissipation sheet side of the semiconductor module through the hole, and the semiconductor module and the heat dissipation sheet are connected. Penetrate the gap. As a result, the gap between the semiconductor module and the heat dissipation sheet is filled with the sealing member to reduce the gap space, so that the heat dissipation performance from the semiconductor module to the cooler is improved. (2) In the invention of claim 2, the same effect as in claim 1 is obtained, and since the hole is formed in the resin mold member, it is possible to easily form the hole without considering the current path. (3) According to the invention of claim 3, the same effects as those of claims 1 and 2 are obtained, and since the height of the protruding portion is higher than that of the semiconductor element, bubbles discharged from the holes during filling of the liquid sealing agent are Does not adhere to semiconductor elements. As a result, the sealing effect of the semiconductor element by the sealing member does not decrease. (4) According to the invention of claim 4, the same effects as those of claims 1 and 2 are obtained, and the bubbles discharged from the holes at the time of filling the liquid encapsulant are contained in the liquid encapsulant in the semiconductor element disposition region. It is directly discharged to the outside of the liquid sealant without being discharged. As a result, it is possible to reliably prevent bubbles from adhering to the semiconductor element.

【0009】[0009]

【発明の実施の形態】以下、図を参照して本発明の実施
の形態を説明する。図1は、半導体素子21,22を用
いて直流P,Nを交流U,V,Wに変換するインバータ
の電力変換部回路の一部を示す図であり、U,V,Wの
内の1相分、例えばU相、に関する部分を示したもので
ある。図1に示す例では、半導体素子21,22として
MOS FETが用いられている。11はP極用のバスバー、
12はインバータ出力用のバスバー、13はN極用のバ
スバーである。また、51,52は、半導体素子21,
22の各々のゲートGに駆動信号を印加するゲート端子
である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a part of a power converter circuit of an inverter that converts direct current P, N into alternating current U, V, W by using semiconductor elements 21, 22. It shows a portion related to a phase component, for example, a U phase. In the example shown in FIG. 1, the semiconductor elements 21 and 22 are
MOS FET is used. 11 is a bus bar for P pole,
12 is a bus bar for inverter output, and 13 is a bus bar for N pole. Further, 51, 52 are semiconductor elements 21,
22 is a gate terminal for applying a drive signal to each gate G of 22.

【0010】図2は、図1に示した回路の構造を示す斜
視図である。バスバー11上には導電性の接合材31に
より半導体素子21が固着されており、半導体素子21
の裏面(図1のドレインD)とP極用のバスバー11の
表面とが面接合されている。同様に、接合材32により
半導体素子22がインバータ出力用バスバー12上に固
着され、半導体素子22の裏面(図1のドレインD)と
バスバー12の表面とが面接合されている。接合材3
1,32は、半導体素子21,22とバスバー11,1
2との間を電気的に接続するとともに熱的接続の役割も
果たしており、ハンダ等が用いられる。なお、接合材3
1,32としては、ハンダ以外に銀フィラー等を含有す
る導電ペーストを用いても良い。
FIG. 2 is a perspective view showing the structure of the circuit shown in FIG. The semiconductor element 21 is fixed on the bus bar 11 with a conductive bonding material 31.
The back surface (drain D in FIG. 1) of the above is surface-bonded to the front surface of the bus bar 11 for the P pole. Similarly, the semiconductor element 22 is fixed on the inverter output bus bar 12 by the bonding material 32, and the back surface of the semiconductor element 22 (drain D in FIG. 1) and the front surface of the bus bar 12 are surface-bonded. Bonding material 3
1, 32 are semiconductor elements 21, 22 and bus bars 11, 1
The two are electrically connected and also play a role of thermal connection, and solder or the like is used. The bonding material 3
In addition to solder, conductive paste containing silver filler or the like may be used as 1, 32.

【0011】半導体素子21,22の図示上面側には図
1のソースSおよびゲートGが形成されており、半導体
素子21のソースは金属ワイヤ41によりバスバー12
に接続され、ゲートは金属ワイヤ61によりゲート端子
51に接続されている。ゲート端子51には半導体素子
21の駆動用信号が入力される。一方、半導体素子22
のソースは金属ワイヤ42によりバスバー13に接続さ
れ、ゲートは金属ワイヤ62によりゲート端子52に接
続されている。
The sources S and the gates G of FIG. 1 are formed on the upper surfaces of the semiconductor elements 21 and 22 in the figure, and the source of the semiconductor element 21 is the metal wire 41 for the bus bar 12.
, And the gate is connected to the gate terminal 51 by a metal wire 61. A signal for driving the semiconductor element 21 is input to the gate terminal 51. On the other hand, the semiconductor element 22
The source is connected to the bus bar 13 by the metal wire 42, and the gate is connected to the gate terminal 52 by the metal wire 62.

【0012】各バスバー11〜13は電位が異なるの
で、互いに接触しないような間隔で配置されている。1
は各バスバー11〜13の縁部分を覆うとともに、各バ
スバー11〜13の間を埋めるように電気絶縁性の樹脂
でモールド形成したものであり、以下では樹脂枠1と呼
ぶことにする。なお、図2では樹脂枠1の一部を破断面
とした。この樹脂枠1により複数のバスバー11〜13
は一つに結合され、一体のモジュールMが形成される。
また、樹脂枠1はバスバー11〜13間を電気的に絶縁
する機能も果たしている。
Since the bus bars 11 to 13 have different electric potentials, they are arranged at intervals so as not to contact each other. 1
Is molded with an electrically insulative resin so as to cover the edge portions of the bus bars 11 to 13 and fill the spaces between the bus bars 11 to 13, and will be referred to as a resin frame 1 below. Note that, in FIG. 2, a part of the resin frame 1 has a fracture surface. With this resin frame 1, a plurality of bus bars 11 to 13
Are joined together to form an integral module M.
The resin frame 1 also has a function of electrically insulating between the bus bars 11 to 13.

【0013】一体化されたモジュールMは、放熱シート
3を介してヒートシンク2に固定されている。ヒートシ
ンク2内には冷却水等の冷媒が流れる流路2aが形成さ
れている。放熱シート3は、半導体素子21,22から
バスバー11,12に伝達された熱をヒートシンク2に
伝達するとともに、バスバー11,12とヒートシンク
2との間の電気的絶縁を確保する役割も担っている。半
導体素子21,22で発生した熱はバスバー11,12
および放熱シート3を介してヒートシンク2に伝えら
れ、流路2aを流れる冷媒に放熱される。
The integrated module M is fixed to the heat sink 2 via the heat dissipation sheet 3. A flow path 2a through which a coolant such as cooling water flows is formed in the heat sink 2. The heat dissipation sheet 3 plays a role of transferring the heat transferred from the semiconductor elements 21 and 22 to the busbars 11 and 12 to the heatsink 2 and ensuring electrical insulation between the busbars 11 and 12 and the heatsink 2. . The heat generated in the semiconductor elements 21 and 22 is transferred to the bus bars 11 and 12
The heat is also transmitted to the heat sink 2 via the heat dissipation sheet 3 and is radiated to the refrigerant flowing through the flow path 2a.

【0014】樹脂枠1には半導体素子21,22を囲む
ように壁1aが形成されており、この壁1aで囲まれた
半導体配設領域Sに封止部材としてゲル部材4が充填さ
れる。なお、図2ではゲル部材4の図示を省略した。図
3は図2のA−A断面図であり、壁1aの上端付近まで
ゲル部材4が充填されている。その結果、半導体素子2
1,22および金属ワイヤ41,42,61,62はゲ
ル部材4に封止され、半導体素子21,22の保護や、
金属ワイヤ41,42,61,62の空中配線部の共振
防止を図ることができる。
A wall 1a is formed in the resin frame 1 so as to surround the semiconductor elements 21 and 22, and a semiconductor mounting region S surrounded by the wall 1a is filled with a gel member 4 as a sealing member. The gel member 4 is not shown in FIG. FIG. 3 is a sectional view taken along the line AA of FIG. 2, in which the gel member 4 is filled up to the vicinity of the upper end of the wall 1a. As a result, the semiconductor element 2
1, 22 and the metal wires 41, 42, 61, 62 are sealed in the gel member 4 to protect the semiconductor elements 21, 22 and
The resonance of the aerial wiring portion of the metal wires 41, 42, 61, 62 can be prevented.

【0015】図3に示すように、樹脂枠1は上述した壁
1aの他に、バスバー間の連結部1b、1cおよび壁1
aの外側に延在するフランジ部1dを有している。バス
バー11〜13の底面は連結部1b、1cおよびフラン
ジ部1dの底面部よりも図示下方に突出しており、放熱
シート3にはバスバー11〜13の底面が接触してい
る。また、連結部1cには貫通孔100が形成されてお
り、ゲル部材4は孔100を通して連結部1cの底面と
放熱シート3との隙間や、さらにはバスバー11〜13
の底面と放熱シート3との間の微小隙間にも浸入する。
As shown in FIG. 3, in addition to the wall 1a described above, the resin frame 1 includes the connecting portions 1b and 1c between the bus bars and the wall 1.
It has a flange portion 1d extending to the outside of a. The bottom surfaces of the bus bars 11 to 13 project below the bottom surfaces of the connecting portions 1b and 1c and the flange portion 1d in the drawing, and the bottom surfaces of the bus bars 11 to 13 are in contact with the heat dissipation sheet 3. In addition, a through hole 100 is formed in the connecting portion 1c, and the gel member 4 passes through the hole 100 to form a gap between the bottom surface of the connecting portion 1c and the heat dissipation sheet 3, and further the bus bars 11 to 13.
Also penetrates into the minute gap between the bottom surface of the heat radiation sheet 3 and the heat radiation sheet 3.

【0016】図4は図3のB部を拡大して示した図であ
り、図5は図4のC部をさらに拡大した図である。前述
したように、バスバー11〜13の表面には微視的な凹
凸があるため、図5に示すようにバスバー底面と放熱シ
ート3との間に微小な隙間が生じる。本実施の形態で
は、液状のゲル部材4が連結部1cに形成された孔10
0を通って連結部1cと放熱シート3との隙間に入り込
み(図4参照)、さらに、そこからバスバー11と放熱
シート3との隙間5にゲル部材4が浸入する(図5参
照)。一方、従来の場合には連結部1cに貫通孔が形成
されないので、図5のバスバー11と放熱シート3との
隙間5は空気層となっていた。空気の熱伝導率は0.0
3(W/m・K)であるが、ゲル部材4の熱伝導率はそ
れよりも大きく、例えば、0.15(W/m・K)であ
る。そのため、バスバー11と放熱シート3との隙間5
にゲル部材4を導き入れることにより、バスバー11か
らヒートシンク2への放熱性能を向上させることができ
る。
FIG. 4 is an enlarged view of portion B of FIG. 3, and FIG. 5 is a further enlarged view of portion C of FIG. As described above, since the surfaces of the bus bars 11 to 13 have microscopic unevenness, a minute gap is formed between the bottom surface of the bus bar and the heat dissipation sheet 3 as shown in FIG. In the present embodiment, the liquid gel member 4 is formed in the hole 10 formed in the connecting portion 1c.
0, and enters into the gap between the connecting portion 1c and the heat dissipation sheet 3 (see FIG. 4), and further, the gel member 4 penetrates into the gap 5 between the bus bar 11 and the heat dissipation sheet 3 (see FIG. 5). On the other hand, in the conventional case, since the through hole is not formed in the connecting portion 1c, the gap 5 between the bus bar 11 and the heat dissipation sheet 3 in FIG. 5 is an air layer. The thermal conductivity of air is 0.0
Although it is 3 (W / m · K), the thermal conductivity of the gel member 4 is higher than that, for example, 0.15 (W / m · K). Therefore, the gap 5 between the bus bar 11 and the heat dissipation sheet 3
By introducing the gel member 4 into the heat sink 2, heat dissipation performance from the bus bar 11 to the heat sink 2 can be improved.

【0017】《ゲル部材充填手順の説明》図6,7はゲ
ル部材4の充填作業の手順を説明する図である。図6
(a)に示すように樹脂枠1のフランジ部1dにはネジ
固定用の貫通孔17が複数形成されており、モジュール
Mは貫通孔17を利用してヒートシンク2にネジ固定さ
れる。14は、モジュール取付用ネジ孔19が形成され
たゲル充填用治具である。モジュールMは、ヒートシン
ク2に取り付ける場合と同様に、ネジ16により放熱シ
ート3を挟むように治具14に取り付けられる。このと
き、バスバー11〜13の底面が放熱シート3に押圧さ
れるようにネジ16を締め付ける。なお放熱シート3に
も、貫通孔17に対応する位置に貫通孔18が形成され
ている。
<< Explanation of Gel Member Filling Procedure >> FIGS. 6 and 7 are views for explaining the procedure of the filling operation of the gel member 4. Figure 6
As shown in (a), a plurality of through holes 17 for screw fixing are formed in the flange portion 1d of the resin frame 1, and the module M is screw-fixed to the heat sink 2 using the through holes 17. 14 is a gel filling jig in which a module mounting screw hole 19 is formed. The module M is attached to the jig 14 so that the heat radiation sheet 3 is sandwiched by the screws 16 as in the case of attaching to the heat sink 2. At this time, the screws 16 are tightened so that the bottom surfaces of the bus bars 11 to 13 are pressed by the heat dissipation sheet 3. The heat dissipation sheet 3 also has through holes 18 formed at positions corresponding to the through holes 17.

【0018】次に、図6(b)に示すように、ディスペ
ンサ15を用いて壁1aで囲まれた半導体素子配設領域
Sの内側空間にゲル部材4を充填する。ゲル部材4はシ
リコーンを主成分とし、充填時にはゾル状態で低粘度の
液状である。そして、充填後に常温もしくは高温で一定
時間放置することによりゾル状態からゲル硬化する。充
填されたゲル部材4は連結部1cの孔100を通ってバ
スバー11〜13と放熱シート3との隙間5(図5参
照)に浸入する。
Next, as shown in FIG. 6B, the gel member 4 is filled in the inner space of the semiconductor element disposition region S surrounded by the wall 1a using the dispenser 15. The gel member 4 contains silicone as a main component, and is a low-viscosity liquid in a sol state at the time of filling. After the filling, the gel is hardened from the sol state by leaving it at room temperature or high temperature for a certain time. The filled gel member 4 penetrates into the gap 5 (see FIG. 5) between the bus bars 11 to 13 and the heat dissipation sheet 3 through the hole 100 of the connecting portion 1c.

【0019】次いで、図7(a)に示すように、ゲル部
材4が充填されたモジュールMを治具14に固定した状
態で真空炉30に装填し、真空炉30内を真空ポンプ3
4で真空排気する。その結果、バスバー11〜13と放
熱シート3との隙間に介在する空気はフランジ部1dと
放熱シート3との隙間36から排出されるとともに、連
結部1cの孔100からも気泡35となって排出され
る。空気が排出された隙間には、粘度の低い液状のゲル
部材4が浸入する。
Next, as shown in FIG. 7A, the module M filled with the gel member 4 is loaded into the vacuum furnace 30 while being fixed to the jig 14, and the inside of the vacuum furnace 30 is vacuum pumped.
Evacuate at 4. As a result, the air present in the gaps between the bus bars 11 to 13 and the heat radiation sheet 3 is discharged from the gap 36 between the flange portion 1d and the heat radiation sheet 3 and also discharged as bubbles 35 from the holes 100 of the connecting portion 1c. To be done. The liquid gel member 4 having a low viscosity enters the gap where the air is discharged.

【0020】その後、真空炉30の炉内温度を最大で1
50℃まで昇温し、ゲル部材4をゲル硬化させる。な
お、このときの炉内温度および放置時間はゲル部材4の
硬化条件に応じて設定される。ゲル部材4がゲル硬化し
たら、図7(b)のようにネジ16を外して、モジュー
ルMを治具14から取り外す。放熱シート3とバスバー
11〜13との隙間にはゲル部材4が浸入しているの
で、ゲル部材4を媒体としてファンデルワールス力およ
びアンカー効果により放熱シート3とモジュールMとは
一体化される。
Thereafter, the temperature inside the vacuum furnace 30 is set to 1 at maximum.
The temperature is raised to 50 ° C. and the gel member 4 is gel-hardened. The furnace temperature and the standing time at this time are set according to the curing conditions of the gel member 4. When the gel member 4 is gel-hardened, the screw 16 is removed and the module M is removed from the jig 14 as shown in FIG. 7B. Since the gel member 4 penetrates into the gaps between the heat dissipation sheet 3 and the bus bars 11 to 13, the heat dissipation sheet 3 and the module M are integrated with each other by the van der Waals force and the anchor effect using the gel member 4 as a medium.

【0021】上述したように、本実施の形態では、樹脂
枠1の連結部1cに貫通孔100を形成して、壁1aで
囲まれた半導体素子配設領域Sに充填されたゲル部材4
をバスバー11〜13と放熱シート3との隙間に浸入さ
せたことにより、バスバー11〜13からヒートシンク
2への放熱性能を向上させることができる。さらに、ゲ
ル部材4が充填されたモジュールMを真空雰囲気内に置
くことにより隙間5に介在する空気が排出され、ゲル部
材4の隙間5への浸入を確実に行わせることができる。
As described above, in the present embodiment, the through hole 100 is formed in the connecting portion 1c of the resin frame 1, and the gel member 4 filled in the semiconductor element disposition region S surrounded by the wall 1a.
By infiltrating into the gap between the bus bars 11 to 13 and the heat dissipation sheet 3, the heat dissipation performance from the bus bars 11 to 13 to the heat sink 2 can be improved. Further, by placing the module M filled with the gel member 4 in a vacuum atmosphere, the air intervening in the gap 5 is discharged, and the gel member 4 can be surely infiltrated into the gap 5.

【0022】また、図7(a)に示すように、貫通孔1
00は金属ワイヤ42が設けられている部分を避けて形
成されているので、真空引きの際に排出される気泡35
が金属ワイヤ42に付着することが無い。例えば、気泡
35が金属ワイヤ42に付着した状態でゲル部材4がゲ
ル硬化すると、気泡35が付着した部分はゲル部材4の
無い空洞となる。そのため、気泡35が付着すると金属
ワイヤ42の固定不足や共振防止不良を招くが、本実施
の形態ではそのような不都合を避けることができる。
Further, as shown in FIG. 7A, the through hole 1
Since 00 is formed avoiding the portion where the metal wire 42 is provided, the bubbles 35 discharged during evacuation
Does not adhere to the metal wire 42. For example, when the gel member 4 is gel-hardened with the bubbles 35 attached to the metal wire 42, the portion to which the bubbles 35 are attached becomes a void without the gel member 4. Therefore, if the bubbles 35 adhere to the metal wire 42, the metal wire 42 may be insufficiently fixed or the resonance may be prevented. However, in the present embodiment, such an inconvenience can be avoided.

【0023】「変形例1」図8は上述した実施の形態の
第1の変形例であり、図3と同位置の断面図である。連
結部1cには柱状部110が形成されており、この柱状
部110と連結部1cとを貫通するように孔100が形
成されている。柱状部110の高さHは、ゲル部材4の
深さをD1、半導体素子22の高さをH1としたとき、
H1<H<D1となるように設定される。好ましくは、
D1とほぼ同程度が良い。このような高さHの柱状部1
10に孔100を形成して、孔100の出口をゲル部材
4の表面近くとすることにより、真空引きの際に孔10
0から排出される気泡が半導体素子22や金属ワイヤ4
2に付着するのを防止することができる。
[Modification 1] FIG. 8 is a first modification of the above-described embodiment and is a sectional view taken at the same position as in FIG. A columnar portion 110 is formed in the connecting portion 1c, and a hole 100 is formed so as to penetrate the columnar portion 110 and the connecting portion 1c. When the depth H of the gel member 4 is D1 and the height of the semiconductor element 22 is H1, the height H of the columnar portion 110 is
It is set so that H1 <H <D1. Preferably,
About the same as D1 is good. The columnar portion 1 having such a height H
The hole 100 is formed in the hole 10 and the outlet of the hole 100 is near the surface of the gel member 4, so that the hole 10 can be removed during vacuuming.
The bubbles discharged from 0 are the semiconductor element 22 and the metal wire 4
It can be prevented from adhering to 2.

【0024】また、図9に示すように孔100が形成さ
れた柱状部110の高さHをゲル部材4の深さD1より
大きくしても良い。ゲル部材4を充填する際には、吐出
口15aが孔100の真上となるようにディスペンサ1
5を位置決めして充填を行う。ゲル部材4は孔100に
流れ込むとともに半導体素子配設領域Sにも充填され
る。図9の場合、孔100から排出される気泡は、半導
体素子収納空間のゲル部材4内に排出されることなく直
接外部空間に排出される。そのため、半導体素子22や
金属ワイヤ42への気泡の付着を確実に防止することが
でき、孔100からの距離を考慮せずに半導体素子22
や金属ワイヤ42の配置設計を行うことができる。
Further, as shown in FIG. 9, the height H of the columnar portion 110 in which the hole 100 is formed may be made larger than the depth D1 of the gel member 4. When the gel member 4 is filled, the dispenser 1 is placed so that the discharge port 15 a is directly above the hole 100.
5 is positioned and filling is performed. The gel member 4 flows into the holes 100 and fills the semiconductor element disposition region S as well. In the case of FIG. 9, the bubbles discharged from the hole 100 are directly discharged to the external space without being discharged to the gel member 4 in the semiconductor element housing space. Therefore, it is possible to reliably prevent air bubbles from adhering to the semiconductor element 22 and the metal wire 42, and to consider the distance from the hole 100.
The layout of the metal wire 42 can be designed.

【0025】「変形例2」図10は第2の変形例を示す
図であり、図2と同様の斜視図である。なお、図10で
はヒートシンク2の図示を省略した。上述した図2のモ
ジュールMでは孔100は連結部1cの一箇所に形成さ
れているだけであったが、図10のモジュールM2では
各連結部1b、1cの複数箇所に孔100を形成した。
ただし、金属ワイヤ41,42の真下の位置を除いた部
分に形成する。この場合も、図8,9のような柱状部1
10を複数形成して、各柱状部110に貫通孔100を
形成するようにしても良い。このように貫通孔100を
複数形成することにより、バスバー11〜13の底面全
体にゲル部材4を浸入させやすくなる。また、真空引き
の際に隙間5(図5参照)から排出される空気の経路が
短くなり、効率良く空気を排出することができるので、
真空引きの作業時間を短縮することができる。
[Modification 2] FIG. 10 is a view showing a second modification and is a perspective view similar to FIG. The heat sink 2 is not shown in FIG. In the module M of FIG. 2 described above, the hole 100 was formed only at one place of the connecting portion 1c, but in the module M2 of FIG. 10, the hole 100 was formed at a plurality of places of each connecting portion 1b, 1c.
However, it is formed in the portion excluding the positions directly under the metal wires 41, 42. Also in this case, the columnar portion 1 as shown in FIGS.
A plurality of 10 may be formed and the through hole 100 may be formed in each columnar portion 110. By forming a plurality of through holes 100 in this manner, it becomes easy for the gel member 4 to penetrate into the entire bottom surfaces of the bus bars 11 to 13. In addition, the path of the air discharged from the gap 5 (see FIG. 5) during evacuation is shortened, and the air can be discharged efficiently,
The work time for vacuuming can be shortened.

【0026】なお、上述した実施の形態では、以下の理
由(a),(b)から貫通孔100をバスバー間を絶縁
している樹脂枠1に形成した。 (a)樹脂枠1であれば、樹脂枠1をモールド成形する
際に貫通孔100を容易に形成することができる。 (b)樹脂枠1であれば電流の経路を考慮する必要がな
い。
In the above-described embodiment, the through hole 100 is formed in the resin frame 1 which insulates the bus bars from each other for the following reasons (a) and (b). (A) With the resin frame 1, the through holes 100 can be easily formed when the resin frame 1 is molded. (B) With the resin frame 1, it is not necessary to consider the current path.

【0027】しかしながら、バスバー11〜13と放熱
シート3との隙間にゲル部材4を導くという目的からす
ると、必ずしも樹脂枠1に貫通孔100を形成する必要
はない。例えば、半導体素子21,22や金属ワイヤ4
1,42,61,62に影響しない位置であれば、バス
バー11〜13に貫通孔100を形成しても良い。
However, for the purpose of guiding the gel member 4 into the gap between the bus bars 11 to 13 and the heat dissipation sheet 3, it is not always necessary to form the through hole 100 in the resin frame 1. For example, the semiconductor elements 21 and 22 and the metal wire 4
The through holes 100 may be formed in the bus bars 11 to 13 as long as they do not affect the positions 1, 42, 61 and 62.

【0028】また、インバータ回路の1相分の回路を例
に本発明を説明したが、半導体素子が実装された複数の
バスバーを樹脂モールドして一体化し、半導体素子配設
領域Sにゲル部材4を充填する構造のものであれば、同
様に適用することができる。
Although the present invention has been described by taking the circuit for one phase of the inverter circuit as an example, a plurality of bus bars on which semiconductor elements are mounted are resin-molded and integrated, and the gel member 4 is provided in the semiconductor element mounting region S. If it has a structure for filling the

【0029】以上説明した実施の形態と特許請求の範囲
の要素との対応において、樹脂枠1は樹脂モールド部材
を、ゲル部材4は液状封止剤を、柱状部100は突出部
をそれぞれ構成する。
In the correspondence between the embodiment described above and the elements in the claims, the resin frame 1 constitutes a resin mold member, the gel member 4 constitutes a liquid sealant, and the columnar portion 100 constitutes a protruding portion. .

【図面の簡単な説明】[Brief description of drawings]

【図1】インバータの電力変換部回路の一部を示す図で
ある。
FIG. 1 is a diagram showing a part of a power conversion unit circuit of an inverter.

【図2】本発明による半導体装置の一実施の形態を示す
図であり、図1に示した回路の構造を示す斜視図であ
る。
FIG. 2 is a diagram showing an embodiment of a semiconductor device according to the present invention, and is a perspective view showing the structure of the circuit shown in FIG.

【図3】図2のA−A断面図である。3 is a cross-sectional view taken along the line AA of FIG.

【図4】図3に示したB部の拡大図である。FIG. 4 is an enlarged view of part B shown in FIG.

【図5】図4に示したC部の拡大図である。5 is an enlarged view of a C portion shown in FIG.

【図6】ゲル部材4の充填作業の手順を示す図であり、
(a),(b)の順に作業が進む。
FIG. 6 is a diagram showing a procedure of a filling operation of the gel member 4,
The work proceeds in the order of (a) and (b).

【図7】図6に続く作業手順を示す図であり、(a),
(b)の順に作業が進む。
FIG. 7 is a diagram showing a work procedure following FIG. 6, (a),
The work proceeds in the order of (b).

【図8】第1の変形例を示す断面図である。FIG. 8 is a sectional view showing a first modification.

【図9】第1の変形例において、柱状部100の高さH
をゲル部材4の深さD1より大きくした場合を示す断面
図である。
9 is a height H of the columnar part 100 in the first modification. FIG.
FIG. 6 is a cross-sectional view showing a case where is larger than the depth D1 of the gel member 4.

【図10】第2の変形例を示す斜視図である。FIG. 10 is a perspective view showing a second modified example.

【符号の説明】[Explanation of symbols]

1 樹脂枠 1a 壁 1b,1c 連結部 1d フランジ部 2 ヒートシンク 3 放熱シート 4 ゲル部材 5 隙間 11,12,13 バスバー 21,22 半導体素子 30 真空炉 34 真空ポンプ 35 気泡 41,42,61,62 金属ワイヤ 100 孔 110 柱状部 M,M2 半導体モジュール S 半導体素子配設領域 1 resin frame 1a wall 1b, 1c connection part 1d flange 2 heat sink 3 heat dissipation sheet 4 Gel member 5 gap 11,12,13 busbar 21,22 Semiconductor element 30 vacuum furnace 34 Vacuum pump 35 bubbles 41, 42, 61, 62 Metal wire 100 holes 110 Column M, M2 semiconductor module S Semiconductor element mounting area

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子が面接合により実装された複
数のバスバーを樹脂モールド部材により一体化し、半導
体素子配設領域に液状封止剤を充填して硬化させること
により前記半導体素子を封止した半導体モジュールと、
前記半導体モジュールが放熱シートを挟んで固定される
冷却器とを備える半導体装置において、 前記半導体素子配設領域から前記半導体モジュールの前
記放熱シートに対向する部分へと貫通する孔を少なくと
も一つ形成したことを特徴とする半導体装置。
1. A semiconductor element is sealed by integrating a plurality of bus bars on which semiconductor elements are mounted by surface bonding with a resin mold member and filling a liquid sealing agent in a semiconductor element arrangement region and curing the liquid sealing agent. A semiconductor module,
In a semiconductor device having a cooler in which the semiconductor module is fixed with a heat dissipation sheet sandwiched, at least one hole penetrating from the semiconductor element disposition region to a portion of the semiconductor module facing the heat dissipation sheet is formed. A semiconductor device characterized by the above.
【請求項2】 請求項1に記載の半導体装置において、 前記孔を、前記半導体素子配設領域に含まれる前記樹脂
モールド部材に形成したことを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein the hole is formed in the resin mold member included in the semiconductor element disposition region.
【請求項3】 請求項2に記載の半導体装置において、 前記樹脂モールド部材に高さが前記半導体素子よりも高
い突出部を形成し、前記突出部に前記孔を形成したこと
を特徴とする半導体装置。
3. The semiconductor device according to claim 2, wherein a protrusion having a height higher than that of the semiconductor element is formed on the resin mold member, and the hole is formed in the protrusion. apparatus.
【請求項4】 請求項3に記載の半導体装置において、 前記突出部の高さを前記封止剤の表面よりも高くしたこ
とを特徴とする半導体装置。
4. The semiconductor device according to claim 3, wherein the height of the protrusion is higher than the surface of the sealant.
JP2001194255A 2001-06-27 2001-06-27 Semiconductor device Pending JP2003007928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001194255A JP2003007928A (en) 2001-06-27 2001-06-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001194255A JP2003007928A (en) 2001-06-27 2001-06-27 Semiconductor device

Publications (1)

Publication Number Publication Date
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Family

ID=19032423

Family Applications (1)

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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039242A (en) * 2003-06-26 2005-02-10 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2006190711A (en) * 2004-12-28 2006-07-20 Toshiba Corp Semiconductor device
JP2006213072A (en) * 2005-02-01 2006-08-17 Advics:Kk Vehicle hydraulic pressure control device
JP2020053502A (en) * 2018-09-26 2020-04-02 株式会社ケーヒン Power module
WO2020250669A1 (en) * 2019-06-12 2020-12-17 Hitachi Automotive Systems, Ltd. Power converter and method for manufacturing the power converter

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005039242A (en) * 2003-06-26 2005-02-10 Toshiba Corp Semiconductor device and method of manufacturing the same
JP4559777B2 (en) * 2003-06-26 2010-10-13 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2006190711A (en) * 2004-12-28 2006-07-20 Toshiba Corp Semiconductor device
JP4575147B2 (en) * 2004-12-28 2010-11-04 株式会社東芝 Semiconductor device
JP2006213072A (en) * 2005-02-01 2006-08-17 Advics:Kk Vehicle hydraulic pressure control device
JP2020053502A (en) * 2018-09-26 2020-04-02 株式会社ケーヒン Power module
WO2020250669A1 (en) * 2019-06-12 2020-12-17 Hitachi Automotive Systems, Ltd. Power converter and method for manufacturing the power converter
JP2022535259A (en) * 2019-06-12 2022-08-05 日立Astemo株式会社 Power converter and method for manufacturing the power converter
JP7237205B2 (en) 2019-06-12 2023-03-10 日立Astemo株式会社 Power converter and method for manufacturing the power converter

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