JP2003005955A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor for executing instructions by successively reading those instructions according to a sequence capable of reducing the program size by reducing a redundant program code when there is an instruction group in a relation that a source operand and a destination operand are inverted. SOLUTION: There are a first instruction to explicitly designating an instruction to be inverted, and to directly control the execution order of instructions, a second instruction to directly control the execution order of the instructions, and a third instruction to directly control the execution order of the instructions by making a pair with the first or second instruction. Only when the first instruction is decoded, an instruction decoder 50 updates an inversion stage flag 110 in order to invert the data transfer origin and transfer destination, and when the first instruction is decoded, the instruction decoder 50 returns the inversion state flag 110 to the pre-updated original state in order not to invert the data transfer origin and transfer destination.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a data processing device called a CPU, a microprocessor, or the like.

[0002]

2. Description of the Related Art In recent years, with the development of electronic technology, data processing devices such as CPUs and microprocessors have become widespread and used in all fields. In a conventional data processing device having a general-purpose register, the general-purpose registers can be operated in any combination, so that the number of instructions can be kept relatively small compared to the case where the operand is limited to a memory address. . Further, since the register specifying code having a bit length shorter than that of the operand address is used, the instruction word length is relatively short.

Here, in general data processing, there are cases where a series of processing that is completely contrary to a certain series of processing is required regardless of its application such as scientific and technological calculation or control. FIG. 15 shows an example of a program executed by a conventional data processing device. This is an example of a program that is frequently used to save and restore registers. Below, a brief description is given for each instruction expressed in mnemonics. The value in [] in the figure is the code size of the instruction.

First line: SUB 6, R3 (immediate value 6 is subtracted from the value in the R3 register and the result is stored in the R3 register. LABEL1: indicates an address.) [2by
te] Second line: MOV R0, @ (4, R3) (The value of the R0 register is stored in the memory at the address obtained by adding the immediate value 4 to the R3 register.) [2byte] Third line: MOV R1, @ (2 , R3) (The value of the R1 register is stored in the memory of the address obtained by adding the immediate value 2 to the R3 register.) [2 byte] Fourth line: MOV R2, @ (0, R3) (The value of the R2 register is set to the R3 register. It is stored in the memory at the address to which the immediate value 0 is added.) [2 byte] 5th line: SUB R0, R0 (value of R0 register and R
The value of the 0 register is subtracted and stored in the R0 register. ) [1 byte] Sixth line: Process (This process is a data process consisting of a plurality of instructions and the R0 register, R1 register, and R2 register may be rewritten.) Seventh line: MOV @ ( 4, R3), R0 (The value stored in the memory at the address obtained by adding the R3 register and the immediate value 4 is loaded to the R0 register.) [2 byte] 8th line: MOV @ (2, R3), R1 (R3 The value stored in the memory at the address obtained by adding the register and the immediate value 2 is loaded to the R1 register.) [2 byte] Line 9: MOV @ (0, R3), R2 (Address obtained by adding the R3 register and the immediate value 0) The value stored in the memory of R2 is loaded into the R2 register.) [2 byte] 10th line: ADD 6, R3 (immediate value 6 is added to the value of the R3 register and the result is R3 register And stores it in the data.) [2
byte] 11th line: RTS (Returns from the subroutine.
The memory is read by using the contents of the stack pointer SP as an address, and the contents are stored in the program counter PC. Add 2 to the stack pointer and update SP. )
[1 byte] As described above, in the subroutine starting from the address indicated by LABEL1, the data transfer instruction is used in order not to destroy the data of the register used in the processing of the sixth line.

[0005]

However, according to the above-described conventional data processing apparatus, as shown in an example in FIG. 15, the instruction groups arranged in the 7th to 9th rows are 2
Although it is an instruction group in which the source operand and the destination operand of the instruction group arranged from the 4th line to the 4th line are inverted, it is necessary to secure a memory area as the program code, and therefore the program size is There was a problem of increase.

In view of the above problems, it is an object of the present invention to provide a data processing device which can keep the program size small.

[0007]

In order to solve the above-mentioned problems, a data processing apparatus according to the present invention executes a fetch unit that sequentially reads instructions, a decoding unit that decodes the read instructions, and executes the decoded instructions. A data processing device comprising: an execution unit for executing a reverse instruction storage unit for storing a target instruction for inverting a data transfer source and a transfer destination; and a reverse state identifier indicating whether or not the target instruction is reversely executed. And an operand control unit for inverting the data transfer source and the transfer destination described in the instruction.

With the above arrangement, the operand control circuit causes the data transfer source and the transfer destination to respond to the instruction of the inversion state identifier stored in the inversion state storage means only for the target instruction for inverting the data transfer source and the transfer destination. By inverting
Two types of data transfer processing that can be executed by one instruction group can be implemented.

Further, the data processing apparatus of the present invention having the above-mentioned configuration directly controls the execution order of the first instruction and the first instruction for directly designating the target instruction and directly controlling the execution order of the instructions. Instruction storage means for storing a second instruction, and a third instruction that pairs with the first instruction or the second instruction to directly control the execution order of the instructions; the first instruction and the second instruction Of the instructions, the inversion state identifier is updated to invert the data transfer source and the transfer destination only when the first instruction is decoded.
It is preferable to further include an inversion state updating unit for returning the inversion state identifier before updating so as not to invert the data transfer source and the transfer destination when the instruction is decoded.

According to this configuration, (1) when the second instruction is decoded, the instruction execution order is directly controlled, and then data processing is performed by one instruction group, and (2) data transfer source and transfer are performed. Directly controlling the instruction to be inverted and directly controlling the execution order of the instructions When the first instruction is decoded, the instruction execution order is directly controlled, and then the instruction group is different from the previous instruction. (3) When data is processed, (3) when the third instruction is decoded, it is possible to perform an operation of returning to the state before update regardless of the inverted state. That is, when the execution order of the instructions is transferred to one instruction group, different data transfer processing is performed depending on either the first instruction or the second instruction, and at the time of restoration, the data transfer source and the transfer destination are transferred. It is possible to return the treatment to normal.

Further, in the data processing apparatus of the present invention having the above-mentioned configuration, a pair of the first instruction and the first instruction for explicitly designating the target instruction and directly controlling the execution order of the instructions is formed. An instruction storing means for storing a second instruction for directly controlling the execution order of the instructions, and the first instruction
When the second instruction is decoded, the inversion state identifier is updated so as to invert the data transfer source and the transfer destination, and when the second instruction is decoded, the inversion state identifier indicates the data transfer source and the transfer destination. If it is to invert, the inversion state updating means for returning the inversion state identifier to before updating, assuming that the data transfer source and the transfer destination are not inverted after controlling the execution order of the instructions, and the second instruction are decoded. It is preferable to further include instruction invalidation control means for invalidating the second instruction if the inversion state identifier does not invert the data transfer source and the transfer destination.

According to this structure, the second instruction is valid only when the first instruction is decoded and the inversion state is being updated to invert the data transfer source and the transfer destination. As a result, when the inverted state is not updated by the first instruction, the second instruction is invalidated, and unnecessary return processing is not performed.

Further, only when the execution order of the instructions is directly transferred to one instruction group by the first instruction, a data transfer process different from the normal one is requested, and a return process is executed by the second instruction. It is possible to return the inversion state to before the update by assuming that the data transfer source and the transfer destination are not inverted after controlling the execution order of the instruction. That is, the first
By moving the execution order of instructions to one instruction group with
It is possible to request a different data transfer process and return to the normal state when returning.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] The first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, and 6.
8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, and FIG.
Will be explained. The following numerical values are x'00, x'0
It may be expressed as 1, etc., but this is a hexadecimal notation.

FIG. 4 shows an example of a program executed by the data processing device of the first embodiment. In this program example, each instruction is represented by mnemonic. Hereinafter, each instruction of this program will be briefly described. In addition,
The value written in the right end [] of each line is the code size of the instruction.

First line: SUB 6, R3 (immediate value 6 is subtracted from the value of the R3 register and the result is stored in the R3 register. LABEL1: indicates an address.) [2b
yte] Second line: MOV R0, @ (4, R3) (The value of the R0 register is stored in the memory at the address obtained by adding the R3 register and the immediate value 4. LABEL2: indicates the address.) [2byte] 3 Line: MOV R1, @ (2, R3) (The value of the R1 register is stored in the memory at the address obtained by adding the immediate value 2 to the R3 register.) [2byte] Line 4: MOV R2, @ (0, R3) (The value of the R2 register is stored in the memory at the address obtained by adding 0 to the R3 register.) [2 byte] Fifth line: FRTS (Invalid when the inversion state flag is 0. When the inversion state flag is 1 Stack pointer S
The memory is read by using the content of P as an address and the content is stored in the program counter PC. Add 2 to the stack pointer and update SP. Reset the inversion status flag to 0. ) [1 byte] Line 6: SUB R0, R0 (R0 register value and R
The value of the 0 register is subtracted and stored in the R0 register. )
[1 byte] 7th line: Process (This process is a data process consisting of a plurality of instructions and the R0 register, R1 register, and R2 register may be rewritten.) 8th line: FJSR @ (LABEL2) (The stack pointer SP is decremented by 2 and SP is updated. The program counter PC + 2 (indicating the next instruction on the 9th line) is written to the memory address indicated by the stack pointer SP. The inversion state flag is set to 1 and the program counter is set. LAB to PC
Update to L2. ) [2 byte] Line 9: ADD 6, R3 (immediate value 6 is added to the value of the R3 register and the result is stored in the R3 register.) [2
byte] 10th line: RTS (Returns from the subroutine.
The memory is read by using the contents of the stack pointer SP as an address, and the contents are stored in the program counter PC. Add 2 to the stack pointer and update SP. )
[1 byte] FJSR @ (LABEL2) and FRTS described above are
These are an instruction to call a subroutine and an instruction to return from a subroutine.

FIG. 2 is a block diagram showing the configuration of the data processing apparatus of this embodiment.

This data processing device is composed of three stages, that is, an instruction reading stage (hereinafter referred to as IF stage), a decoding stage (hereinafter referred to as DEC stage), and an operation execution stage (hereinafter referred to as EX stage). It shall have a staged pipeline structure. In addition, DEC
Operations such as address calculation may be executed at the stage.

In FIG. 2, reference numeral 106 is a ROM in which instructions are stored. Reference numeral 125 is an instruction read circuit for reading the instructions stored in the ROM 106. An instruction register 108 stores the fetched instruction.

An instruction decoding circuit 123 decodes the instruction fetched by the instruction reading circuit 125 and controls each unit of the data processing device. 110 is a reverse state flag,
When it is 0, it is not inverted, and when it is 1, it is inverted. 10
Reference numeral 9 is a pipeline control signal for controlling the pipeline.

A register file 105 is composed of four registers R0 to R3 and a stack pointer SP. The register length is 16 bits. Reference numeral 102 denotes an arithmetic unit that performs arithmetic logic operation. 111
Is a program counter (hereinafter referred to as a PC) indicating the address of the instruction read by the instruction read circuit 125.
In addition to PC, the value of PC + 2 is also outputable. Reference numeral 113 is P for reading the program counter 111.
It is C bus.

Reference numeral 112 is a constant generator for generating a constant under the control of the instruction decoding circuit 123. Constant generator 11
2 is a constant which is explicitly indicated by the operation code or a constant such as d8 added to the instruction code, which is stored in the instruction register 108.
Is stored via the instruction decoding circuit 123 and generated in response to the pipeline control signal 109. Reference numeral 104 is an RLST that stores the output of the arithmetic unit 102. 103 is AB
It is an OAR that stores the output from the US. 114 is RL
It is a first selector that selects the output of ST104 and OAR103. A second selector 115 selects the output of ABUS or PC. Reference numeral 122 denotes a bus interface circuit (hereinafter, referred to as BIB) that controls data exchange with an external device.
Abbreviated).

FIG. 3 shows the instruction decoding circuit 123 shown in FIG.
3 is a block diagram showing a detailed configuration of FIG. F decodes the operation code of the instruction register 108 and invalidates the instruction F
The RTS instruction invalidation signal 56, the instruction determination signal 52, and the inversion state flag 110 are updated or the inversion state flag 110 is updated.
Is an instruction decoder that reads out. The instruction decoder 50
It includes means (not shown) for updating the inversion state flag 110. As described above, the inversion state flag 110 indicates a non-inversion state when 0, and an inversion state when 1 is set.

Reference numeral 52 is an instruction determination signal composed of a plurality of signal lines indicating the instruction determined by the instruction decoder 50. Reference numeral 53 is an operand control circuit for controlling the operand, which receives the inversion state flag 110, the instruction register 108 and the instruction determination signal 52 as inputs, and outputs the operand access control signal 54 and the pipeline control signal 109. 10
Reference numeral 9 is a pipeline control signal for controlling the data flow and pipeline operation of the data processing device, which is output from the operand control circuit 53. 54 is an operand access control signal for controlling access to the operand,
It consists of multiple signal lines.

Each signal of the operand access control signal 54 is as follows. The MRD reads data from the memory address indicated by OAR 103,
This is a memory read control signal output to the bus interface circuit 122. MWT is a memory write control signal that is output to the bus interface circuit 122 to write data at the memory address indicated by the OAR 103. RWT is a register write signal output to the register file 105 to store data in the register file 105. RRD is a register read signal output to the register file 105 to read data from the register file 105. SRC [1: 0] is made up of 2 bits and is a signal indicating a register forming a source operand, DEST [1:].
[0] is also a signal consisting of 2 bits and indicating a register forming a destination operand. DI
The R signal will be described later.

The pipeline control signal 109 and the operand access control signal 54 are combined. The data processing device is controlled. The FRTS command invalidation signal 56
Is an instruction [FR used in the data processing apparatus of the present embodiment.
When TS] is decoded, it is output from the instruction decoder 50 according to the value of the inversion state flag 110 (that is, the instruction decoder 50 includes means for invalidating the FRTS instruction).

FIG. 1 is an explanatory view showing an example of an instruction code of the data processing apparatus of this embodiment. In order from the left column, the instruction type (for example, RR indicates processing between registers), the instruction format, and the instruction code are shown.

The above instruction format is shown in FIG. The instruction format f1 is composed of a 4-bit operation code and two 2-bit register designation codes.
The instruction format f2 includes a 4-bit operation code, two 2-bit register designation codes, an 8-bit immediate value (imm8), an address displacement (d8), or an 8-bit absolute address (abs).
It consists of 8). The instruction format f3 includes an 8-bit operation code, a 2-bit register designation code, an 8-bit immediate value (imm8), an address displacement (d8), or an 8-bit absolute address (abs).
It consists of 8). The instruction format f4 includes an 8-bit operation code, an 8-bit immediate value (imm8), an address displacement (d8), or an 8-bit absolute address (abs8). Instruction format f5
Is an instruction consisting of only an 8-bit opcode.

The instruction code shown in FIG. 1 is stored in the instruction register 108, and the instruction code is decoded by the instruction decoder 50 to determine the instruction type. actually,
Since there are instruction types that are processed in two stages (for example, JSR) and instruction types that perform different processing depending on the value of the inversion state flag 110 (for example, FRTS), the instruction decoder 5
0 outputs the result of determining the instruction type as the instruction determination signal 52.

For example, the instruction decoder 50 is a register-register data transfer instruction when it is a load instruction (at that time signal LD = 1) and when it is a store instruction (at that time signal ST = 1). (At that time the signal RR =
1) The register-immediate value data transfer instruction (signal R-imm8 = 1 at that time) and the instruction to call a subroutine (signal JSR-1 = at that time)
1, JSR-2 = 1, FJSR-1 = 1, or FJ
SR-2 = 1), an instruction to return from the subroutine (signals RTS-1 = 1, RTS-2 at that time)
= 1, FRTS = 1, FRTS-1 = 1, or FR
TS-2 = 1), respectively.

In the first embodiment, RTS, JSR, FR
For the TS and FJSR, it is assumed that the DEC stage and the EX stage are each processed in two stages (FRT
The first stage is represented by * -1, and the second stage is represented by * -2, although S may be invalidated. This stage switching shall be processed by the instruction decoder 50.

Next, FIG. 6 is an explanatory diagram showing input / output signals of the operand control circuit 53 according to the first embodiment. Figure 6
Then, the operand access control signal 54 shown in each row of RR, LD, and ST has a value of the inversion state flag 110 of 0.
It turns out that it depends on whether it is 1 or 1. That is, the operand control circuit 53 is configured to include a target instruction for inverting the data transfer source and the transfer destination, and a means for inverting and executing the target instruction.

DIR of operand access control signal 54
Is the re of the instruction corresponding to the instruction formats f1 and f2.
Indicates whether the fields indicated by g1 [1: 0] and reg2 [1: 0] correspond to SRC [1: 0] or DEST [1: 0]. When DIR = 1, SRC
[1: 0] = reg1 [1: 0], DEST [1: 0]
= Reg2 [1: 0]. When DIR = 0, SRC [1: 0] = reg2 [1: 0], DEST
This corresponds to [1: 0] = reg1 [1: 0]. DIR =
* Is an instruction that implicitly determines the register to be used.

Further, FJSR-2 and FRTS-2 shown in FIG.
In the above, an arrow is shown in the column of the inversion state flag 110, but this is in accordance with the timing to be described later.
0 indicates that the inversion state flag 110 is changed from the value marked on the left of the arrow to the value marked on the right.

The operation of the data processing apparatus of the first embodiment configured as above will be described.

First, when the inversion state flag 110 is 0,
Regarding how the data processing device of the first embodiment processes the program example shown in FIG. 15, a program execution example 1 (pipeline operation is shown in FIG. 8) and a program execution example 2 (pipeline in FIG. 9) are shown. Operation is shown). Next, the inversion state flag 110 is also 0.
At this time, how a command (JSR) that calls a subroutine is processed will be described as a program execution example 3 (a pipeline operation is shown in FIG. 10).

Furthermore, the program execution example 4 (FIG. 11) shows how the data processing apparatus of the first embodiment processes the program example (FIG. 14) whose code size is smaller than that of the program example shown in FIG. , FIG. 12 and FIG. 13 show the pipeline operation).

(Explanation of the operation of the program example shown in FIG. 15)
The data processing device according to the first embodiment uses the instruction 1 [SUB 6, R, which is the first half of the program example shown in FIG.
3], instruction 2 [MOV R0, @ (4, R3)], instruction 3 [MOV R1, @ (2, R3)], instruction 4 [MOV
R2, @ (0, R3)], instruction 5 [SUB R0, R
0] is sequentially shown in FIG. 8 as a program execution example 1.

FIG. 8 is an explanatory diagram of the pipeline operation according to the program execution example 1. In the description of the pipeline operation, b'00, b'01, b'10, and b'11 shown below are shown.
Is the register number in binary notation. Note that d8 is a displacement consisting of 8 bits. Hereinafter, the operation will be described for each timing in order of the passage of time. Inversion state flag 1 at timing t1
It is assumed that 10 is 0. There are timings that represent the first half (for example, timing t11) and the second half (timing t12) of the stage.

(Program Execution Example 1: Description of First Half of Program Example Shown in FIG. 15) <Timing t1> IF Stage: Instruction 1 [SUB 6, R3] Timing t11: Instruction 1 is read from ROM 106 and instruction register 108 Stored in.

<Timing t2> DEC stage: Instruction 1 [SUB 6, R3] Timing t21: Instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. R-im
The instruction determination signal 52 of m8 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t22: instruction decoding circuit 123
Then, the pipeline control signal 109 is output.

IF stage: Instruction 2 [MOV R0, @
(4, R3)] Timing t21: Instruction 2 is read from the ROM 106 and stored in the instruction register 108.

<Timing t3> EX stage: Instruction 1 [SUB 6, R3] Timing t31: Read the value of the register indicated by DEST [1: 0] in ABUS (control by RRD). Imm8 (6 at this time) is read from the constant generator 112 in CBUS.

Timing t32: After the values read to ABUS and CBUS are subtracted by the arithmetic unit 102, RLS
It is stored in the register indicated by DEST [1: 0] from T104 via ABUS (control by RWT).

DEC stage: instruction 2 [MOV R0,
@ (4, R3)] Timing t31: The instruction 2 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The ST instruction determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t32: The pipeline control signal 109 is output from the instruction decoding circuit 123. BBUS
The value of the register indicated by DEST [1: 0] is read (control by RRD). D8 (4 at this time) is read from CBUS to the constant generator 112.

IF stage: Instruction 3 [MOV R1, @
(2, R3)] Timing t31: Instruction 3 is read from the ROM 106 and stored in the instruction register 108.

<Timing t4> EX stage: Instruction 2 [MOV R0, @ (4, R
3)] Timing t41: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t42: SRC at ABUS
The value of the register indicated by [1: 0] is read out, and the first
It is stored in the memory address indicated by OAR 103 via the selector 114 (control by MWT).

DEC stage: instruction 3 [MOV R1,
@ (2, R3)] Timing t41: The instruction decoding circuit 123 decodes the instruction 3 stored in the instruction register 108. The ST instruction determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t42: The pipeline control signal 109 is output from the instruction decoding circuit 123. BBUS
The value of the register indicated by DEST [1: 0] is read (control by RRD). D8 (2 at this time) is read from CBUS to the constant generator 112.

IF stage: Instruction 4 [MOV R2, @
(0, R3)] Timing t41: Instruction 4 is read from ROM 106 and stored in instruction register 108.

<Timing t5> EX stage: Instruction 3 [MOV R1, @ (2, R
3)] Timing t51: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t52: SRC to ABUS
The value of the register indicated by [1: 0] is read out, and the first
It is stored in the memory address indicated by OAR 103 via the selector 114 (control by MWT).

DEC stage: instruction 4 [MOV R2,
@ (0, R3)] Timing t51: The instruction decoding circuit 123 decodes the instruction 4 stored in the instruction register 108. The ST instruction determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t52: The pipeline control signal 109 is output from the instruction decoding circuit 123. BBUS
The value of the register indicated by DEST [1: 0] is read (control by RRD). D8 (0 at this time) is read from the constant generator 112 in CBUS.

IF stage: Instruction 5 [SUB R0, R
0] Timing t51: Instruction 5 is read from ROM 106 and stored in instruction register 108.

<Timing t6> EX stage: Instruction 4 [MOV R2, @ (0, R
3)] Timing t61: The values read by BBUS and CBUS are added, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t62: SRC to ABUS
The value of the register indicated by [1: 0] is read out, and the first
It is stored in the memory address indicated by OAR 103 via the selector 114 (control by MWT).

DEC stage: instruction 5 [SUB R0,
R0] Timing t61: The instruction decoding circuit 123 decodes the instruction 5 stored in the instruction register 108. The RR command determination signal 52 is output. Inversion state flag 110
The value 0 of 0 is input to the operand control circuit 53.

Timing t62: The instruction decoding circuit 123 outputs the pipeline control signal 109.

IF stage: Instruction 6 [NOP] Timing t61: Instruction 6 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

<Timing t7> EX stage: Instruction 5 [SUB R0, R0] Timing t71: The value of the register indicated by SRC [1: 0] is read at ABUS (control by RRD). The value of the register indicated by DEST [1: 0] is read into BBUS (control by RRD).

Timing t72: RLS after the values read out to ABUS and BBUS are subtracted by the arithmetic unit 102.
It is stored in the register indicated by DEST [1: 0] from T104 via ABUS (control by RWT).

DEC stage: instruction 6 [NOP] timing t71: nothing is decoded and the process proceeds to the next DEC stage.

Timing t72: Nothing is decoded and the process proceeds to the next DEC stage.

IF stage: Instruction 7 [NOP] Timing t71: Instruction 7 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

As described above, the first half of the program example shown in FIG. 15 is data-processed.

Next, the data processing apparatus according to the first embodiment uses the instruction 1 [MOV @ (4, R3), R0] and the instruction 2 [MOV, which are the latter half of the program example shown in FIG.
@ (2, R3), R1], instruction 3 [MOV @ (0,
R3), R2], instruction 4 [ADD 6, R3], instruction 5
Program execution example 2 for the operation of sequentially processing [RTS]
Show as. FIG. 9 is an explanatory diagram of the pipeline operation according to the program execution example 2. Hereinafter, the operation will be described for each timing in order of the passage of time. Here, it is assumed that the value of the inversion state flag 110 is 0 at the timing t1.

(Program execution example 2: the latter half of the program example shown in FIG. 15) <Timing t1> IF stage: instruction 1 [MOV @ (4, R3), R
0] Timing t11: Instruction 1 is read from ROM 106 and stored in instruction register 108.

<Timing t2> DEC stage: instruction 1 [MOV @ (4, R3), R
0] Timing t21: The instruction decoding circuit 123 decodes the instruction 1 stored in the instruction register 108. The LD command determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t22: The pipeline control signal 109 is output from the instruction decoding circuit 123. BBUS
The value of the register indicated by SRC [1: 0] is read out (control by RRD). D8 (4 at this time) is read from CBUS to the constant generator 112.

IF stage: Instruction 2 [MOV @ (2,
R3), R1] Timing t21: Instruction 2 is read from ROM 106 and stored in instruction register 108.

<Timing t3> EX stage: Instruction 1 [MOV @ (4, R3), R
0] Timing t31: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 via the ABUS from the RLST 104. Timing t32:
Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is DES via ABUS
Stored in the register indicated by T [1: 0] (RWT
Control).

DEC stage: instruction 2 [MOV @
(2, R3), R1] Timing t31: The instruction decoding circuit 123 decodes the instruction 2 stored in the instruction register 108. The LD command determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t32: The instruction decoding circuit 123 outputs the pipeline control signal 109. BBUS
The value of the register indicated by SRC [1: 0] is read out (control by RRD). D8 (2 at this time) is read from CBUS to the constant generator 112.

IF stage: Instruction 3 [MOV @ (0,
R3), R2] Timing t31: Instruction 3 is read from ROM 106 and stored in instruction register 108.

<Timing t4> EX stage: Instruction 2 [MOV @ (2, R3), R
1] Timing t41: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t42: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: instruction 3 [MOV @
(0, R3), R2] Timing t41: The instruction decoding circuit 123 decodes the instruction 3 stored in the instruction register 108. The LD command determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t42: The instruction decoding circuit 123 outputs the pipeline control signal 109. BBUS
The value of the register indicated by SRC [1: 0] is read out (control by RRD). D8 (0 at this time) is read from the constant generator 112 in CBUS.

IF stage: Instruction 4 [ADD 6, R
3] Timing t41: Instruction 4 is read from ROM 106 and stored in instruction register 108.

<Timing t5> EX stage: Instruction 3 [MOV @ (0, R3), R
2] Timing t51: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t52: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: instruction 4 [ADD 6, R
3] Timing t51: The instruction decoding circuit 123 decodes the instruction 4 stored in the instruction register 108. R-im
The instruction determination signal 52 of m8 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t52: instruction decoding circuit 123
Then, the pipeline control signal 109 is output.

IF stage: Instruction 5 [RTS] Timing t51: Instruction 5 is read from ROM 106 and stored in instruction register 108.

<Timing t6> EX stage: Instruction 4 [ADD 6, R3] Timing t61: The value of the register indicated by DEST [1: 0] is read in ABUS (control by RRD).
In CBUS, imm8 (6 at this time) is the constant generator 112.
Read from.

Timing t62: After the values read out to ABUS and CBUS are added by the arithmetic unit 102, RLS
It is stored in the register indicated by DEST [1: 0] from T104 via ABUS (control by RWT).

DEC stage: Instruction 5 [RTS-1] Timing t61: Instruction 5 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. RTS-
The instruction determination signal 52 of 1 is output. Inversion status flag 1
The value 0 of 10 is input to the operand control circuit 53.

Timing t62: instruction decoding circuit 123
Then, the pipeline control signal 109 is output.

IF stage: Skip timing t61: Instruction fetch is skipped by the instruction determination signal 52 of RTS-1.

<Timing t7> EX stage: Instruction 5 [RTS-1] Timing t71: SP value read in BBUS is passed through the arithmetic unit 102, and then RLST 104 outputs A.
It is stored in the OAR 103 via the BUS.

Timing t72: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the PC via ABUS.

DEC stage: Instruction 5 [RTS-2] Timing t71: Instruction 5 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. RTS-
The instruction determination signal 52 of 2 is output. Inversion status flag 1
The value 0 of 10 is input to the operand control circuit 53.

Timing t72: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. BBU
The value of SP is read into S (control by RRD). C
X'02 is read from the constant generator 112 in BUS.

IF stage: instruction 6 [Next (next instruction)] Timing t71: instruction 6 is read from ROM 106 and stored in instruction register 108.

<Timing t8> EX stage: Instruction 5 [RTS-2] Timing t81: After the read values are added to BBUS and CBUS, they are stored in SP from RLST 104 via ABUS (by RWT). control).

Timing t82: Processing by the next instruction is performed.

DEC stage: instruction 6 [Next (next instruction)] Timing t81: Processing by the next instruction is performed.

Timing t82: Processing by the next instruction is performed.

IF stage: Instruction 7 [NOP] Timing t81: Instruction 7 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

As shown in the above program execution examples 1 and 2,
The data processing device according to the first exemplary embodiment uses the inversion state flag 11
When 0 is 0, the program example shown in FIG. 15 is processed.

Similarly, when the inversion state flag 110 is 0, the instruction 1 [JSR @
(LABEL1)] will be processed in a program execution example 3 (a pipeline operation diagram in FIG. 10).

Here, the operation by the command JSR @ (LABEL1) is as follows. First, the stack pointer SP is subtracted by 2 and SP is updated. The program counter 111 (PC + 2) is written to the memory address indicated by the stack pointer SP. The program counter 111 (PC) is updated to the branch destination address. The operand inversion state is set to 0.

FIG. 10 is an explanatory diagram of the pipeline operation according to the program execution example 3. Hereinafter, the operation will be described for each timing in order of the passage of time.

(Program Execution Example 3) <Timing t1> IF stage: Instruction 1 [JSR @ (LABEL1)] Timing t11: Instruction 1 is read from the ROM 106 and stored in the instruction register 108.

<Timing t2> DEC Stage: Instruction 1 [JSR-1] Timing t21: Instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. JSR-
The instruction determination signal 52 of 1 is output. Inversion status flag 1
The value 0 of 10 is input to the operand control circuit 53.

Timing t22: The instruction decoding circuit 123 outputs the pipeline control signal 109. BBUS
The SP value is read out (control by RRD). CB
X'02 is read out from the constant generator 112 in the US.

IF stage: Skip timing t21: Instruction fetch is skipped by the instruction determination signal 52 of JSR-1.

<Timing t3> EX stage: Instruction 1 [JSR-1] Timing t31: After the value read by BBUS and CBUS is subtracted, it is stored in OAR 103 from RLST 104 via ABUS. Further, the value of RLST 104 is stored in SP via ABUS (control by RWT).

Timing t32: Data is stored in the memory address indicated by the OAR 103 via the first selector 114 (control by MWT).

DEC stage: Instruction 1 [JSR-2] Timing t31: Instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. JSR-
The instruction determination signal 52 of 2 is output. Inversion status flag 1
The value 0 of 10 is input to the operand control circuit 53.

The pipeline control signal 109 is output from the instruction decoding circuit 123. The value of PC + 2 is read from the program counter 111 to BBUS. D8 (at this time, PC + 2 + d8 is a relative value where LABEL1 is the address) is read from the constant generator 112.

Timing t32: After the values of BBUS and CBUS are added, the values are stored in the PC from RLST 104 via ABUS.

IF stage: Instruction 2 [Next (Next instruction)] Timing t31: Instruction 3 is read from ROM 106 and stored in instruction register 108.

<Timing t4> EX stage: Instruction 1 [JSR-2] Timing t4: nothing is executed.

DEC stage: instruction 2 [Next (next instruction)] Timing t41: Processing by the next instruction is performed.

Timing t42: Processing by the next instruction is performed.

IF stage: Instruction 3 [NOP] Timing t41: Instruction 3 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

As described above, when the inverted state flag 110 is 0,
It has been described how the instruction (JSR) for calling the subroutine is processed by the data processing device according to the first embodiment. As described above, the data processing apparatus according to the first embodiment can execute the program example shown in FIG. 15 together with the description of the program execution example 1 and the program execution example 2 described above.

Next, by using the mechanism of the present invention, the data processing apparatus of the first embodiment will find a program example (FIG. 4) in which the code size is reduced by 3 bytes as compared with the program example shown in FIG. Will be described.

First, as the program execution example 4, when the inversion state flag 110 is 0, FRTS is invalidated by the output of the FRTS instruction invalidation signal 56, and the processing of the next instruction is continued without changing the inversion state flag 110. The operation performed will be described. Specifically, the data processing device according to the first embodiment uses the instruction 1 [MOV R2, @ (0, R
3)], instruction 2 [FRTS], and instruction 3 [SUB
R0, R0] are sequentially processed. It should be noted that the instruction 1 [SUB 6, R] arranged in the first to fourth lines in FIG.
3], instruction 2 [MOV R0, @ (4, R3)], instruction 3 [MOV R1, @ (2, R3)], instruction 4 [MOV
Regarding the operation of processing R2, @ (0, R3)],
FIG. 8 (timings t1 to t
Since it has been described using 6), it will be omitted. FIG. 11 shows
FIG. 8 is an explanatory diagram of pipeline operation according to program execution example 4. Hereinafter, the operation will be described for each timing in order of the passage of time. The inversion state flag 110 is 0 at the timing t1.

(Program execution example 4: invalidation of FRTS instruction) <Timing t1> IF stage: instruction 1 [MOV R2, @ (0, R
3)] Timing t11: Instruction 1 is read from ROM 106 and stored in instruction register 108.

<Timing t2> DEC stage: instruction 1 [MOV R2, @ (0, R
3)] Timing t21: The instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The ST instruction determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t22: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. BBU
The value of the register indicated by DEST [1: 0] is read into S (control by RRD). D8 (0 at this time) is read from the constant generator 112 in CBUS.

IF stage: Instruction 2 [FRTS] Timing t21: Instruction 2 is read from the ROM 106 and stored in the instruction register 108.

<Timing t3> EX stage: Instruction 1 [MOV R2, @ (0, R
3)] Timing t31: The values read by BBUS and CBUS are added, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t32: SRC to ABUS
The value of the register indicated by [1: 0] is read out, and the first
It is stored in the memory address indicated by OAR 103 via the selector 114 (control by MWT).

DEC stage: instruction 2 [FRTS] Timing t31: instruction 2 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The value 0 of the inversion state flag 110 is input to the instruction decoder 50 together with the instruction, and the FRTS instruction determination signal 52 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t32: The FRTS instruction invalidation signal 56 is output from the instruction decoding circuit 123.

IF stage: Instruction 3 [SUB R0, R
0] Timing t31: Instruction 3 is read from ROM 106 and stored in instruction register 108.

<Timing t4> EX stage: instruction 2 [FRTS] Timing t41: nothing is executed by the FRTS instruction invalidation signal 56.

Timing t42: Nothing is executed by the FRTS instruction invalidation signal 56.

DEC stage: instruction 3 [SUB R0,
R0] Timing t41: The instruction decoding circuit 123 decodes the instruction 3 stored in the instruction register 108. The RR command determination signal 52 is output. Inversion state flag 110
The value 0 of 0 is input to the operand control circuit 53.

Timing t42: The instruction decoding circuit 123 outputs the pipeline control signal 109.

IF stage: Instruction 4 [NOP] Timing t41: Instruction 4 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

<Timing t5> EX stage: Instruction 3 [SUB R0, R0] Timing t51: The value of the register indicated by SRC [1: 0] is read at ABUS (control by RRD). The value of the register indicated by DEST [1: 0] is read into BBUS (control by RRD).

Timing t52: After the values read out to ABUS and BBUS are subtracted by the arithmetic unit 102, RLS
It is stored in the register indicated by DEST [1: 0] from T104 via ABUS (control by RWT).

DEC stage: instruction 4 [NOP] Timing t51: No processing is performed.

Timing t52: No processing is performed.

IF stage: Instruction 5 [NOP] Timing t51: Instruction 5 is read from ROM 106 and stored in instruction register 108. NOP does nothing and proceeds to the next instruction.

As described above, in the program execution example 4, since the inversion state flag 110 is 0, FRTS becomes FR.
It is invalidated by the output of the TS command invalidation signal 56, and the processing of the next instruction is continued without changing the inversion state flag 110.

Next, as a program execution example 5, the data processing apparatus according to the first embodiment executes the instruction 1 [FJSR @
The operation of making a subroutine call with (LABEL2)] and then returning with a subroutine by an instruction 5 [FRTS] will be described. Specifically, command 1 [FJSR
@ (LABEL2)] is decoded, a subsequent instruction 2 is set by setting the inversion state flag 110 to 1.
[MOV R0, @ (4, R3)], instruction 3 [MOV
R1, @ (2, R3)], instruction 4 [MOV R2, @
An operand access control signal 54 for inverting the data transfer destination and the data transfer source of (0, R3)] is output. Further, when the instruction 5 [FRTS] is decoded by the instruction decoder 50, since the inversion state flag 110 which is the input of the instruction decoder 50 is 1, the instruction determination signal 5 of FRTS-1
2 is output and the instruction 5 [FRTS] is executed without being invalidated. In the process, the inversion state flag 110 is reset to 0, and a process of sequentially processing the instructions subsequent to the instruction 6 [ADD 6, R3] with the inversion state flag 110 set to 0 will be described.

The range of the explanation in this program execution example 5 is that the data processor according to the first embodiment executes the instruction 1 [FJ.
SR @ (LABEL2)], instruction 2 [MOV R0,
@ (4, R3)], instruction 3 [MOV R1, @ (2, R
3)], instruction 4 [MOV R2, @ (0, R3)], instruction 5 [FRTS], and instruction 6 [ADD 6, R3] are sequentially processed, but instruction 6 [ADD 6, R3] is processed. The pipeline operation of the succeeding instruction 7 [RTS] is the same as that already described in the program execution example 2 (timing t4 to t8), and therefore the description thereof is omitted here.

12 and 13 are explanatory diagrams of the pipeline operation according to the program execution example 5. 12 and 13
In FIG. 12, the program execution example 5 is illustrated at successive timings t1 to t10.
6, t7, t8 and the timings t6, t7, t8 in FIG.
Represents the same timing. Hereinafter, the operation will be described for each timing in order of the passage of time.
The inversion state flag 110 is 0 at the timing t1.

(Program execution example 5: FJSR to FR
Explanation up to TS) <Timing t1> IF stage: instruction 1 [FJSR @ (LABEL
2)] Timing t11: Instruction 1 is read from ROM 106 and stored in instruction register 108.

<Timing t2> DEC Stage: Instruction 2 [FJSR-1] Timing t21: Instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. FJSR
The instruction determination signal 52 of -1 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t22: The instruction decoding circuit 123 outputs the pipeline control signal 109. BBUS
The SP value is read out (control by RRD). CB
X'02 is read out from the constant generator 112 in the US.

IF stage: Skip timing t21: Instruction fetch is skipped by the instruction determination signal 52 of FJSR-1.

<Timing t3> EX stage: Instruction 1 [FJSR-1] Timing t31: After the values read by BBUS and CBUS are subtracted, they are stored in the OAR 103 from the RLST 104 via ABUS. Further, the value of RLST 104 is stored in SP via ABUS (control by RWT).

Timing t32: Data is stored in the memory address indicated by the OAR 103 via the first selector 114 (control by MWT).

DEC stage: Instruction 1 [FJSR-2] Timing t31: Instruction 1 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. FJSR
-2 instruction determination signal 52 is output. Instruction decoding circuit 1
23, the pipeline control signal 109 is output. B
The value of PC + 2 is read from the program counter 111 to BUS. D8 on CBUS (at this time, PC + 2 +
The constant generator 1 is the relative value where d8 is LABEL2.
12 is read.

Timing t32: After the values of BBUS and CBUS are added, the values are stored in the PC from the RLST 104 via ABUS. The value of the inverted state flag 110 is updated by the instruction decoder 50 from 0 to 1.

IF stage: Instruction 2 [MOV R0, @
(4, R3)] Timing t31: Instruction 2 is read from the ROM 106 and stored in the instruction register 108.

<Timing t4> DEC stage: instruction 2 [MOV R0, @ (4, R
3)] Timing t41: The instruction 2 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The ST instruction determination signal 52 is output. The value 1 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t42: The pipeline control signal 109 is output from the instruction decoding circuit 123 (since the value of the inversion state flag 110 is 1, pipeline control corresponding to the LD instruction type is performed). Operand control circuit 53 outputs an operand access control signal 54 in response to a row in which instruction determination signal 52 is ST and inversion state flag 110 is 1. The value of the register indicated by SRC [1: 0] is read into BBUS (control by RRD). D8 (4 at this time) is a constant generator 11 in CBUS
2 is read.

IF stage: Instruction 3 [MOV R1, @
(2, R3)] Timing t41: Instruction 3 is read from the ROM 106 and stored in the instruction register 108.

<Timing t5> EX stage: Instruction 2 [MOV R0, @ (4, R
3)] Timing t51: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t52: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: instruction 3 [MOV R1,
@ (2, R3)] Timing t51: The instruction 3 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The ST instruction determination signal 52 is output. The value 1 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t52: The pipeline control signal 109 is output from the instruction decoding circuit 123 (since the value of the inversion state flag 110 is 1, pipeline control corresponding to the LD instruction type is performed). Operand control circuit 53 outputs an operand access control signal 54 in response to a row in which instruction determination signal 52 is ST and inversion state flag 110 is 1. The value of the register indicated by SRC [1: 0] is read into BBUS (control by RRD). D8 (2 at this time) is a constant generator 11 in CBUS
2 is read.

IF stage: Instruction 4 [MOV R2, @
(0, R3)] Timing t31: Instruction 4 is read from ROM 106 and stored in instruction register 108.

<Timing t6> EX stage: Instruction 3 [MOV R1, @ (2, R
3)] Timing t61: The values read by BBUS and CBUS are added, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t62: Data is loaded from the memory address indicated by OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: instruction 4 [MOV R2,
@ (0, R3)] Timing t61: The instruction decoding circuit 123 decodes the instruction 3 stored in the instruction register 108. The ST instruction determination signal 52 is output. The value 1 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t62: The pipeline control signal 109 is output from the instruction decoding circuit 123 (since the value of the inversion state flag 110 is 1, pipeline control corresponding to the LD instruction type is performed). Operand control circuit 53 outputs an operand access control signal 54 in response to a row in which instruction determination signal 52 is ST and inversion state flag 110 is 1. The value of the register indicated by SRC [1: 0] is read into BBUS (control by RRD). D8 (0 at this time) is a constant generator 11 in CBUS
2 is read.

IF stage: Instruction 5 [FRTS] Timing t61: Instruction 5 is read from ROM 106 and stored in instruction register 108.

<Timing t7> EX stage: Instruction 4 [MOV R2, @ (0, R
3)] Timing t71: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 via the ABUS from the RLST 104.

Timing t72: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: Instruction 5 [FRTS-1] Timing t71: Instruction 5 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The value 1 of the inversion status flag 110 is input to the instruction decoder 50 together with the instruction. At this time, since the value of the inverted state flag 110 is 1, the instruction determination signal 52 of FRTS-1 is output. The value 1 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t72: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. Operand control circuit 53 outputs an operand access control signal 54 corresponding to the FRTS-1 instruction.

IF stage: Skip timing t71: Instruction fetch is skipped by the instruction determination signal 52 of FRTS-1.

<Timing t8> EX stage: Instruction 5 [FRTS-1] Timing t81: SP value read out in BBUS is passed through the arithmetic unit 102, and then RLST 104 outputs A.
It is stored in the OAR 103 via the BUS.

Timing t82: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the PC via ABUS.

DEC stage: Instruction 5 [FRTS-2] Timing t81: Instruction 5 stored in the instruction register 108 is decoded again by the instruction decoding circuit 123. FR
The instruction determination signal 52 of TS-2 is output. The value of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t82: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. Operand control circuit 53 outputs an operand access control signal 54 corresponding to the FRTS-2 instruction. BBU
The value of SP is read into S (control by RRD). C
X'02 is read from the constant generator 112 in BUS. Further, the value of the inversion state flag 110 is reset from 1 to 0.

IF stage: Instruction 6 [ADD 6, R
3] Timing t81: Instruction 6 is read from ROM 106 and stored in instruction register 108.

<Timing t9> EX stage: Instruction 5 [FRTS-2] Timing t91: After the values read to BBUS and CBUS are added, they are stored in SP from RLST 104 via ABUS (by RWT). control).

Timing t92: Nothing is executed.

DEC stage: instruction 6 [ADD 6, R
3] Timing t91: The instruction decoding circuit 123 decodes the instruction 6 stored in the instruction register 108. R-im
The instruction determination signal 52 of m8 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t92: instruction decoding circuit 123
Then, the pipeline control signal 109 is output.

IF stage: Instruction 7 [next instruction] Timing t91: Description is omitted.

<Timing t10> EX stage: Instruction 6 [ADD 6, R3] Timing t101: The value of the register indicated by DEST [1: 0] is read in ABUS (control by RRD). Imm8 (6 at this time) is read from the constant generator 112 in CBUS.

Timing t102: ABUS and CBUS
After the value read out to the
It is stored in the register indicated by DEST [1: 0] from ST104 via ABUS (control by RWT).

DEC stage: instruction 7 [next instruction] Timing t101: Description is omitted.

Timing t102: Description is omitted.

IF stage: Description is omitted.

Timing t101: Description is omitted.

As described above, in the program execution example 5, the data processing apparatus according to the first embodiment has the instruction 1 [FJSR.
@ (LABEL2)] is executed (DEC stage timing t32) to set the inversion state flag 110 to 1, so that the instruction 2 [MOV R0, @ (4,
R3)], instruction 3 [MOV R1, @ (2, R3)],
The operand access control signal 54 for inverting the data transfer destination and the data transfer source of the instruction 4 [MOV R2, @ (0, R3)] is output. Further, when the instruction 5 [FRTS] is decoded by the instruction decoder 50 (timing t7
1), the inversion state flag 11 which is the input of the instruction decoder 50
Since 0 is 1, the instruction determination signal 52 of FRTS-1 is output, and this instruction is executed without being invalidated as described in the instruction 2 [FRTS] of the program execution example 4. In the execution process, the inversion state flag 110 is reset to 0 (timing t82), and the instruction 6 [ADD 6, R
3] and subsequent instructions are sequentially processed with the value 0 of the inversion state flag 110.

As described above, according to the data processing device of the first embodiment, program execution examples 1 and 2 show examples of programs executed by the conventional data processing device shown in FIG. In addition to being executed as described above, the program example of FIG. 4 can be executed as shown in the program execution examples 4 and 5. That is, the degree of freedom in selecting a program example (FIG. 4) having a smaller code size than that of the program example of FIG. 15 is increased.

This is to invert the data transfer source and the transfer destination when the instruction [FJSR] for controlling the instruction execution order is decoded, update the inversion state flag 110, and similarly control the instruction execution order. Order [FRTS]
When the reverse state flag 110 is 0, the instruction [FRTS] is set only when the reverse state flag 110 is 0.
This is because the program code size is reduced by disabling.

More specifically, with a small change from the program description shown in the program example of FIG. 15, an instruction group to be reused that is not a subroutine (from the second line of the program example shown in FIG. 4th line), the command [FJS
R] and instruction [FRTS] can be efficiently reused (redundant program code can be replaced by two instructions).

[0195] Furthermore, 2 of the program example of FIG.
Since the instructions arranged on the 4th to 4th lines can be called as a subroutine by FJSR from another program, the effect of reducing the program size is further enhanced by using this.

[Embodiment 2] Referring to FIG. 1, FIG. 2, FIG. 3, FIG. 5, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. Explain. In addition,
The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

FIG. 5 shows an example of a program executed by the data processing device of the second embodiment. In this program example, each instruction is represented by mnemonic. Below, a brief description is given for each instruction of the program example shown in FIG. The value in [] is the code size of the instruction.

First line: SUB 6, R3 (immediate value 6 is subtracted from the value in the R3 register and the result is stored in the R3 register. LABEL1: indicates an address.) [2byt
e] Second line: JSR @ (LABEL2) (Decrement stack pointer SP by 2 to update SP. Write program counter 111 (PC + 2) to the memory address indicated by stack pointer SP. Set inversion state flag 110 to 0, The program counter 111 (PC) [points to the next instruction on the third line] is updated to LABEL 2.) [2b
yte] third line: SUB R0, R0 (value of R0 register and R
The value of the 0 register is subtracted and stored in the R0 register. )
[1 byte] Fourth line: Process (This process is a data process consisting of a plurality of instructions, and the R0 register, the R1 register, and the R2 register may be rewritten.) The fifth line: FJSR @ (LABEL2) (The stack pointer SP is decremented by 2 and SP is updated. The program counter 111 (PC + 2) [points to the next instruction on the sixth line] is written to the memory address indicated by the stack pointer SP. Then, the program counter 111 (PC) is updated to LABEL2.) [2
byte] 6th line: ADD 6, R3 (immediate value 6 is added to the value of the R3 register and the result is stored in the R3 register.) [2
byte] 7th line: RTS (Return from subroutine. Memory is read by using the contents of stack pointer SP as an address and the contents are stored in program counter 111 (PC). 2 is added to the stack pointer and SP is updated. The status flag 110 is reset to 0.)
[1 byte] 8th line: MOV R0, @ (4, R3) (The value of the R0 register is stored in the memory at the address obtained by adding the R3 register and the immediate value 4. LABEL2: indicates the address.) [2 byte] 9th line: MOV R1, @ (2, R3) (The value of the R1 register is stored in the memory at the address obtained by adding the R3 register and the immediate value 2.) [2byte] 10th line: MOV R2, @ (0, R3 (The value of the R2 register is stored in the memory of the address obtained by adding the R3 register and the immediate value 0.) [2 byte] 11th line: RTS (Return from the subroutine.
The memory is read by using the contents of the stack pointer SP as an address, and the contents are read by the program counter 111 (PC).
To store. Add 2 to the stack pointer and update SP. The inversion state flag 110 is reset to 0. )
[1 byte] In this program example, the instruction [JSR @ (LABEL
2)] and the instruction [FJSR @ (LABEL2)], the data processing by the subroutine from the 8th line to the 11th line can be realized in two ways.

The structure of the instruction decoding circuit according to the second embodiment is as shown in FIG. 3 and has been described in the first embodiment. FIG. 7 is an explanatory diagram showing input / output signals of the operand control circuit 53 according to the second embodiment. Here, the rows of the instruction determination signal 52 of RTS-1 and RTS-2 are different from those in FIG. That is, even when the inversion state flag 110 is 1, RTS-1 and RTS-2 are executed and RTS-1 and RTS-2 are executed.
It is shown that the inversion state flag 110 is reset from 1 to 0 by decoding -2.

In addition, FJSR-2 and FRTS- in FIG.
2 and RTS-2, an arrow is shown in the column of the inversion state flag 110, but the inversion state flag 110 is indicated by an arrow according to the timing described in the first embodiment and a timing (RTS-2) described later. It means changing from the value shown on the left to the value shown on the right.

How the data processing device of the second embodiment having the above-mentioned configuration processes the program example (FIG. 5) in which the code size is reduced by 2 bytes compared to the program example 1 will be described. .

First, the first half of this program example, instruction 1 [SUB 6, R3], instruction 2 [JSR @ (LAB
EL2)], instruction 3 [MOV R0, @ (4, R
3)], instruction 4 [MOV R1, @ (2, R3)], instruction 5 [MOV R2, @ (0, R3)], instruction 6 [RT
S] and instruction 7 [SUB R0, R0].

In the case of instruction 1, the inversion state flag 110 is 0. Next, in the instruction 2 [JSR @ (LABEL2)] (the execution order is shifted to the instruction indicated by LABEL2), J
SR-1, JSR-2, and the inversion state flag 110 is 0
(FIG. 7). At this time, the inversion state flag 110 remains 0. Furthermore, instruction 3 to instruction 5
Are executed with the inversion state flag 110 set to 0.

Next, in the instruction 6 [RTS] (moving the execution order to the instruction 7), RTS-1, RTS-2 and the inversion state flag 110 are controlled in accordance with the line of 0 (FIG. 7). At this time, the inversion state flag 110 remains 0 and is not updated. Then, the instruction 7 is executed with the inversion state flag 110 set to 0. That is, the instruction 1 is shown in FIG. 8 (timings t1 to t3), and the instruction 2 is shown in FIG. 10 (timings t1 to t3).
At t4), the instruction 3 to the instruction 5 are shown in FIG.
6), the instruction 6 performs the operation already described with reference to FIG. 9 (timing t5 to t8) and the instruction 7 with reference to FIG. 8 (timing t5 to t7).

Next, the second half of the program example of FIG. 5 is instruction 1 [FJSR @ (LABEL2)], instruction 2 [MO.
V R0, @ (4, R3)], instruction 3 [MOV R1,
@ (2, R3)], instruction 4 [MOV R2, @ (0, R
3)], instruction 5 [RTS], instruction 6 [ADD 6, R
3], a series of operations up to the instruction 7 [RTS] will be described.

Instruction 1 [FJSR @ (LABEL2)]
Then (moving the execution order to the instruction indicated by LABEL2), the FJSR-1, FJSR-2, and the inversion state flag 110 are controlled according to the row of 0 (FIG. 7). At this time, the inversion state flag 110 is updated from 0 to 1 in FRTS-2. Further, the instruction 2 to the instruction 4 are in the inverted state flag 1
10 is executed as 1. Next, in the instruction 5 [RTS] (moving the execution order to the instruction 6), RTS-1, RTS-2
And the inversion state flag 110 is controlled according to the row of 1 (FIG. 7). At this time, the inversion state flag 110 is set to RTS-2.
Is reset from 1 to 0. This operation is the second embodiment.
It is possible to consider that the command 5 [RTS] is executed and reset to 0 by RTS-2 regardless of the value of the inversion state flag 110, although it is a function provided in the data processing device according to.
Next, the instructions 6 and 7 are executed with the inversion state flag 110 set to 0.

It should be noted that the instructions 1 to 4 operate as already described with reference to FIG. 12 (timings t1 to t7) and the instructions 6 and 7 with FIG. 9 (timings t4 to t8). Therefore, here, only how the instruction 5 [RTS] is processed when the value of the inversion state flag 110 is 1 will be described.

As a sixth program execution example, in order to explain how to process the instruction 5 [RTS] when the value of the inversion state flag 110 is 1, the instruction 4 [MOV R2,
@ (0, R3)] to command 5 [RTS], command 6 [AD
D 6, R 3] are sequentially processed by the data processing device according to the second embodiment (however, for instruction 4, only the EX stage is described).

FIG. 14 is an explanatory diagram of the pipeline operation according to the program execution example 6. Hereinafter, the operation will be described for each timing in order of the passage of time. The inversion state flag 110 is set to the instruction 1 [FJSR @ (LABEL
2)], the timing is t1.
Is 1 when.

(Program execution example 6: Inversion state flag 1)
RTS operation for resetting 10) <Timing t1> IF stage: instruction 5 [RTS] Timing t11: Instruction 5 is read from the ROM 106 and stored in the instruction register 108.

<Timing t2> EX stage: Instruction 4 [MOV R2, @ (0, R
3)] Timing t21: After the values read by BBUS and CBUS are added, the values are stored in the OAR 103 from the RLST 104 via ABUS.

Timing t22: Data is loaded from the memory address indicated by OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the register indicated by DEST [1: 0] via ABUS (control by RWT).

DEC stage: Instruction 5 [RTS-1] Timing t21: Instruction 5 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The value 1 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50. Command determination signal 52 of RTS-1
Is output.

Timing t22: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. Operand control circuit 53 outputs an operand access control signal 54 corresponding to the RTS-1 instruction.

IF stage: Skip timing t21: Instruction fetch is skipped by the instruction determination signal 52 of RTS-1.

<Timing t3> EX stage: Instruction 5 [RTS-1] Timing t31: SP value read in BBUS is passed through the arithmetic unit 102, and then RLST 104 outputs A.
It is stored in the OAR 103 via the BUS.

Timing t32: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the PC via ABUS.

DEC stage: Instruction 5 [RTS-2] Timing t31: Instruction 5 stored in the instruction register 108 is decoded again by the instruction decoding circuit 123. RT
The instruction determination signal 52 of S-2 is output. The value of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t32: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. The operand control circuit 53 outputs an operand access control signal 54 corresponding to the RTS-2 instruction. The SP value is read into BBUS (control by RRD). CBU
X'02 is read from S from the constant generator 112. Further, the value of the inversion state flag 110 is reset from 1 to 0.

IF stage: Instruction 6 [ADD 6, R
3] Timing t31: Instruction 6 is read from ROM 106 and stored in instruction register 108.

<Timing t4> EX stage: Instruction 5 [RTS-2] Timing t41: After the values read to BBUS and CBUS are added, the values are stored in SP from RLST 104 via ABUS (by RWT). control). Timing t42: Nothing is executed.

DEC stage: instruction 6 [ADD 6, R
3] Timing t41: The instruction 6 stored in the instruction register 108 is decoded by the instruction decoding circuit 123. R-im
The instruction determination signal 52 of m8 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53.

Timing t42: instruction decoding circuit 123
Then, the pipeline control signal 109 is output.

IF stage: Instruction 7 [next instruction] Timing t41: Description is omitted.

<Timing t5> EX stage: Instruction 6 [ADD 6, R3] Timing t51: The value of the register indicated by DEST [1: 0] is read in ABUS (control by RRD).
In CBUS, imm8 (6 at this time) is the constant generator 112.
Read from.

Timing t52: The values read out to ABUS and CBUS are added by the arithmetic unit 102, and then RLS is passed.
It is stored in the register indicated by DEST [1: 0] from T104 via ABUS (control by RWT).

DEC stage: instruction 7 [next instruction] Timing t51: Description is omitted.

Timing t52: Description is omitted.

IF stage: Description is omitted.

Timing t51: Description is omitted.

As described above, in the program execution example 6, when the inversion state flag 110 is set to 1 and the instruction 5 [RTS] is decoded, along with the decoding of the instruction determination signal 52 of RTS-2, the DEC stage of timing t32 The inversion state flag 110 is reset from 1 to 0. This operation is a function provided in the data processing device according to the second embodiment, but the command 5 is executed regardless of the value of the inversion state flag 110.
[RTS] will be executed and reset to 0 by RTS-2.

As a result, the command [JSR @ (LAB
EL2)] and command [FJSR @ (LABEL2)]
Then, there are two types of data processing by the subroutine from the 8th line to the 11th line of the program example 3. Here, in the program example shown in FIG. 4, it is possible to make a subroutine call to the instructions arranged in the second to fourth lines from another program by using only FJSR.
On the other hand, according to the data processing device of the second embodiment, it is possible to selectively use FJSR and JSR and make a subroutine call. This increases the possibility of reusing the subroutine and improves the effect of reducing the program size.

[Third Embodiment] The third embodiment of the present invention will be described below with reference to FIGS. 3, 7, 17, 18, 19, and 2.
0 will be described with reference to FIG. In the data processing device according to the third embodiment, the data processing device according to the second embodiment is added with a function of processing an instruction [MOV @ (R0, R1), @ (R0, R2)]. Therefore, components having the same configurations as those of the second embodiment described above are designated by the same reference numerals and description thereof will be omitted. The instruction [MOV @ (R
0, R1), @ (R0, R2)] loads data from an address where the value of register R0 and the value of register R1 are added, and data is added to the address where the value of register R0 and the value of register R2 are added. This is an instruction to store.

FIG. 19 shows the configuration of the data processing device according to the third embodiment. Reference numeral 116 is an LDB for temporarily storing load data. This data processing device is different from the data processing device described with reference to FIG. 2 in that an LDB 116 is added, and the LDB 116 temporarily stores the loaded data and stores the loaded data via the second selector 115. And output the data.

FIG. 17 is an explanatory diagram of instructions added in the third embodiment. Here, the instruction format f6 in FIG. 17A is composed of 2 bytes. Also, reg1 [1:
0] and dreg [1: 0] are added to be the load memory address, and reg2 [1: 0] and dre [1: 0] are added.
The address to which g [1: 0] is added becomes the memory address to be stored. When the instruction decoding circuit 123 decodes the instruction, reg1 [1: 0], reg2 [1: 0], d
It is assumed that the field of reg [1: 0] is known.

FIG. 17B shows the instruction type, instruction format, and instruction code. FIG. 17
When the instruction code of (b) is decoded by the instruction decoder 50, it is determined as the instruction type LDST, and the instruction determination signal 52 corresponding to the stage is output.

FIG. 18 is an explanatory diagram showing input / output signals of the operand control circuit added according to the third embodiment.
18 is added to FIG. 7 to add a function. The command determination signals 52 [LDST-1] and [LDST-2] are
Instruction [MOV @ (R0, R1), @ (R0, R2)]
Is an instruction decision signal 52 that is output when the instruction decoder 50 decodes, and is added to the instruction decision types described in the description of FIG. 3, and the DEC stage and the EX stage each have two stages. It is processed.

Here, when the value of DIR is 1, reg1
The address obtained by adding [1: 0] and dreg [1: 0] is the transfer source, and reg2 [1: 0] and dreg [1:
0] is added to the transfer destination. On the contrary, DI
When the value of R is 0, reg2 [1: 0] and dreg
The address to which [1: 0] is added becomes the transfer source, and reg
The address obtained by adding 1 [1: 0] and dreg [1: 0] is the transfer destination.

With the configuration according to the third embodiment described above, the instruction code shown in FIG. 17B can be processed.
When it is decoded, as shown in FIG. 18, the operand access control signal 54 is output according to the value of the inversion state flag 110. Hereinafter, the operation of processing the additional instruction of the third embodiment when the inversion state flag 110 is 0 (program execution example 7), and the inversion state flag 1
The operation (program execution example) of processing the additional instruction when 10 is 1 will be described respectively.

First, as a program execution example 7, an instruction [MOV is executed by the data processing device according to the third embodiment.
The operation of processing @ (R0, R1), @ (R0, R2)] with the value 0 of the inversion state flag 110 will be described. Figure 20
FIG. 14 is an explanatory diagram of pipeline operation according to program execution example 7. Hereinafter, the operation will be described for each timing in order of the passage of time (the inversion state flag 110 is 0 at the timing t1).

(Program execution example 7: Inversion state flag 1)
Operation of additional instruction when 10 is 0) <Timing t1> IF stage: instruction [MOV @ (R0, R1), @
(R0, R2)] Timing t11: The instruction is read from the ROM 106,
It is stored in the instruction register 108.

<Timing t2> DEC stage: instruction [LDST-1: MOV @
(R0, R1), @ (R0, R2)] Timing t21: The instruction stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The value 0 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50. LDST-1 instruction determination signal 52
Is output.

Timing t72: The instruction decoding circuit 123 outputs the pipeline control signal 109. The operand control circuit 53 outputs an LDST-1 instruction determination signal and an operand access control signal 54 in which the value of the inversion state flag 110 is 0. BBUS to SRC
The value of the register indicated by [1: 0] is read (R
Control by RD). The value of the register R0 corresponding to dreg [1: 0] is read to ABUS.

<Timing t3> EX stage: instruction [LDST-1: MOV @
(R0, R1), @ (R0, R2)] Timing t31: The read values are added to ABUS and BBUS, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t32: Data is loaded from the memory address indicated by the OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the LDB 116 via ABUS.

DEC stage: instruction [LDST-2:
MOV @ (R0, R1), @ (R0, R2)] Timing t31: The instruction stored in the instruction register 108 is decoded again by the instruction decoding circuit 123. LDS
The instruction determination signal 52 of T-2 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t32: The instruction decoding circuit 123 outputs the pipeline control signal 109. The operand control circuit 53 outputs an LDST-1 instruction determination signal and an operand access control signal 54 in which the value of the inversion state flag 110 is 0. BBUS to DEST
The value of the register indicated by [1: 0] is read (R
Control by RD). The value of the register R0 corresponding to dreg [1: 0] is read to ABUS.

<Timing t4> EX stage: instruction [LDST-2: MOV @
(R0, R1), @ (R0, R2)] Timing t41: The values read out to ABUS and BBUS are added, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t42: LDB to the memory address indicated by OAR 103 via the first selector 114.
The data stored in 116 is stored (control by MWT).

Next, as a program execution example 8, an instruction [MOV @ is issued by the data processing device according to the third embodiment.
The operation of processing (R0, R1), @ (R0, R2)] with the value 1 of the inversion state flag 110 will be described. FIG. 21 shows
FIG. 16 is an explanatory diagram of pipeline operation according to program execution example 8. Hereinafter, the operation will be described for each timing in the order in which time elapses (inversion state flag 1 at timing t1
10 is 1).

(Program execution example 8: Inversion state flag 1)
Operation of additional instruction when 10 is 1) <Timing t1> IF stage: instruction [MOV @ (R0, R1), @
(R0, R2)] Timing t11: The instruction is read from the ROM 106,
It is stored in the instruction register 108.

<Timing t2> DEC stage: instruction [LDST-1: MOV @
(R0, R1), @ (R0, R2)] Timing t21: The instruction stored in the instruction register 108 is decoded by the instruction decoding circuit 123. The value 1 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50. LDST-1 instruction determination signal 52
Is output.

Timing t72: instruction decoding circuit 123
Then, the pipeline control signal 109 is output. The operand control circuit 53 outputs an instruction determination signal of LDST-1 and an operand access control signal 54 in which the value of the inversion state flag 110 corresponds to 1. BBUS to SRC
The value of the register indicated by [1: 0] is read (R
Control by RD). The value of the register R0 corresponding to dreg [1: 0] is read to ABUS.

<Timing t3> EX stage: instruction [LDST-1: MOV @
(R0, R1), @ (R0, R2)] Timing t31: The read values are added to ABUS and BBUS, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t32: Data is loaded from the memory address indicated by OAR 103 via the first selector 114 (control by MRD). The loaded data is stored in the LDB 116 via ABUS.

DEC stage: instruction [LDST-2:
MOV @ (R0, R1), @ (R0, R2)] Timing t31: The instruction stored in the instruction register 108 is decoded again by the instruction decoding circuit 123. LDS
The instruction determination signal 52 of T-2 is output. The value 0 of the inversion state flag 110 is input to the operand control circuit 53 and the instruction decoder 50.

Timing t32: The instruction decoding circuit 123 outputs the pipeline control signal 109. The operand control circuit 53 outputs an LDST-2 instruction determination signal and an operand access control signal 54 corresponding to the value of the inversion state flag 110 being 1. BBUS to DEST
The value of the register indicated by [1: 0] is read (R
Control by RD). The value of the register R0 corresponding to dreg [1: 0] is read to ABUS.

<Timing t4> EX stage: instruction [LDST-2: MOV @
(R0, R1), @ (R0, R2)] Timing t41: The values read out to ABUS and BBUS are added, and then stored in the OAR 103 from the RLST 104 via ABUS.

Timing t42: LDB to the memory address indicated by the OAR 103 via the first selector 114.
The data stored in 116 is stored (control by MWT).

In the above program execution example 7, data is transferred from the memory whose address is the added value of the register R0 and register R1 which is the transfer source to the memory whose address is the added value of the register R0 and register R2 which is the transfer destination. Transfers are being made. On the other hand, in Program Execution Example 8, data is transferred from a memory whose address is the added value of the register R0 and register R2 which is the transfer source to a memory whose address is the added value of the register R0 and register R1 which is the transfer destination. ing. As shown in FIG. 18, this corresponds to SRC [1: 0] and DE depending on the value of the inversion state flag 110.
This is because the ST [1: 0] operand access control signal 54 is configured to be inverted.

Using this instruction, as an example, it is possible to construct an instruction group for performing batch data transfer processing from the memory area having the leading address R1 to the memory area having the leading address R2 while incrementing the value of R0. The instruction to add the value of R0 is not included in the specific instruction to invert, and does not hinder the increment operation. The data processing apparatus according to the third embodiment includes the control mechanism that reverses the data transfer source and the transfer destination even in the data transfer from the memory to the memory as described in the first and second embodiments. It becomes more practical and the program code size can be reduced by combining with this mechanism.

The inversion target instruction according to the present invention is not particularly limited to the inversion target instruction specified by the operand control circuit (including the inversion instruction storage means) according to the first to third embodiments. Further, there are a plurality of instructions corresponding to FJSR, and the inversion target instructions corresponding to each of the plurality of instructions are defined, and the inversion instruction storage means stores the inversion target instructions according to the plurality of instructions, and It is also possible to adopt a configuration in which the inversion control is performed only for the inversion target instruction.

[0263]

As described above, according to the data processing device of the present invention, only the target instruction for inverting the data transfer source and the transfer destination is in accordance with the instruction from the inversion state storage means.
Since the operand control circuit inverts the data transfer source and the transfer destination and two types of data transfer processing that can be processed by one instruction group can be performed, redundant program codes can be reduced and the program code size can be reduced. Contributes to capacity.

Further, according to the data processor of the present invention,
When the second instruction is decoded, the instruction execution order is directly controlled, and then data processing is performed by one instruction group, the target instruction whose data transfer source and transfer destination are inverted is explicitly indicated, and the instruction is executed. When the first instruction that directly controls the order is decoded, similarly, the execution order of the instructions is directly controlled, and then data processing different from the above is performed by one instruction group, and when the third instruction is decoded, it is inverted. It is possible to perform the operation of returning to the state before the update regardless of the state. That is, when the instruction execution order is transferred to one instruction group, different data transfer processing is performed depending on either the first instruction or the second instruction, and the data transfer source and the transfer destination are treated at the time of return. Since it is possible to return to the normal state, redundant program code can be reduced and a subroutine by one instruction group can be called any number of times by two kinds of processing, which increases the degree of freedom in programming. .

Further, according to the data processing apparatus of the present invention, the second instruction is read only when the first instruction is decoded and the inversion state is inversion for inversion of the data transfer source and the transfer destination.
Command is valid. As a result, when the inverted state is not updated by the first instruction, the second instruction is invalidated, and unnecessary return processing is not performed. Further, only when the execution order of the instructions is directly controlled by one instruction group by the first instruction, a data transfer processing different from the normal one is requested, and the execution order of the instruction which becomes the return processing by the second instruction. It is possible to return the inversion state to the state before the update, assuming that the data transfer source and the transfer destination are not inverted after the control. In other words, by shifting the instruction execution order to one instruction group by the first instruction, it becomes possible to request different data transfer processing and return to normal when returning.
According to this configuration, it is possible to efficiently reuse a non-subroutine instruction group to be reused by the first instruction and the second instruction by reducing changes from the conventional program description (redundant program). You can replace the code with two instructions). Further, since the subroutine can be called again by the first instruction, the effect of reducing the program size is further enhanced by utilizing this.

As described above, the data processing device according to the present invention contributes to the reduction in the capacity of the program code size, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of an instruction code of a data processing device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a data processing device according to the present invention.

FIG. 3 is a block diagram showing a configuration of an instruction decoding circuit according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a program executed by the data processing device according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a program executed by the data processing device according to the second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing input / output signals of the operand control circuit according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram showing input / output signals of the operand control circuit according to the second embodiment of the present invention.

FIG. 8 is an explanatory diagram of pipeline operation according to program execution example 1.

FIG. 9 is an explanatory diagram of a pipeline operation according to program execution example 2.

FIG. 10 is an explanatory diagram of a pipeline operation according to a program execution example 3.

FIG. 11 is an explanatory diagram of pipeline operation according to program execution example 4.

FIG. 12 is an explanatory diagram of pipeline operation according to program execution example 5 (first half).

FIG. 13 is an explanatory diagram of pipeline operation according to program execution example 5 (second half).

FIG. 14 is an explanatory diagram of pipeline operation according to program execution example 6;

FIG. 15 is an explanatory diagram of a program example executed by a conventional data processing device.

FIG. 16 is an explanatory diagram showing an instruction format by the data processing device of the present invention.

FIG. 17 is an explanatory diagram of instructions added in the third embodiment of the present invention.

FIG. 18 is an explanatory diagram showing input / output signals of an operand control circuit added according to the third embodiment of the present invention.

FIG. 19 is a block diagram showing the configuration of a data processing device according to a third embodiment of the present invention.

FIG. 20 is an explanatory diagram of a pipeline operation according to the program execution example 7.

FIG. 21 is an explanatory diagram of a pipeline operation according to the program execution example 8.

[Explanation of symbols]

50 Instruction Decoder 52 Command judgment signal 53 Operand control circuit 54 Operand access control signal 56 FRTS command invalidation signal 102 arithmetic unit 103 OAR 104 RSLT 105 register file 106 ROM 108 Instruction register 109 Pipeline control signal 110 Inversion status flag 111 program counter 112 Constant generator 113 PC bus 114 first selector 115 Second selector 116 LDB 122 Bus interface circuit 123 Instruction decoding circuit 125 instruction read circuit

Claims (3)

[Claims] 1. A data processing device comprising: a fetch unit for sequentially reading instructions; a decoding unit for decoding the read instructions; and an execution unit for executing the decoded instructions, wherein a data transfer source and a transfer destination are provided. An inversion instruction storage unit that stores a target instruction to be inverted; an inversion state storage unit that stores an inversion state identifier that indicates whether or not the target instruction is inverted and executed;
A data processing device, comprising: an operand control unit for inverting a data transfer source and a transfer destination described in an instruction. 2. A first instruction that directly specifies the target instruction and directly controls the execution order of the instructions, a second instruction that directly controls the execution order of the instructions, and the first instruction or the second instruction. An instruction storing unit that stores a third instruction that directly controls the execution order of the instruction in pair with the instruction of, and the first instruction of the first instruction and the second instruction.
The inversion state identifier is updated so as to invert the data transfer source and the transfer destination only when the instruction is decoded, and the data transfer source and the transfer destination are not inverted when the third instruction is decoded. The data processing device according to claim 1, further comprising an inversion state updating unit that returns the inversion state identifier before updating. 3. A first instruction that explicitly specifies the target instruction and directly controls the execution order of the instruction, and a second instruction that pairs with the first instruction and directly controls the execution order of the instruction. And an instruction storing means for storing the instruction, and the inversion state identifier is updated so as to invert the data transfer source and the transfer destination when the first instruction is decoded, and the second instruction is decoded. At this time, if the inversion state identifier is to invert the data transfer source and the transfer destination, the inversion state identifier is returned to the state before the update assuming that the data transfer source and the transfer destination are not inverted after controlling the execution order of the instructions. Inversion state updating means, and instruction invalidation control means for invalidating the second instruction if the inversion state identifier does not invert the data transfer source and the transfer destination when the second instruction is decoded. Further comprising data processing apparatus according to claim 1.