JP2002544587A5 - - Google Patents

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Publication number
JP2002544587A5
JP2002544587A5 JP2000616500A JP2000616500A JP2002544587A5 JP 2002544587 A5 JP2002544587 A5 JP 2002544587A5 JP 2000616500 A JP2000616500 A JP 2000616500A JP 2000616500 A JP2000616500 A JP 2000616500A JP 2002544587 A5 JP2002544587 A5 JP 2002544587A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000616500A
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JP2002544587A (ja
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Application filed filed Critical
Priority claimed from PCT/US2000/013232 external-priority patent/WO2000068783A2/en
Publication of JP2002544587A publication Critical patent/JP2002544587A/ja
Publication of JP2002544587A5 publication Critical patent/JP2002544587A5/ja
Pending legal-status Critical Current

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JP2000616500A 1999-05-12 2000-05-12 デジタル信号プロセッサ計算コア Pending JP2002544587A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13376699P 1999-05-12 1999-05-12
US60/133,766 1999-05-12
PCT/US2000/013232 WO2000068783A2 (en) 1999-05-12 2000-05-12 Digital signal processor computation core

Publications (2)

Publication Number Publication Date
JP2002544587A JP2002544587A (ja) 2002-12-24
JP2002544587A5 true JP2002544587A5 (ja) 2007-07-05

Family

ID=22460216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000616500A Pending JP2002544587A (ja) 1999-05-12 2000-05-12 デジタル信号プロセッサ計算コア

Country Status (3)

Country Link
EP (4) EP2267597A3 (ja)
JP (1) JP2002544587A (ja)
WO (1) WO2000068783A2 (ja)

Families Citing this family (11)

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Publication number Priority date Publication date Assignee Title
WO2002010914A1 (en) * 2000-07-28 2002-02-07 Delvalley Limited A method of processing data
WO2003021426A2 (en) 2001-08-29 2003-03-13 Analog Devices Inc. Method and apparatus for timing and event processing in wireless systems
JP4502662B2 (ja) * 2004-02-20 2010-07-14 アルテラ コーポレイション 乗算器−累算器ブロックモード分割
US20090031104A1 (en) * 2005-02-07 2009-01-29 Martin Vorbach Low Latency Massive Parallel Data Processing Device
CN100559905C (zh) * 2005-07-20 2009-11-11 大唐移动通信设备有限公司 基带芯片
US7555514B2 (en) * 2006-02-13 2009-06-30 Atmel Corportation Packed add-subtract operation in a microprocessor
JP5481793B2 (ja) 2008-03-21 2014-04-23 富士通株式会社 演算処理装置および同装置の制御方法
CA2751388A1 (en) * 2011-09-01 2013-03-01 Secodix Corporation Method and system for mutli-mode instruction-level streaming
FR3021428B1 (fr) 2014-05-23 2017-10-13 Kalray Multiplication de matrices de bits utilisant des registres explicites
CN108334337B (zh) * 2018-01-30 2022-02-01 江苏华存电子科技有限公司 含自动管理功能的低延迟指令调度器及过滤猜测访问方法
CN113157636B (zh) * 2021-04-01 2023-07-18 西安邮电大学 协处理器、近数据处理装置和方法

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JPS61255433A (ja) * 1985-05-07 1986-11-13 Mitsubishi Electric Corp 演算装置
JPH077356B2 (ja) * 1989-05-19 1995-01-30 株式会社東芝 パイプライン方式のマイクロプロセッサ
US5175863A (en) * 1989-10-23 1992-12-29 International Business Machines Corporation Signal data processing system having independently, simultaneously operable alu and macu
US5926644A (en) * 1991-10-24 1999-07-20 Intel Corporation Instruction formats/instruction encoding
DE69327504T2 (de) * 1992-10-19 2000-08-10 Koninklijke Philips Electronics N.V., Eindhoven Datenprozessor mit Operationseinheiten, die gemeinsam Gruppen von Registerspeichern benutzen
JPH0876977A (ja) * 1994-09-06 1996-03-22 Matsushita Electric Ind Co Ltd 固定小数点演算装置
WO1996017293A1 (en) * 1994-12-01 1996-06-06 Intel Corporation A microprocessor having a multiply operation
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
TW424192B (en) * 1995-05-02 2001-03-01 Hitachi Ltd Microcomputer
CN100465874C (zh) * 1995-08-31 2009-03-04 英特尔公司 根据指令对数据执行运算的方法、处理器和系统
CN101794213B (zh) * 1995-08-31 2014-09-17 英特尔公司 控制移位分组数据的位校正的装置
WO1997009679A1 (en) * 1995-09-01 1997-03-13 Philips Electronics North America Corporation Method and apparatus for custom processor operations
US5710914A (en) * 1995-12-29 1998-01-20 Atmel Corporation Digital signal processing method and system implementing pipelined read and write operations
US5822606A (en) * 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5954811A (en) 1996-01-25 1999-09-21 Analog Devices, Inc. Digital signal processor architecture
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
GB2317466B (en) * 1996-09-23 2000-11-08 Advanced Risc Mach Ltd Data processing condition code flags
US6530014B2 (en) * 1997-09-08 2003-03-04 Agere Systems Inc. Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits
US6260137B1 (en) 1997-09-12 2001-07-10 Siemens Aktiengesellschaft Data processing unit with digital signal processing capabilities

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