JP2002533825A - Intelligent IC - Google Patents

Abstract

(57) [Summary] The present invention relates to an intelligent IC. The intelligent IC comprises a main processor 1 and an operating system for executing a main program P1 for configuring a main process for performing a task, and at least one sub-program for configuring at least one process for performing a task. At least one sub-processor 2 capable of simultaneously executing P2, a common power supply circuit 6 between the processors, and a power disturbance superimposed on the power disturbance of the main process in order to perform continuous or intermittent scrambling. Means for ensuring that one or more sub-processes with different operating signatures at the same power are performed simultaneously with the main process, while continuously or intermittently leading to the power supply circuit. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] A microprocessor, microcomputer or intelligent IC
It is known to sequentially execute the instructions of a program stored in a memory, internally or externally, in synchronization with one or more timing signals referencing a clock signal supplied to a microprocessor, microcomputer or intelligent IC. is there. By intelligent IC is meant an IC that contains a finite number of circuits specific to the execution of a limited number of instructions or functions specially developed for it.

It has been found that the various stages of the execution of such a program can be tracked over time. This is because the execution of instructions is performed sequentially according to a process predetermined by the program, generally in synchronization with a clock signal that periodically gives the processor a fixed timing. In fact, every program is represented by a sequence of instructions, which must be executed sequentially in a known order. Since the sequence of instructions is executed according to a predetermined process, the beginning and end of each instruction is completely known. The predetermined process has what is called a “signature” that can be recognized by advanced analysis means. It is known that the signature of this process is obtained, for example, from the measurement signals of the power consumption of the various electrical circuits used by the executed instruction or instruction sequence. Thus, since the running program is composed of such a series of predetermined instructions whose signatures are known, in principle, knowing the nature of the instruction sequence executed at a predetermined moment in the processing unit of the processor Is possible.

[0003] By such means, it is possible to determine the specific instruction to be executed and what data is used by this instruction.

[0004] The possibility of observing the details of the execution of a program on a microprocessor or microcomputer is a significant drawback when the microprocessor or microcomputer is used for high security applications. In fact, a malicious individual may thus know the continuous state of the processor and use this information to learn some important consequences of internal processing.

[0005] For example, a given operation may take place at different moments depending on the result of a given protected operation, such as part of the authentication of internal secret information, decryption of a message, or checking the integrity of some information. I can imagine what happens. Also, depending on the moment considered, for example, acting on the processor or obtaining the values of some registers by physical analysis, it is possible to carry out cryptographic calculations, even based on the secret encryption key used. Even when used, information about the result or content of the confidential information is available.

[0006] Devices are known that provide a first improvement to a protected microcomputer by providing a circuit for generating random clock pulses. This makes it particularly difficult to observe the event by analysis, because it is not possible to immediately synchronize the event, making it difficult to predict the occurrence of the event.

[0007] However, this type of solution has a number of disadvantages.

First, the design of such circuits is difficult and cumbersome, as random functions cannot be simulated over complex circuits as well as microcomputers. It is even more difficult to test the scrambled behavior of A series of random clock pulses is actually very difficult to simulate testing a circuit, but controlling the overall behavior of the entire logic circuit of a processor, especially during signal switching on internal buses and registers. But more difficult.

Another device is known that introduces a new architecture based on the use of a dummy memory, and the microprocessor uses or does not use the dummy memory so as not to be completely synchronized with the outside world. I do. In this way, observing events and signatures is particularly difficult.

However, the use of random clocks or dummy memories does not change the basic behavior of the microprocessor, even if they provide a useful improvement. Microprocessors are always sequential, even if the instructions sent one after another are part of different processes. Thus, it is only theoretically possible to "filter" the illegal instructions and store only the correct instructions, thereby utilizing the information sent from the microprocessor.

Another disadvantage is that the execution contents of the program interrupted by the dummy sequence must be backed up and returned to the original state, but the memory resources required for such backup cannot be ignored. .

It is an object of the present invention to provide intelligent ICs with means for inhibiting such types of analysis, and more generally to prevent any interpretation of signals sent from a processor or main processing unit. . This type of IC is called "MUMIC (
Multi Untraceable MICrocomputer).

The object is that the intelligent IC has at least a main processor and an operating system for executing a main program to configure a main process for performing a task, and at least one process for performing a task. At least one sub-processor capable of simultaneously executing one sub-program, a power supply circuit common to the processors, and a power disturbance superimposed on the power disturbance of the main process in order to perform continuous or intermittent scrambling. By means of ensuring that one or more sub-processes with different operating signatures at the same power, while continuously or intermittently leading to the power supply circuit, are performed simultaneously with the main process. .

According to another feature, the main processor or the sub-processor is a protected microprocessor or microcomputer, respectively.

According to another feature, these means comprise the main processor of the intelligent IC (
The additional security created by the operating system of 1) and formed by the above means depends only on the decisions resulting from execution by the main processor of the operating system located at the location of the IC which is not accessible from the outside. Has been.

According to another feature, a main memory dedicated to the main processor, at least partially including the operating system, inaccessible from the outside and accessible by at least one of the two processors; And

According to another feature, the apparatus has at least one communication bus between the processors, respective memories for the processors, and input / output circuits.

According to another feature, the intelligent IC is constructed using logic circuits distributed on one or more substrates, wherein the physical layout of the two processors is
Instead of using easily recognizable functional blocks, they are constituted by separate logical structures, for example, by physical interleaving.

According to another feature, the secondary processor performs a secondary process task that minimizes or disables the operational signature of the primary processor.

According to another feature, the secondary processor assigns a task of the secondary process correlated with the task of the primary process executed by the primary processor so that intermediate processing results never appear in the middle of the process. Execute.

According to another feature, the sub-program uses a smaller working space than the main program.

A second object of the present invention is to make the main process operable only when the sub process is operating.

This second object is achieved by the intelligent IC having communication means between the main processor and the sub-processor.

According to another feature, by means of communication between the two processors, the main processor comprises:
It is possible to know whether the sub processor is operating.

According to another feature, the means of communication between the two processes allows the primary processor to perform authentication of the secondary processor.

According to another feature, authentication or operational testing of the secondary processor is performed during processing by the primary processor.

According to another feature, the activation means of the secondary processor is controlled by the main processor and its main program, an interrupt system, a time counter or a combination of the three.

A third object of the present invention is that the sub-process executes a program completely different from the main program.

This third object is achieved by executing the task of the sub-process without being correlated with the task of the main process executed by the main processor.

According to another feature, the secondary processor performs the task of the secondary process that minimizes or disables the operational signature of the primary processor.

A fourth object of the present invention is that the signature of the program used by the sub-program is
It consists in inducing the opposite result to the result sent from the main processor.

The fourth object is that the sub-program implements a process that is correlated with the main process so that the combination of the two processes supplies the operation signature of the sub-processor that hides the operation signature of the main processor. Is achieved by

According to another feature, the secondary processor performs a task that is correlated with the task of the primary processor so that intermediate processing results never appear in the middle of the process.

A fifth object of the present invention is to realize an original architecture by using a circuit which has been validated without creating a new semiconductor technology or using a new manufacturing method.

The fifth object is achieved by the sub processor replacing the main processor, and conversely, the main processor replacing the sub processor.

According to another feature, the secondary processor performs tasks correlated with the tasks of the primary processor by synchronizing the processes and comparing two data values sent from each processor executing each program. I do.

According to another feature, the secondary processor performs tasks correlated with the tasks of the primary processor by logically deducing the secondary program from the primary program.

According to another feature, the intelligent IC comprises at least two processors, each processor (1, 2) being connected with RAM, ROM for each processor and non-volatile memory for the main processor. Each has a bus (3, 4).

According to another feature, the intelligent IC includes a plurality of processors, each processor connected to the same multiplexed communication bus between the processors, a RAM, a ROM, and a non-volatile memory array. Are connected to the multiplexed communication bus, and the contention of the common multiplexed communication bus is
It is managed by an iteration circuit.

According to another feature, the sub-processor sequentially executes the program executed by the main processor and the program correlated or uncorrelated with the program executed in any order.

Other features and advantages of the present invention will become more apparent from the following description, taken in conjunction with the accompanying drawings.

The intelligent IC targeted by the present invention is a MUMIC (Multi Un
A first modified embodiment of the logical configuration will be described with reference to FIG. This logical configuration does not indicate a physical configuration or a topology layout, as described below. This intelligent IC comprises a main processor (1) and a sub processor (
Each processor is connected to each memory (12, 13, 22) by each communication bus (address, data and command) (3, 4). These memories are respectively composed of a main program (P1) and a subprogram (P2) executed by a main processor (1) and a subprocessor (2) and work registers such as nonvolatile memory RAMs (11, 21). including. The memory connected to the secondary processor is a random access "dummy" memory (DumRAM).
21) and a read-only "dummy" memory (DumROM 22), allowing the sub-processor (2) to execute tasks that overlap the tasks of the main processor (1). The operation system of the main processor is, for example, a ROM (1
Although it is inaccessible from the outside in 2), it is included in a portion accessible from at least one of the two processors. Each processor (1, 2) has its own sequencer (19 or 20). The IC according to the invention also comprises an input / output circuit (14), which is connected to a single bus or, if the circuit is arranged to comprise a plurality of buses according to alternative embodiments, It is connected to the bus of the main processor and is connected to the outside world by a switch or, if there is no switch, by a connection device, and receives a signal from a terminal. Register group (R1,
R2, R3) and the interrupt circuit (15) can be added to a processor that requires it in order to implement one of the functional modifications corresponding to the modified embodiments described later. The three elements (R1, R2, R3) are connected to an interrupt generation circuit (15),
The interrupt generation circuit is connected to an interrupt input of the processor (in this case, the main processor).

The operation system of the main processor (1) is one in the case of the modified embodiment of the master main processor and the slave sub-processor, and is arranged in the ROM (12) accessible by the main processor. . If required in a variant embodiment in which the processor is role-swappable, a second operating system or the same operating system may be able to access the secondary processor, for example by exchanging an access right jeton. Check this access right before the processor moves. Similarly, especially in the case of role exchange, ie, FIG.
In an alternative embodiment of a, an interrupt circuit can be added to each processor that needs it for the role to be fulfilled.

The main program (P 1) is included in the non-volatile memory (13), and considering that the use of the dummy memory may be executed simultaneously between at least two processors of the intelligent IC, France Published Patent Application No. 276536
This corresponds to the one described in No. 1. In such a case, the two types of memory (dummy memory and other memory) are used during the same time, even though the buses are actually multiplexed.

The IC also includes an input / output interface connected to at least one bus of the IC, which interface may be of a parallel / parallel or parallel / serial type. In the modified embodiment, the working RAM (11) of the main processor (1) is replaced with the dummy RAM (DumRAM 21) of the sub-processor (2).
) And form the same double-port memory as shown in FIG. These double port memories (11-21) use the first address register pair (110, 210) to generate address signals (ADD0, ADD).
1) to allow access by the main processor (1) or the sub-processor (2). These double port RAMs (11-21) also use a first pair of data registers (111, 211) to allow data read access by the main processor (1) or the sub-processor (2). . The output of the read data register is an amplifier (113, 213) that sends a data signal (D0, D1).
Connected to. In addition, these double-port RAMs (11-21) also use a second pair of data registers (112, 212) and the main processor (1
) Or data write access by the sub-processor (2). The architecture of this type of double port memory is available from vendors such as Motorola or Texas Instruments. Synchronous or asynchronous double port memories allow read or write access to the area of the memory address via two separate paths. Such double-port memories are used, inter alia, to control the synchronization process between different systems. The use of double-ported memory to synchronize processes means that the processor can access the memory, synchronously or asynchronously, and share simultaneously available data via two independent paths (address and data). Based on facts.

Two processors (1, 2), buses (3, 4) and memory (11-21; 1)
2, 13, 22) are supplied by a common power supply circuit (6) so as to minimize the difference between the power utilization of one processor and the other. With the advancement of semiconductor technology, it is now possible in practice to place two processors with an area of only a few mm ² on the same chip, thus obtaining an economically promising solution, The additional cost of the processor is negligible, especially as compared to the area occupied by RAM and programmable non-volatile memory (NVM). It has been proposed to use a housing partitioning tool that allows the processor to be integrated into a single, uniquely designed block. Those skilled in the art typically
When two processors must be laid out on the same board with ROM, programmable non-volatile memory, various functions are combined, an optimal path is searched, and timing restrictions are adhered to. Therefore, a certain architecture and layout are adopted, but this layout is very close to that shown in FIG. 7, and the two processors (CPU1 and CPU2) are arranged close to each other, and the clock circuit ( H) is located near the processor. Peripheral circuits (14) that make up the inputs and outputs are also adjacent to the processor, which is termed logic "glue" G1 in technical terminology and is a set of logic elements required for the operation of the IC. It is. RAM (11-21), ROM (12-22)
The other elements constituting the programmable nonvolatile memory NVM (13) are arranged all around. A feature of the present invention is that logical operators, arithmetic operators, and control functions are connected to each other at the gate or basic cell level so that the physical location of cells belonging to a function can be determined a priori. It has to be mixed.
Thus, each processor is divided into several elements, shown in FIG. 6 as squares or rectangles. These elements may be included in other elements of a clock circuit represented by a circle, or in hexagonal elements of a logical "glue", or in trapezoidal elements of a peripheral circuit. In addition, as shown in FIG. 6, layout can be performed in a combination of these elements. The physical layout of the circuits of the two processors is advantageously constructed by using such an entirely trivial topology, with no easily recognizable physical functional blocks as in the general case. . Such a topology is used in "gate array" circuits, where each cell of the matrix can perform any function. In this way, the two processors (1, 2) are logically separated, to the extent that two adjacent transistors can belong to either the processor or the circuit to which they are coupled. Nevertheless, they are physically staggered. This is possible because the classification of the circuits involving the area of the card with the microprocessor does not require very high performance in terms of clock period. Therefore, such a circuit layout method is particularly preferable for ensuring the safety of the device. Of course, the realization of such circuits requires computer-aided automatic design to properly route signals and control functions. Therefore, the design is such that the consumption of each functional block is completely interleaved and combined.

Further, the two processors may be connected via a specific link or via a bus (3, 4)
The bus is shared between two processors by a set of communication registers (50, 51 in FIG. 2a) connected to the other processor or by a period stolen via the bus of another processor, or alternatively as shown in FIG. If so, communication is possible by the arbitration logic.

FIG. 2 a shows, for example, a link using two registers (50, 51) operating in interrupt mode by means of a detection circuit (B 1, B 2), but similar to the protocol used in chip cards. Double access register using protocol (5
) May be used. In this case, the main processor (1) is the master. FIG.
In the embodiment according to the first embodiment, the first register (50) is connected to the bus (3) of the main processor (1).
) And the bus (4) of the secondary processor (2), while the second register (51) provides the link in the opposite direction. The first register (50
) Or each of the second registers (51) is a first storage flip-flop (B1).
) Or second storage flip-flops (B2), which enter the active state when information is sent to the corresponding register. The output of the first flip-flop (B1) is connected to the interrupt system of the second processor (2), and the output of the second flip-flop (B2) is connected to the interrupt system of the main processor (1). . The size of the registers is sufficient to accommodate the requests and responses from each processor. FIG. 2b shows the structure of a frame with a header, a data area and an error detection area. Each frame can constitute an information block (block I) or an ACK block (block A), and these blocks are transmitted in both directions. The header can be composed of 2 bytes, the first byte indicates a block number, and the second byte indicates a length. When a block is sent to the first register (50), the flip-flop generates a signal which is interpreted by the second processor (2) as an interrupt signal IT1, and thus there is a message addressed to the first register (50). I can let you know. Therefore,
The second processor (2) obtains the data of the block by reading the contents of the first register (50), and then sends the data to the second register (51) addressed to the main processor (1) with the same number. Acknowledgment of the receipt of the block with the given ACK block (block A). This method is known, but not necessarily required within the scope of the invention, in particular to allow chaining of blocks. In each information block, the information area itself can be divided into two parts, a command area and a data area. Thus, the main processor can send instructions to the sub-processor by the command area. For example, this list includes, but is not limited to, commands such as read, write, data check, and authenticate. When receiving the command, the sub-processor (2) acknowledges the reception of this command by an ACK block (block A) sent to the second register (51), processes the command, and then processes the information block (block A response is issued to the second register (51) as I). The main processor (1) acknowledges receipt of this block by the ACK block sent to the first register (50), and so on. By numbering the blocks, data blocks that have not been successfully transmitted and received can be repeated. Of course, the protocol for exchanging information between the main processor and the sub-processor can be used in the reverse direction.

The two programs (P 1 and P 2) are executed by the main processor (1) and the sub processor (2), respectively, so that two instructions are executed simultaneously. Further, the clock phase for controlling the sub-processor (2) can be shifted so that the instruction cycle does not correspond exactly in each processor. Furthermore, the shift may be variable and random, which manifests itself as a superposition of similarly variable instruction cycles. These shifts are performed by the sequencer (20) of the secondary processor (2).
Can occur.

An advantageous and economical solution consists of using a very small “dummy” memory (DumRAM 21) for the “dummy” memory of the secondary processor (2). Indeed, since the dummy memory plays no real functional role, it can limit the space that can be addressed to this memory and minimize the space occupied by the chip. This space corresponds, for example, to simply adding one or more lines of RAM to a matrix of RAM. This space has its own address and data registers.

The secondary processor (2) may be kept running at all times, but it is preferable to arrange a communication channel between the two processors, and the communication channel is advantageously
It can be used to start the secondary processor (2) and / or to inform the primary processor (1) that the secondary processor (2) is performing a function and / or actually perform a task. The processor has at least two states, active and inactive. For example, the active state corresponds to the execution of a series of various operations, and the non-active state can be implemented by a standby loop that includes no operations. The transition from state to state is performed by a communication mechanism between the processors. For example, the main processor
By sending an interrupt signal to the inactive secondary processor, the secondary processor can be activated. In an alternative embodiment that implements the wake-up mechanism, each processor has an interrupt line or a reset line destined for at least one other processor. Indeed, although not the preferred method, another way to transition from the active state to the inactive state is to maintain an initialization (reset) signal destined for the processor to be deactivated, and It consists of deleting this. Thus, the activation means is a means by which one processor can cause another processor to transition from an active state to a non-active state and vice versa.

This can be done by an authentication mechanism between the two processors or by an activation register test mechanism. The authentication mechanism is activated at the request of the main processor (1), or periodically, or alternatively optionally. If the main processor (1) detects an anomaly during authentication, it can stop any processing or enter a waiting loop.

Therefore, this type of function can be used in the interrupt mode. For example, if an interrupt occurs due to an abnormality detected at the level of the main processor (1), a dialog is started between the two processors to perform authentication controlled by the main processor (1). This authentication is performed, for example, by encrypting data by the main processor (1) based on a key stored in a secret area of the programmable nonvolatile memory (13, NVM) connected to the bus (3) of the main processor (1). It consists of becoming. The encrypted data is sent to the secondary processor (2) via a communication channel,
The secondary processor decrypts the encryption and sends the result to the primary processor (1), and the primary processor compares the data with the decryption result. If the result is correct, the main processor (
1) continues to run, otherwise enters a wait loop to wait for the next authentication.
Such mechanisms are well known and do not pose a particular problem for those skilled in the art.

The primary processor (1) also has a “dummy” RAM (Dum) of the secondary processor (2).
It is also possible to test the activation register in the RAM 22) and to check whether this register has been properly changed in each test. If the registers have not changed,
As before, the main processor can suspend its activation.

In a variant embodiment, a copy of any part of the main program (P1) can be used as the subprogram (P2), by first specifying an address randomly and / or This is performed by operating on data different from the program data. Thus, a guarantee is obtained that the program will execute a reliable but functionally useless instruction.

Also, the sub-processor (2) can execute a program that is correlated with the program executed by the main processor so that an intermediate processing result never appears during execution. For example, two functions f1 and f2 different from the operation F are represented by F =
g (f1, f2) is selected so that the result of the operation F is obtained by a function g combining two different functions, and the two functions are respectively executed by the respective processors. Suppose you want to hide the result.

The code and / or data of the chip card are protected from errors and the chip card is attacked (differential fault an).
It has been proposed to set up "intolerants aux faults" programs in order to prevent enabling the implementation of AFA (Analysis, DFA). This error is particularly due to the instantaneous change of the power supply and / or the clock (power / clock glitch).
ch). In the example below (hypothetical communication program), an attacker will alter the behavior of a conditional connection (line 3) or decrement (line 6) to receive data beyond the normally scheduled storage area. (Answer_a
address + answer_length).

1 b = answer address 2 a = answer length 3 if (a == 0) goto 84 transmit (b ^* ) 5 b = b + 1 6 a = a−17 goto 38... These “failures” for chip cards (that is, failures can be detected) The program has, by definition, a redundancy task executed by the processor (CPU) of the microprocessor card.

A physical or logical counter that is decremented, as well as transfer-type atomic instructions (“swap”, “read-modify-
At some "synchronization" points formed by hardware or software "locks" (e.g., "write"), one or more main processes check whether the redundancy tasks for program execution match. I do.

If the processor checks as an indication of an attack, it is considered a mismatch.
These checks are much more complicated when hackers put errors in the card code. In the above example, the attacker would have to change the behavior of the two (or more) tasks in the same way, but this seems to be impossible (infeasible) in practice.

In fact, protection of the entire “critical” data of a program is required. For variables, this protection can be provided by copying to memory. Each processor (CPU) then has its own copy of the variable and saves it in a working memory rather than a dummy type. In a hypothetical example, the variable "
The decrement of "a" (loop counter) can be protected by the following instruction sequence executed by each processor.

6a = a-1 6 ′ Processor Synchronization 6 ″ if (a ′! = A) gotoattack where “a ′” is a copy of the variable “a” used by the second processor. , “A” is different from “a ′”, the program is “attack (attack)
) "And jumps to a processing routine that takes the necessary measures to protect the card.

For example, when an attack is detected, the process jumps to “attack” (label), and the “attack” processing routine performs initialization (Reset) of the microprocessor and / or erases a key in, for example, a programmable nonvolatile memory of an EEPROM type. Perform the required operation.

It should also be noted that the flow control, ie the control of the progress of the program, can be protected directly. In that case, the protected important data is the ordinal counter of the processor (or other information associated with the ordinal counter if the processor does not execute the same code). After each jump (conditional or unconditional) for which protection is desired, the redundancy task must compare the information in the direction in which each jump was taken. In the above hypothetical example, a conditional jump on line 3 can be protected by exchanging and comparing ordinal counters or corresponding information on lines 4,8.

The exchange and comparison operations can be performed by software means (similar to instruction sequence 6-6 ″ above) or occur as a result of a synchronization operation and send to the enable input (80). The comparator (8) shown in FIG.
) Can be implemented by hardware means. Comparator (8) also receives at its other input (81, 82) a signal indicating the value of each ordinal counter (PC, PC ') in each main processor (1) and sub-processor (2).

In the case of an attack, the hardware comparator (8) starts an interrupt process using a signal (attack interrupt) transmitted via its output (83), and the interrupt process turns off the interrupt mechanism of the microprocessor. Perform an appropriate operation via (eg, Reset interrupt).

Although these mechanisms may be similar to the conventional execution of a program in a system with two processors, the mechanisms of the present invention are very different in that:

^{* The} two processors are powered by the same circuit and are configured to mix the various instantaneous consumptions of the two processors and the combined circuit. The two processors can be located on the same silicon (silicon) substrate.

^* The signature of the instruction used on the secondary processor can hide the impact of the signature of the instruction executed on the primary processor.

[0070] ^* The purpose of the sub-program, in a different but perform the function to hide the functions of the main program is the main program. Thus, a task that has no correlation with the main program, or conversely, performs a task that has even contradictions, has a task parallel to the main program that is correlated with the main program for the purpose of hiding the main program. It can be considered to be implemented.

^* The size of the "dummy" RAM can often be much smaller than required for normal operation of the program.

[0072] ^* main processor, when the secondary processor is authenticated, and or to be operated only perform essential programs in the sense of safety.

^* The content of the “dummy” RAM has no functional significance,
The AM only plays a role in scrambling the trace of power consumption in the memory array.

^* It is not necessary to back up or restore the contents of the sub-program.

In another variant embodiment, the main processor (1) has a time counter (timer)
) (R3), and the time counter is initialized by using the random generator (R1) or from the contents of the programmable nonvolatile memory (13, NVM). The programmable non-volatile memory (13) may in fact contain a unique number that changes with each use. The time counter (R3) starts authentication of the sub-processor (2) by the main processor (1) when the time limit is reached after a lapse of time that cannot be predicted from the outside.

In another alternative embodiment, register (R2) can be used to initiate an interrupt after being loaded with certain information (eg, coming from memory or random generator (R1)). .

In another variant embodiment, the random generator (R1) comprises a main processor (1)
Of the main processor (1), which generates an irregular interrupt which is not synchronized at all with the execution of the program in the main processor (1). Of course, the interrupt system may or may not be masked depending on the processing considered. In this case, if the interrupt is masked,
The overall function remains the same for a single processor, but the current main program (P
If it is desired to protect 1) from being externally observed as necessary, this interrupt is permitted, and authentication and activation of the sub-processor (2) are started.

In another variant embodiment with a common bus shared between at least two, for example, n processors, each processor (FIGS. 31a, b,.
The three types of lines, the first bus request line (31), the second bus busy line (32), and the third bus polling line (33) of the common bus (3), provide the central arbitration logic (8). Connected. The first two types, request line (31) and busy line (32), each consist of a single line common to all processors, while the last type, polling line (33), Are the individual lines (33a, 33b,..., 33n) with n processors (1a, 1b,... 1n). The whole processor
RAM, ROM, programmable nonvolatile memory (NV) via a single bus (3)
M) and an input / output circuit (I / O).

A processor (eg, 1a) wishing to acquire bus (3) indicates on the bus request line (31) that it has this desire. The arbitration circuit (8), according to a predetermined algorithm (eg, periodic interrogation, bus polling), performs polling-type lines (33b,.
Inquire about other processors (1b,..., 1n) for 3n). The first processor making the request and being queried acquires the bus and activates the bus busy line (32). The arbitration circuit (8) restarts the inquiry only when the bus (3) is released by the transition of the signal transmitted to the bus busy line (32) from the active state to the inactive state. Thus, it can be seen that the processors are connected to the same bus and share this bus by multiplexing this access in time.

Of course, it is possible to combine the effects of the above embodiments, and it is not necessary to perform scrambling continuously.

Thus, if the main program (P1) performs non-critical operations, the scrambling performed according to the invention is intermittent, for example by intermittent return to the operation of a single processor. Sends the result to the outside world for test purposes, or masks the interrupt of the time counter (R3) or the random generator. When the protected operation is performed, the main program (P1) permits this operation to "scramble" the operation of the sub-processor (2).

In fact, the security is not obtained from the processors being randomly timed as in the prior art, but rather from two processors (1,.
2) is performed by simultaneously executing programs (P1, P2) having two different signatures.

The program executed by the main processor (1) is such that the operation of the main processor is
It can be configured to be controlled by a security operation system. The security operation system determines the type of scrambling to be performed according to the type of program executed by the machine. In this case, the operation system of the main processor (1) appropriately manages various command signals of the sub processor (2). It is clear that the sub-program (P2) can be used to execute functions useful for the main program (P1), including operations that can shorten the overall processing time. These processes are performed by, for example, a sub-program, but also include preparing a calculation to be used later by the main program (P1). Of course, if the processor operates in a multi-programming mode, it is easy to generalize the mechanism of the present invention, in which case the application program can be considered as the main program.

The above-described random generator and time counter do not pose any particular problem in implementation and, if used separately for other applications completely unrelated to the present invention, will be known to those skilled in the art. is there.

In another alternative embodiment, the invention can be configured such that two processors can alternately assume the role of primary and secondary processors. this is,
It is assumed that the priority tokens are exchanged between the two processors, giving the processor that owns the token of the two the role of master at a given moment.

Other modifications likewise form part of the inventive concept. Variations described with respect to embodiments limited to two processors are also applicable to embodiments with multiple processors, which also form part of the invention. Thus, in the detailed description of the invention, the expression read-only memory should always be understood as ROM, but it may mean PROM, EPROM, EEPROM or any other type of programmable nonvolatile read-only or random access. It can be replaced by a memory.

[Brief description of the drawings]

FIG. 1 is a logical block diagram illustrating an embodiment of an IC of the present invention having two processors, each with a bus.

FIG. 2a shows an embodiment of a communication circuit between two processors of an IC.

FIG. 2b is a diagram showing the structure of a frame used in communication between two processors of an IC.

FIG. 3 is a block diagram illustrating an embodiment of an IC of the present invention having two processors with a single bus.

FIG. 4 is a block diagram illustrating an embodiment of protection by synchronization and comparison of two values of a data element sent from each processor.

FIG. 5 is a diagram showing an embodiment of a double-port memory that can be accessed via each port by an IC processor.

FIG. 6 is a diagram schematically showing a physical layout of an IC element according to the present invention.

FIG. 7 is a diagram showing a conventional layout of a circuit element including two processors.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yugong, Michel France, F-78310-Morpa, Réuil de Separgille, 6F term (reference) 5B076 FC08 FD04 5B098 AA10 GA04 GC14

Claims (24)

[Claims] 1. A main processor (1) for executing a main program (P1) and an operation system for configuring a main process for performing a task, and at least one process for configuring at least one process for performing a task. 1
At least one sub-processor (
2), a power supply circuit common to the processors (6), and a power supply circuit for continuously or intermittently performing power disturbances superimposed on power disturbances of the main process in order to perform continuous or intermittent scrambling. Means for ensuring that one or more sub-processes with different operational signatures at the same power while performing the same process are performed simultaneously with the main process. 2. The intelligent IC according to claim 1, wherein the main processor (1) or the sub-processor (2) is a protected microprocessor or microcomputer, respectively. 3. The means are activated by the operating system of the main processor (1) of the intelligent IC and the additional security created by said means is located at the location of the intelligent IC which is not accessible from the outside. Operation system main processor (
2. The intelligent IC as claimed in claim 1, wherein it depends only on the decisions resulting from the execution according to 1). 4. A main memory (12, 13) dedicated to a main processor (1) which is inaccessible from the outside and is accessible by at least one of the two processors (1 and 2) and at least partially includes an operation system. The intelligent IC according to claim 1, further comprising: a secondary memory (21, 22) dedicated to a secondary processor (2). 5. At least one communication bus between said processors (1, 2).
3, 4), respective memories for the processors (1, 2), and input / output circuits (
14. The intelligent IC according to claim 1, comprising: 6. An intelligent IC configured using logic circuits distributed on one or a plurality of substrates, wherein the physical layout of two processors does not use easily recognizable function blocks. 2. The intelligent IC according to claim 1, wherein the intelligent IC is configured by a separate logical structure by physical interleaving. 7. The intelligent IC according to claim 1, wherein the sub-processor (2) executes a task of a sub-process that minimizes or invalidates an operation signature of the main processor (1). 8. The sub-processor (2) assigns a task of the sub-process correlated with the task of the main process executed by the main processor (1) so that an intermediate processing result never appears in the middle of the process. 2. The intelligent IC according to claim 1, wherein the IC is executed. 9. The intelligent IC according to claim 1, wherein the sub-program (P2) uses a work space smaller than a work space of the main program (P1). 10. The intelligent IC according to claim 1, further comprising communication means between the main processor (1) and the sub-processor (2). 11. Communication means between two processors (50, 51, B1, B2
2. The intelligent IC according to claim 1, wherein the main processor (1) can determine whether or not the sub processor (2) is operating. 12. Main processor (1) by means of communication between two processes.
2. The intelligent IC according to claim 1, wherein the device can perform authentication of the sub-processor. 13. The intelligent IC according to claim 1, wherein the authentication or operation check of the sub-processor (2) is performed during processing by the main processor (1). 14. The means for activating the sub-processor (2) is a main processor (1) and a main program (P1), an interrupt system (15), a time counter (R3).
2. The intelligent IC according to claim 1, wherein the intelligent IC is controlled by a combination of the three. 15. The intelligent IC according to claim 1, wherein the sub-processor (2) executes a task of the sub-process which is not correlated with a task of the main process executed by the main processor (1). . 16. The intelligent IC according to claim 1, wherein the sub-processor (2) performs a task of a sub-process that minimizes or invalidates an operation signature of the main processor (1). 17. The sub-program (P2) is uncorrelated with the main process such that the combination of the two processes supplies the operation signature of the sub-processor (2) which hides the operation signature of the main processor (1). The intelligent IC according to claim 1, wherein the intelligent IC performs a process. 18. The sub-processor (2) executes tasks correlated with tasks of the main processor (1) such that intermediate processing results never appear in the middle of the process. 2. The intelligent IC according to 1. 19. The method according to claim 1, wherein the sub-processor (2) replaces the main processor (1), and conversely, the main processor (1) replaces the sub-processor (2). Intelligent IC. 20. A task correlated with a task of a main processor (1) by a sub-processor (2) by synchronizing processes and comparing two data values sent from each processor executing each program. The intelligent IC according to claim 1, wherein: 21. The sub-processor (2) executes a task correlated with the task of the main processor (1) by logically deducing the sub-program (P2) from the main program (P1). The intelligent IC according to claim 1, wherein: 22. An intelligent IC including at least two processors
Wherein each of the processors (1, 2) has a bus (3, 4) to which a RAM, a ROM for each processor, and a non-volatile memory for the main processor are connected. 4. The intelligent IC according to 1. 23. An intelligent IC including a plurality of processors, wherein each processor is connected to the same multiplexed communication bus between the processors, and wherein the RAM, ROM, and nonvolatile memory array are connected to the multiplexed communication bus. 2. An intelligent IC as claimed in claim 1, wherein the contention for access to the common multiplexed communication bus is managed by an arbitration circuit (8) connected to the multiplexed communication bus. . 24. The sub-processor (2) sequentially executes a program executed by the main processor (1) and one of a correlated program and a non-correlated program, regardless of the order. The intelligent IC according to claim 1, wherein: