JP2002528784A - Electronic component and method for shielding instruction execution or data processing - Google Patents

Abstract

(57) [Summary] The present invention relates to an electronic component (CI) including a microprocessor (1) for executing a main program and storage means (2, 3). The random number (R) counter (4) generates a count end signal (ITO) at its output to suspend execution of the main program during execution of the subprogram. The present invention can be applied to a chip card.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to electronic components and methods for shielding instruction execution or data processing.

[0002] The invention relates more specifically to electronic components used in applications where access to services or data is tightly controlled. Such components have an architecture formed around a microprocessor and memory. The component uses an algorithm that uses secret data that is included in the component and that cannot be accessed from the outside. The confidential data then helps validate electronic transactions such as purchases, and the data is not accessed from outside the component at any time.

However, by observing some external parameters, such as data exchanged with external systems or power consumption of the power terminals of the components, information about the components may be obtained using statistical processing in some cases. Can be found. In particular, by observing the information flowing over the data bus, typically the serial bus, over time, a correlation can be obtained between this information and the progress of the algorithms used in the components.

[0004] Furthermore, such information can be correlated by observing power consumption according to time. In that case, it is possible to deduce the bit value processed in the instruction. Because, at a given moment, the power consumption of an individual instruction is determined by the bit value "
This is because it varies depending on “0” or “1”.

It is an object of the present invention to block instruction execution or data processing within a component in order to invalidate the observation of external parameters of the electronic component.

According to the present invention, execution of a main program executed by an electronic component is interrupted at random, and a subprogram is executed. In this way, the progress of the program changes constantly. Statistical processing is no longer possible when viewed from the outside, since all the curves obtained are randomly shifted in time. Taking the observation of exchange data as an example, the response time of the card to any external command changes constantly so that it is no longer possible to deduce any suitable information therefrom.

[0007] With respect to the observation of power consumption, this power consumption as a function of time is itself cut off and diffused against the normal consumption curve, so that no suitable information can be obtained therefrom.

Accordingly, the present invention relates to an electronic component comprising at least one microprocessor for executing a main program and storage means, as characterized.

According to the present invention, the component further includes a random number counter that generates information at an output, and suspends execution of the subprogram during execution of the subprogram.

In the first embodiment of the present invention, the subprogram execution time is constant.
In another embodiment of the invention, the execution time is variable. Furthermore, it can be random.

In one refinement, this subprogram activates the power consuming means, thereby disrupting the power consumption curves of the components, and more effectively shielding the operations performed and the data being processed.

The present invention further relates to a method of blocking instruction execution or data processing in an electronic component.

[0013] Other features and advantages of the present invention will become apparent in the following explicit and non-limiting description, taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram of an electronic component according to the invention. FIG. 2 is a block diagram variant of an electronic component according to a variant of the invention.

FIG. 1 is a simplified block diagram of an electronic component CI according to the present invention. The components have a microprocessor 1 and internal resources connected to a data bus 6.
The internal resources include, in particular, a memory, in this embodiment a program memory 2, a working memory 3, a counter 4, and a random number R generator 5.

The electronic component CI has various external connection terminals. In an embodiment, it is a data serial input / output component and thus has data input / output I / O terminals. Further, the components include a ground terminal VSS, a power supply terminal VCC, and a terminal related to a control signal (not shown).

The microprocessor receives instructions and data at a serial input / output port 8, which is connected to an input / output terminal for data relating to an external system.

The microprocessor internally generates various control signals to control various internal resources.

Among these control signals, the decision signal EN of the counter 4 and the counter initialization signal L
OAD and the start signal SEL of the random number generator 5 are shown.

When determined (EN activation), the counter generates a count end signal ITO. This count end information signal is used as a microprocessor interrupt signal. Thus, it is connected to the input of the interrupt port 7 of the microprocessor. Here, the expression “count end” is a general expression meaning that the counter has finished decrementing from the predetermined value to zero, similarly to the fact that the counter has finished counting to the predetermined value.

Note that in the illustrated embodiment, the counter is a physical resource.

The microprocessor 1 executes a main program included in a program memory for data or an instruction received from a serial input / output port 8 connected to an external system.

According to the invention, the execution of the main program is suspended at random times only during the execution of the sub-programs contained in the program memory.

For this purpose, a counter initialization routine using a new random number is provided at the beginning of the main program. In practice, this routine invalidates the counter (does not activate EN), extracts the random number R in the random number generator 5, loads the random number into the counter (LOAD), and subsequently activates the counter (LOAD). EN activation) instruction.

When the counter is decremented to zero, it activates an end-of-count information signal ITO, which causes an interrupt to the microprocessor. Execution of the main program is suspended during execution of the subprogram (by the microprocessor) corresponding to the target interrupt control routine.

The subprogram comprises at least the already seen sequence of counter initialization with a new random number, so that a new interrupt takes place.

This subprogram can correspond to a certain number of instructions, in which case
It is executed in a fixed time. For example, if the subprogram has a new random number R in generator 5
, And includes only instructions corresponding to the loading (initialization) of the counter 4 in the new disturbance R, the subprogram can be executed in a fixed time.

In this case, in addition to the execution of the main program, there is a termination code (corresponding to a subprogram) that is executed for a fixed time at a random time.

In a variant of the invention, the execution time of the subprogram is variable.

In the first embodiment, the subprogram includes a test for binary data, and the test is changed every time the program is executed, and the number of instructions executed next depends on the test result. Furthermore, the variable execution time can be made dependent on the mathematical function. For example, if the mathematical function requires several cycles of calculation to reach the result, the number of cycles will be a function of the input data, resulting in a variable execution time depending on the mathematical function. Techniques for obtaining these variable times are all well known.

In another embodiment, the variable execution time is random. In this embodiment, the subprogram deactivates the counter, extracts a new random number, decrements
This involves decrementing this value to zero in a loop and then initializing the counter with a new random number.

In this modification, a termination code that is executed at random time and at random time is introduced into the execution of the main program.

In practice, many variations of the invention are possible.

In particular, in order not to significantly reduce the execution time of the main program, the total delay time due to execution of one or a plurality of subprograms can be temporally limited.

According to another embodiment of the present invention, not only can the execution of the main program be suspended at random times, but also additional power consumption can be provided that obscure the power consumption due to the execution of the main program. .

This additional power consumption may be momentarily due to instructions provided in the subprogram. For example, within this subprogram, calculations of several cycles of an algorithm, for example an encryption algorithm, can be performed.

This execution corresponds to the instantaneous power consumption, that is, the instruction execution time, and is inserted into the regular power consumption corresponding to the execution time of the main program to obscure the regular consumption of the main program.

This additional power consumption can also have a lasting effect for a certain period of time. At this time, the subprogram activates the power consuming unit, and the power consuming unit consumes power for at least a certain time between execution of the next instruction of the subprogram and the main program.

A block diagram of an electronic component corresponding to this second embodiment of the present invention is shown in FIG.

In addition to the descriptive elements with the same reference numbers in FIG. 1, the electronic component has a charge pump 9.

The charge pump supplies a high voltage VPP for programming and / or erasing from a power supply voltage VCC and can program and / or erase data in an electrically programmable / erasable nonvolatile memory. A typical example of the memory is an EPROM, an EEPROM, or even a flash EPROM. In the present invention, this charge pump is combined with a program memory.

In an embodiment, the pump is activated by a write signal WE of the program memory.

As a known property, such pumps consume a large amount of power between the time of establishing the high voltage output and the time of programming or erasing, which can be on the order of milliseconds. Activating such a pump imposes a large power consumption, for example by providing a programming instruction in the sub-program, and shields the consumption of the next instruction of the sub-program and the main program.

The present invention is not limited to the above embodiments or variations. The invention encompasses the use of any means for suspending the main program at random times of the time which can be constant, variable or random, with or without the use of means for adding additional power consumption. It doesn't matter.

Such blocking or jamming with any of the variants of the invention, or a combination thereof, makes any statistical processing impossible.

In practice, the choice of a particular subprogram depends on the application of the electronic component.

The invention applies to all components having at least one counter and a random number generator. For a given electronic component, the choice of a particular subprogram depends on the resources of the component of interest, the efficiency with the application of interest.

In addition, the use of various subprograms is also possible, which allows a mixture of types to improve radio interference, in which case the selection of the subprogram to be executed is made at the beginning of the interrupt routine. .

Such a component can be used particularly for a chip card, and can improve the inviolability of the card.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] October 19, 2000 (2000.10.19)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B017 AA03 BB00 CA13 5B076 FD04

Claims (15)

[Claims] An electronic component comprising at least one microprocessor (1) for executing a main program and storage means (2, 3), wherein the electronic component further executes a subprogram by the microprocessor. And a random number (R) counter (4) for generating a count end information signal (ITO) at the output for suspending the execution of the main program. 2. The electronic component according to claim 1, wherein the subprogram execution time is constant. 3. The electronic component according to claim 1, wherein the subprogram execution time is variable. 4. The subprogram execution time is random.
An electronic component according to claim 3. 5. The electronic component according to claim 1, further comprising a power consuming unit activated by a subprogram. 6. Electronic component according to claim 5, characterized in that these power consuming means comprise a charge pump (9). 7. Electronic component according to claim 5, characterized in that these means comprise instructions which cause a momentary consumption. 8. An electronic component (CI) comprising at least one microprocessor (1) for executing a main program and storage means (2, 3),
A method of blocking arithmetic execution or data processing, which comprises using a random number (R) generator (5) and a counter (4), at random times, during main program execution only during subprogram execution. A method comprising suspending execution of a program. 9. A subprogram invalidates a counter (4) and outputs a new random number (4).
Method according to claim 8, characterized in that R) is extracted, the counter (4) is initialized with this new random number, decrementing is allowed and then execution returns to the main program. 10. The method of claim 8, wherein the subprogram can execute at random times. 11. The subprogram invalidates the counter (4), extracts a new random number (R), decrements this new random number in the loop of the subprogram until it becomes zero, followed by a new random number (R). The method according to claim 10, comprising extracting the counter value, initializing the counter with the new random number, starting the counter and returning to the execution of the main program. 12. The method according to claim 8, wherein the sub-program further activates the power consuming means. 13. The method according to claim 12, wherein said power consuming means comprises a charge pump (9). 14. The method according to claim 12, wherein these means include instructions for causing instantaneous power consumption. 15. The apparatus according to claim 8, wherein said apparatus has various subprograms.
15. The method according to any one of claims 1 to 14.