AU6207799A - Electronic component for masking execution of instructions or data manipulation - Google Patents

Electronic component for masking execution of instructions or data manipulation

Info

Publication number
AU6207799A
AU6207799A AU62077/99A AU6207799A AU6207799A AU 6207799 A AU6207799 A AU 6207799A AU 62077/99 A AU62077/99 A AU 62077/99A AU 6207799 A AU6207799 A AU 6207799A AU 6207799 A AU6207799 A AU 6207799A
Authority
AU
Australia
Prior art keywords
instructions
electronic component
data manipulation
masking execution
masking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU62077/99A
Inventor
Philippe Anguita
David Naccache
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus SCA
Gemplus Card International SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus SCA, Gemplus Card International SA filed Critical Gemplus SCA
Publication of AU6207799A publication Critical patent/AU6207799A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2123—Dummy operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microcomputers (AREA)
  • Storage Device Security (AREA)
AU62077/99A 1998-10-16 1999-10-15 Electronic component for masking execution of instructions or data manipulation Abandoned AU6207799A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9812988A FR2784763B1 (en) 1998-10-16 1998-10-16 ELECTRONIC COMPONENT AND METHOD FOR MASKING THE EXECUTION OF INSTRUCTIONS OR THE HANDLING OF DATA
FR9812988 1998-10-16
PCT/FR1999/002521 WO2000023866A1 (en) 1998-10-16 1999-10-15 Electronic component for masking execution of instructions or data manipulation

Publications (1)

Publication Number Publication Date
AU6207799A true AU6207799A (en) 2000-05-08

Family

ID=9531646

Family Applications (1)

Application Number Title Priority Date Filing Date
AU62077/99A Abandoned AU6207799A (en) 1998-10-16 1999-10-15 Electronic component for masking execution of instructions or data manipulation

Country Status (6)

Country Link
EP (1) EP1121629A1 (en)
JP (1) JP2002528784A (en)
CN (1) CN1332860A (en)
AU (1) AU6207799A (en)
FR (1) FR2784763B1 (en)
WO (1) WO2000023866A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118042A (en) * 1999-10-19 2001-04-27 Hitachi Ltd Card monitoring method
FR2818766A1 (en) * 2000-12-21 2002-06-28 Bull Cp8 METHOD FOR SECURING THE EXECUTION OF AN IMPLANTED PROGRAM IN AN ELECTRONIC MODULE WITH MICROPROCESSOR, AS WELL AS THE ELECTRONIC MODULE AND THE MICROCIRCUIT CARD THEREOF
JP4173297B2 (en) * 2001-09-13 2008-10-29 株式会社ルネサステクノロジ Memory card
EP1293856A1 (en) * 2001-09-18 2003-03-19 EM Microelectronic-Marin SA Secure integrated circuit having confidential parts and a method for activating the circuit
GB0221240D0 (en) * 2002-09-13 2002-10-23 Koninkl Philips Electronics Nv Current source for cryptographic processor
EP1651969A4 (en) * 2003-07-17 2007-03-07 Atmel Corp Method and apparatus for smoothing current consumption in an integrated circuit
FR2857804B1 (en) 2003-07-17 2006-05-26 Atmel Corp METHOD AND APPARATUS FOR SMOOTHING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT
FR2924262B1 (en) * 2007-11-26 2009-12-11 Sagem Securite METHOD OF MASKING A PASSAGE AT THE END OF LIFE OF AN ELECTRONIC DEVICE AND DEVICE COMPRISING A CORRESPONDING CONTROL MODULE
US20100264982A1 (en) 2007-12-13 2010-10-21 Nxp B.V. Electronic circuit and method of masking current requirements of an electronic circuit
FR2973150B1 (en) * 2011-03-21 2013-04-26 Morpho METHOD OF MASKING A PASSAGE AT THE END OF LIFE OF AN ELECTRONIC DEVICE AND DEVICE COMPRISING A CORRESPONDING CONTROL MODULE

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2638869B1 (en) * 1988-11-10 1990-12-21 Sgs Thomson Microelectronics SECURITY DEVICE AGAINST UNAUTHORIZED DETECTION OF PROTECTED DATA
CA2037857C (en) * 1990-03-20 2001-01-16 Roy Allen Griffin, Iii Prevention of determination of time of execution of predetermined data processing routine in relation to occurrence of prior observable external event
FR2745924B1 (en) * 1996-03-07 1998-12-11 Bull Cp8 IMPROVED INTEGRATED CIRCUIT AND METHOD FOR USING SUCH AN INTEGRATED CIRCUIT

Also Published As

Publication number Publication date
JP2002528784A (en) 2002-09-03
FR2784763B1 (en) 2001-10-19
FR2784763A1 (en) 2000-04-21
EP1121629A1 (en) 2001-08-08
WO2000023866A1 (en) 2000-04-27
CN1332860A (en) 2002-01-23

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase