JP2002374166A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a frequency variable range by suppressing deterioration in phase noise characteristics. SOLUTION: A voltage controlled oscillator section(VCO) 1 outputs an oscillation output signal S1, having a fixed frequency f1=2N(f2+Δfm) (N being an integer of 2 or larger). A selector 6 selects either a frequency-divided output signal, having a frequency division ratio 1/2N of a frequency division section 2 or a frequency-divided output signal having a frequency division ratio 1/N of a frequency dividing section 5. A mixer 7 mixes the signal S1 with a frequency-divided output signal S2. A BPF 8 makes a signal having the frequency difference between the mixed two signals to pass. A doubling multiplication section 9 doubles an output signal S3 from the BPF 8. The VCO 10 oscillates at a prescribed frequency, which lies within the range of ±Δfm, with the center at the frequency f2. A mixer 12 mixes a doubled output signal S4 with an oscillation output signal S5 from the VCO 10. A BPF 13 makes signal components, having a frequency within a range of ±2Δfm with center at (4N-3)(f2+Δfm), to pass through as an output signal S6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a point synthesizer using microwaves or quasi-millimeter waves.
to-Point, Point-to-Multipo
The present invention relates to a frequency synthesizer applied to an int communication device.

[0002]

2. Description of the Related Art Point by microwave or quasi-millimeter wave
-To-Point, Point-to-Multip
In the point communication device, a local oscillation signal is generated by a frequency synthesizer. This frequency synthesizer uses a voltage controlled oscillator (VCO) using a dielectric, a variable capacitance diode, or the like. Its characteristics include:
It is required to cover a wide frequency range and have low phase noise.

Generally, in a voltage controlled oscillator (VCO) using a dielectric or a variable capacitance diode, the phase noise characteristic becomes worse as the variable range of the frequency becomes wider. For this reason, conventionally, a plurality of oscillation circuits of a fixed frequency are provided to switch according to the frequency used, or the oscillation frequency is adjusted individually for each device.

[0004]

However, when a plurality of oscillating circuits are provided, the circuit scale becomes large, and when individually adjusting the oscillating frequency for each device, it is very troublesome. ing.

An object of the present invention is to provide a simple circuit configuration.
An object of the present invention is to provide a frequency synthesizer capable of expanding a frequency variable range while suppressing deterioration of phase noise characteristics.

[0006]

According to the present invention, there is provided a frequency synthesizer comprising: a first phase-locked loop for generating a first oscillation output signal fixed at a frequency f1; Frequency dividing means for dividing the frequency to 1 / N (N is an integer of 2 or more) and dividing ratio 1 / 2N, and outputting one of them; the first oscillation output signal and the frequency dividing output of the frequency dividing means A first mixer for mixing the signal, a first band-pass filter provided on the output side of the first mixer, a multiplying means for doubling an output signal of the first band-pass filter, and a frequency f2 A second phase-locked loop for generating a second oscillation output signal controlled to one frequency within a predetermined range of ± Δfm, and mixing the output signal of the multiplying means with the second oscillation output signal And a second mixer provided on the output side of the second mixer. A second band-pass filter for extracting an output signal, and a control unit for controlling the first phase-locked loop, the second phase-locked loop, and the frequency dividing unit, respectively.

The frequency dividing means divides the first oscillation output signal by a frequency dividing ratio of 1 / N (N is an integer of 2 or more); Divide the output signal by 1 /
A second frequency divider that divides the frequency by 2N; and a frequency division output signal of the first frequency divider and a frequency division output signal of the second frequency divider in response to a selection signal from the control unit. And a selector for selecting and outputting one of them.

Further, the frequency dividing means converts the first oscillation output signal into a frequency dividing ratio of 1 in response to a selection signal from the control means.
/ N (N is an integer of 2 or more) or a frequency dividing ratio of 1 / 2N.

In the above configuration, the control means sets the frequency f1 of the first oscillation output signal to f1 = 2N (f2 +
Δfm) and the frequency of the output signal of the second band-pass filter is (4N−3) (f2 + Δfm)
The frequency dividing means is controlled by determining whether the frequency is higher or lower. Further, the first band-pass filter includes f1- (f
1 / N) to f1- (f1 / 2N). Further, the second band pass filter has a 2f
From 1 (1- (1 / N)) + (f2-Δfm) to 2f1
Signal components up to (1- (1 / 2N))-(f2- [Delta] fm) are passed.

The first phase-locked loop includes a voltage-controlled oscillator oscillating at the frequency f1, a reference oscillator oscillating a reference frequency signal, a frequency-divided output signal of the first frequency divider, P for controlling the voltage controlled oscillator based on the reference frequency signal and a control signal from the control means
An LL unit, a voltage controlled oscillator oscillating at the frequency f1, a reference oscillator oscillating a reference frequency signal, a frequency-divided output signal of the second frequency divider, and It may be constituted by a PLL section for controlling the voltage controlled oscillation section based on a reference frequency signal and a control signal from the control means, and further, a voltage controlled oscillation section oscillated at the frequency f1, and a reference frequency signal. A reference oscillation unit that oscillates and a PLL unit that controls the voltage control oscillation unit based on the frequency divided output signal of the variable frequency divider, the reference frequency signal, and a control signal from the control unit may be used.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Here, a first voltage controlled oscillator (VCO)
1, a first frequency dividing unit 2, a first PLL unit 3, and a reference oscillating unit 4 constitute a first phase locked loop. In addition, a second voltage controlled oscillator (VCO) 10 and a second PCO
The LL unit 11 and the reference oscillation unit 4 form a second phase locked loop.

The first voltage controlled oscillator (VCO) 1 and the second voltage controlled oscillator (VCO) 10 include a voltage controlled oscillator (VC) using a dielectric or a variable capacitance diode.
O). The reference oscillating unit 4 includes an oscillating circuit that generates a high-precision reference frequency signal Ss having a constant frequency using quartz.

Each of the PLL units 3 and 11 is composed of an integrated circuit including a variable frequency dividing circuit, a phase comparing circuit, and the like. Then, the control signals C1,
A phase comparison is performed between the oscillation output signal that has been frequency-divided according to C2 and the reference frequency signal, and a control voltage is generated so that the phase difference becomes 0, so that the first and second voltage controlled oscillators (VC
O) Control 1 and 10 respectively.

The first voltage controlled oscillator (VCO) 1 is controlled to oscillate at a fixed frequency f1. Also, the second
The voltage-controlled oscillation unit (VCO) 10 has a predetermined frequency within a range of ± Δfm around the frequency f2, that is, f
It is controlled to oscillate at 2 + Δf (−Δfm ≦ Δf ≦ + Δfm). The oscillation frequency is controlled by the control unit 14.
The control is performed based on control signals C1 and C2 supplied to the PLL units 3 and 11, respectively.

Incidentally, the first voltage controlled oscillator (VC
O) On the output side of 1, a first frequency divider 2 having a frequency division ratio of 1 / 2N (N is an integer of 2 or more) and a frequency division ratio of 1 / N (N is an integer of 2 or more) are provided. The second frequency divider 5 and the first mixer 7 that mixes the oscillation output signal S1 and the frequency-divided output signal S2 of the first voltage controlled oscillator (VCO) 1 to generate a frequency difference signal are provided. Is provided.

A selector 6 is provided on the output side of each of the frequency dividers 2 and 5. The selector 6 includes a controller 14
Of the frequency-divided output signal (frequency: f1 / 2N) of the first frequency divider 2 and the frequency-divided output signal (frequency: f1 / N) of the second frequency divider 5 according to the selection signal C3 from One of them is selected and supplied to the first mixer 7 as a divided output signal S2.

Here, the divided output signal of the first divider 2 is distributed to the first PLL 3, but the divided output signal of the second divider 5 is divided into the first divided signal. The signal may be distributed to the PLL unit 3 to form a first phase locked loop.

The first mixer 7 has an oscillation output signal S1 (frequency: f1) of the first voltage controlled oscillator (VCO) 1;
The frequency-divided output signal S2 selected by the selector 6 is mixed.

A band-pass filter (BPF) 8 provided on the output side of the first mixer 7 has a frequency f1- (f1 / N) to f1- (f1 / 2) of the output signal of the mixer 7.
The signal components up to N) are designed to pass as a signal S3.

The multiplier 9 is a band pass filter (BPF)
The signal S3 that has passed through No. 8 is doubled, and the frequency is 2f1 (1
− (1 / N)) to 2f1 (1− (1 / 2N)).

The second mixer 12 mixes the output signal S4 of the frequency multiplier 9 with the oscillation output signal S5 of the second voltage controlled oscillator (VCO) 10 (frequency: f2 + Δf).

The band-pass filter (BPF) 13 provided on the output side of the second mixer 12 has a frequency of 2f1 (1
− (1 / N)) + (f2-Δfm) to 2f1 (1-
(1 / 2N))-(f2-Δfm) is designed to be passed as an output signal S6 (frequency: f3).

In the present invention, the oscillation output frequency f1 of the first voltage controlled oscillator (VCO) 1 is set to f1 = 2N
Control is performed at a fixed frequency of (f2 + △ fm).

Next, the operation will be described with reference to FIG.

As described above, the frequency of the second voltage controlled oscillator (VCO) 10 is f2 + Δf (−Δfm ≦ Δ
f ≦ + Δfm), and the frequency f1 /
When the 2N frequency-divided output signal is selected, the frequency f3 of the output signal S6 is: f3 = 2f1 (1- (1 / 2N))-(f2 + [Delta] f) ...
... (1).

When the frequency-divided output signal having the frequency f1 / N is selected by the selector 6, the frequency f3 of the output signal S6 is f3 = 2f1 (1- (1 / N)) + (f2 + .DELTA.f).
... (2).

The maximum frequency f3max of the output signal S6 is
As shown in FIG. 2, this is when Δf = −Δfm in equation (1). That is, f3max = 2f1 (1- (1 / 2N))-(f2-Δ
fm)... (3).

The lowest frequency f3mi of the output signal S6
n is when Δf = −Δfm in the equation (2).
That is, f3min = 2f1 (1- (1 / N)) + (f2-Δf
m)... (4).

Further, when Δf = + Δfm in the equation (1), it is the lowest frequency when the frequency-divided output signal of the frequency f1 / 2N is selected by the selector 6, and in equation (2), Δf = + Δfm Is the highest frequency when the selector 6 selects the frequency-divided output signal of the frequency f1 / N.

Here, when Δf = + Δfm, if the equations (1) and (2) are made to have the same frequency, that is, the selector 6 selects the frequency-divided output signal of the frequency f1 / 2N. If the lowest frequency in the case and the highest frequency when the frequency-divided output signal of frequency f1 / N is selected by the selector 6 are set to be the same frequency, when the frequency-divided output signal is switched by the selector 6, The frequency can be set continuously.

That is, the frequency f3 of the output signal S6 ranges from the lowest frequency f3min to the lowest frequency f3max, that is, 2f1 (1- (1 / N)) + (f2-Δfm).
To 2f1 (1- (1 / 2N))-(f2-.DELTA.fm).

In this case, 2f1 (1- (1 / 2N))-(f2 + .DELTA.fm) = 2f
Since 1 (1− (1 / N)) + (f2 + Δfm), f1 = 2N (f2 + △ fm) (5) holds.

By substituting equation (5) into equations (3) and (4), f3max = (4N-3) (f2 + @ fm) + 2 @ fm (6) f3min = (4N-3) (F2 + △ fm) -2 △ fm (7)

That is, the frequency of the output signal S6 is (4
N-3) (f2 + △ fm) can be set continuously within a range of ± 2 △ fm. Therefore, the band pass filter (BPF) 13 is (4N−3) (f2 + Δf
Any characteristic may be used as long as it allows the light to pass through a range of ± 2 △ fm around m).

Therefore, the controller 14 sets the oscillation frequency f1 of the first voltage controlled oscillator (VCO) 1 to 2N (f2 + Δf
m), and determines whether the frequency f3 of the output signal S6 is higher or lower than (4N−3) (f2 + △ fm), and determines whether the frequency division ratio is f1 / 2N or f1 / N. The selector 6 selects one of the frequency-divided output signals, and sets the oscillation frequency of the second voltage-controlled oscillation unit (VCO) 10 to f
An output signal whose frequency can be continuously set within a range of ± 2 △ fm around (4N−3) (f2 + △ fm) by controlling to one frequency within a range of ± Δfm centered at 2. S6 can be obtained.

As described above, the first voltage controlled oscillator (VC
O) The oscillation frequency f1 of 1 is fixed at 2N (f2 + △ fm), and the frequency variable range of the output signal is twice as large as the frequency variable range ± Δfm of the second voltage controlled oscillator (VCO) 10. Since it can be set to 2 △ fm, deterioration of the phase noise characteristic can be suppressed and the frequency variable range can be widened.

Next, as a simple concrete example, the frequency division ratio of the first and second frequency dividers 2 and 5 is set to 1/8 and 1/4, that is, N = 4, and the second voltage controlled oscillator (VCO) 10
The oscillation output frequency of the center frequency f2 = 0.9 GHz,
Set frequency range ± △ fm = ± 0.1 GHz (0.8 GHz
z to 1 GHz), the frequency f1 of the first voltage controlled oscillator (VCO) 1 = 2N (f2 +
Δfm) = 8 × (0.9 + 0.1) = 8 GHz.

The oscillation output signal S1 (f1 = 8 GHz) of the first voltage controlled oscillator (VCO) 1 and the quarter frequency output signal (f1 / N = 2 GHz) selected by the selector 6
Alternatively, the 1/8 frequency-divided output signal (f1 / 2N = 1 GHz) is mixed by the mixer 7. A bandpass filter (BPF) 8 provided on the output side of the mixer 7 extracts signal components of 6 GHz and 7 GHz having a frequency difference between the two signals.

After that, the frequency is multiplied by 2 by the frequency multiplying section 9 to obtain 12
Signal S4 of 14 GHz or 14 GHz, and the oscillation output signal (0.8 to 1) of the second voltage controlled oscillator (VCO) 10
GHz) and the mixer 7. The pass band of the band-pass filter (BPF) 13 provided on the output side of the mixer 7 is ± 2 △ around (4N−3) (f2 + {fm).
fm, ie ± 0.2 GHz around 13 GHz
(12.8 to 13.2 GHz).

Here, the 1/4 frequency-divided output signal (f1 / N =
When 2 GHz) is selected, the doubled output signal (12 GHz)
Hz) is input to the mixer 7, and the signal component (12.8 to 13 GHz) of the frequency sum of the two signals is input to the band-pass filter (BP).
F) 13 and is output as an output signal S6.

Further, the 1/8 frequency-divided output signal (f1 / 2N =
When 1 GHz is selected, the doubled output signal (14 GHz) is selected.
Hz) is input to the mixer 7, and a signal component (13 to 13.2 GHz) having a frequency difference between the two signals is converted to a band-pass filter (BP).
F) 13 and is output as an output signal S6.

Therefore, the frequency of the output signal S6 is 12.8.
１３13 GHz, the 1/4 frequency-divided output signal (f
1 / N = 2 GHz) is selected by the selector 6, and the oscillation output frequency of the second voltage controlled oscillator (VCO) 10 is set to 0.
What is necessary is just to set to one frequency in the range of 8 GHz to 1 GHz. Further, the frequency of the output signal S6 is 13 to 13.2G.
Hz, the 1/8 frequency-divided output signal (f1 / 2N
= 1 GHz) by the selector 6, and the oscillation output frequency of the second voltage controlled oscillator (VCO) 10 is set to 0.8 GHz.
The frequency may be set within a range from z to 1 GHz.

As described above, the second voltage controlled oscillator (VC
O) Oscillation output frequency of 10 from 0.8 GHz to 1 GHz
By setting the frequency of the output signal to 1
It can be set in the range of 2.8 to 13.2 GHz, and a variable range twice as large as that of the second voltage controlled oscillator (VCO) 10 can be obtained.

FIG. 3 is a block diagram showing another embodiment.

Here, the same components as those shown in FIG. 1 are denoted by the same reference numerals. The difference is shown in FIG.
Is that a variable frequency dividing section 15 is provided instead of the frequency dividing sections 2 and 5 and the selector 6 shown in FIG.

Here, the first voltage controlled oscillator (VC
O) 1, the variable frequency dividing unit 15, the first PLL unit 3, and the reference oscillating unit 4 constitute a first phase locked loop.

The variable frequency dividing unit 15 changes the frequency dividing ratio to 1 / 2N or 1 / N according to the control signal C4 supplied from the control unit 14.
The frequency is switched to N, and the oscillation output signal S1 (frequency: f1) of the first voltage controlled oscillator (VCO) 1 is frequency-divided and output as a frequency-divided output signal S2.

The control unit 14 switches the frequency division ratio of the variable frequency division unit 15 to 1 / 2N or 1 / N by the selection signal C4, and controls the frequency division circuit of the first PLL unit 3 by the control signal C1. By controlling the frequency division ratio, the first voltage controlled oscillator (V
The oscillation frequency f1 of (CO) 1 is given by f1 = 2N (f2 + Δf
m) is controlled to a fixed frequency.

Even with such a configuration, operation can be performed in the same manner as the embodiment shown in FIG.

[0052]

As described above, according to the present invention, the oscillation output frequency f1 of the first voltage controlled oscillator (VCO) is fixed at 2N (f2 + @ fm), and the frequency of the output signal is (4N- 3) Depending on whether it is higher or lower than (f2 + △ fm), one of the frequency-divided output signals f1 / 2N and f1 / N is selected, and a signal having a frequency difference between the two signals is generated by the first mixer. , And ± 2 around the center frequency f2.
By mixing the oscillation output signal of the second voltage controlled oscillator controlled to one frequency within the range of Δfm with the second mixer, the frequency is ± 2 around (4N−3) (f2 + △ fm). An output signal that can be set continuously within the range of Δfm can be obtained. Therefore, it is possible to increase the frequency variable range while suppressing the deterioration of the phase noise characteristic.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a frequency arrangement of an output signal.

FIG. 3 is a block diagram showing another embodiment of the present invention.

[Description of Signs] 1 First voltage controlled oscillator (VCO) 2 First frequency divider 3 First PLL unit 4 Reference oscillator 5 Second frequency divider 6 Selector 7 First mixer 8 Band pass Filter (BPF) 9 Multiplier 10 Second voltage controlled oscillator (VCO) 11 Second PLL 12 Second mixer 13 Bandpass filter (BPF) 14 Controller 15 Variable frequency divider

Claims (9)

[Claims] 1. A first phase-locked loop for generating a first oscillation output signal fixed at a frequency f1, and dividing the first oscillation output signal by a frequency division ratio of 1 / N (N is an integer of 2 or more). Frequency dividing means for dividing the frequency into a frequency dividing ratio of 1 / 2N and outputting one of them; a first mixer for mixing the first oscillation output signal and the frequency divided output signal of the frequency dividing means; A first band-pass filter provided on the output side of the first mixer; a multiplying means for doubling an output signal of the first band-pass filter; A second oscillator for generating a second oscillation output signal controlled at a frequency;
Phase-locked loop, a second mixer for mixing the output signal of the multiplying means and the second oscillation output signal, and a second mixer provided on the output side of the second mixer for extracting the output signal. A frequency synthesizer comprising: a band-pass filter; and control means for controlling the first phase locked loop, the second phase locked loop, and the frequency dividing means. 2. A first frequency dividing means for dividing the first oscillation output signal by a dividing ratio of 1 / N (N is an integer of 2 or more).
And a dividing ratio of 1 / 2N
A second frequency dividing unit for dividing the frequency of the first frequency dividing unit and a frequency dividing output signal of the first frequency dividing unit and a frequency dividing output signal of the second frequency dividing unit according to a selection signal from the control unit. A selector for selecting and outputting one of the two signals.
The described frequency synthesizer. 3. The frequency dividing means divides the first oscillation output signal into a frequency dividing ratio of 1 / N in response to a selection signal from the control means.
2. A variable frequency divider for dividing (N is an integer of 2 or more) or dividing by a dividing ratio 1 / 2N and outputting the divided frequency.
The described frequency synthesizer. 4. The control means controls the frequency f1 of the first oscillation output signal to f1 = 2N (f2 + △ fm), and adjusts the frequency of the output signal of the second bandpass filter to (4N- 3. The frequency synthesizer according to claim 1, wherein the frequency divider is controlled by determining whether the frequency is higher or lower than (f2 + △ fm). 5. The method according to claim 1, wherein said first band-pass filter is f1-
5. The frequency synthesizer according to claim 1, wherein signal components from (f1 / N) to f1- (f1 / 2N) are passed. 6. The filter according to claim 2, wherein the second band-pass filter is 2f1.
(1− (1 / N)) + (f2−Δfm) to 2f1 (1
6. The frequency synthesizer according to claim 1, wherein signal components up to-(1 / 2N))-(f2-.DELTA.fm) are passed. 7. The first phase-locked loop includes a voltage controlled oscillator oscillating at the frequency f1, a reference oscillator oscillating a reference frequency signal, a frequency-divided output signal of the first frequency divider, PLL for controlling the voltage controlled oscillator based on the reference frequency signal and a control signal from the control means
The frequency synthesizer according to claim 2, further comprising a unit. 8. The first phase-locked loop includes a voltage controlled oscillator oscillating at the frequency f1, a reference oscillator oscillating a reference frequency signal, a frequency-divided output signal of the second frequency divider, PLL for controlling the voltage controlled oscillator based on the reference frequency signal and a control signal from the control means
The frequency synthesizer according to claim 2, further comprising a unit. 9. The first phase-locked loop includes a voltage-controlled oscillator oscillating at the frequency f1, a reference oscillator oscillating a reference frequency signal, a frequency-divided output signal of the variable frequency divider, and a reference signal. 4. The frequency synthesizer according to claim 3, further comprising: a PLL unit that controls the voltage control oscillation unit based on a frequency signal and a control signal from the control unit.