JP2002374154A - High-speed current switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed current switching circuit wherein the startup time of its output current is made short without increasing its current consumption, and the overshoot of its output current is suppressed. SOLUTION: By subjecting MOS transistors Q3, Q4 to ON/OFF operations, a switching circuit 12 makes the current set by a current setting circuit 11 flow selectively through first and second current paths 17, 18. A current mirror circuit 13 derives from a MOS transistor Q7 the current being in a predetermined ratio to the set current flowing through the first current path 17, and includes a feedback circuit comprising MOS transistors Q6, Q10. An output- current optimizing circuit 14 so adjusts the phase margin of the feedback circuit included in the current mirror circuit 13 as to optimize the build-up of the output current outputted from the current mirror circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed current switch circuit for switching a transistor to switch a current flowing through the transistor at a high speed. Further, the present invention relates to CD-R, CD-RW, M
In a device for reading and writing data on a recording medium such as O, DVD-R, DVD-RAM, DVD + RW, etc., it is used for a laser diode drive circuit for driving a laser diode (LD).

[0002]

2. Description of the Related Art This type of laser diode driving circuit requires a current switch circuit which starts up a large current for driving a laser diode at a high speed and has a small overshoot of the current at the start. ing. Next, a conventional high-speed current switch circuit will be described with reference to FIG.

As shown in FIG. 7, this current switch circuit includes MOS transistors Q1 to Q11, an inverter 3,
And constant current sources 4, 5, and the like. next,
The operation of the current switch circuit will be described. Now, when the input signal IN input to the input terminal 1 goes to "H" level, the gates of the MOS transistors Q4, Q8, Q9 go to "H" level, and the input signal is inverted by the inverter 3 and The gate of transistor Q3 is at "L" level.

As a result, MOS transistor Q4 is turned on, so that the gate potential of MOS transistor Q10 and its source potential (potentials of nodes N3 and N5) become
It falls according to the current value of the external setting current IIN input from the current setting terminal 2. Here, the MOS transistors Q6 and Q10 form a feedback circuit. Node N3
When the potential of the source falls, the MOS consisting of the source follower
The source potential of the transistor Q11 (node N6
Of the MOS transistor Q)
7 gate voltage. Due to this gate potential, a current flows through MOS transistor Q7, and this current is output current IO
It is output from the output terminal 6 as a UT.

[0005] The MOS transistor Q10 and the MOS transistor Q11 are designed so that the voltage between the gate and the source is the same. Therefore, the value of the output current IOUT of the MOS transistor Q7 is W / L of the MOS transistor Q6 (where W is the channel width of the MOS transistor and L is its channel length).
And W / L of MOS transistor Q7. Therefore, the MOS transistor Q6 and the MOS
The transistor Q7 has a current mirror relationship.

On the other hand, an input signal I input to the input terminal 1
When N goes to the "L" level, the MOS transistor Q4,
Each of the gates of Q8 and Q9 becomes "L" level,
The input signal is inverted by inverter 3 and the gate of MOS transistor Q3 attains "H" level. As a result,
MOS transistor Q4 is turned off, and MOS transistors Q8 and Q9 are turned on. Therefore, the power supply voltage VDD is applied to each gate of the MOS transistors Q10, Q11, Q7, and the output current IOUT of the MOS transistor Q7 is turned off.

At this time, since MOS transistor Q3 is turned on, MOS transistors Q3 and Q5 have:
External setting current IIN set from current setting terminal 2 flows, and the source potential of MOS transistor Q3 (node N1
Is kept constant. This is MOS
This is to prevent the response when the transistor Q4 is turned on, that is, the response when the output current IOUT of the MOS transistor Q7 rises, from being delayed.

In the current switch circuit shown in FIG.
The response characteristic of the output current IOUT of the transistor Q7 is M
It is determined by the band characteristic of the feedback circuit (loop) including the OS transistors Q6 and Q10 and the band characteristic of the source follower including the MOS transistor Q11.
FIG. 8 shows an example of the frequency-gain characteristics and the frequency-phase characteristics of the feedback circuit and the MOS transistor Q11.
It becomes as shown in.

In this circuit, the primary pole of the feedback circuit including MOS transistors Q6 and Q10 is connected to node N3.
, And the secondary pole relates to the node N5. And
The positional relationship between the feedback circuit and the two poles ensures the stability (phase margin) of the feedback circuit. Next, the relationship between the phase margin of the feedback circuit and the corresponding rise characteristic of the output current of the MOS transistor Q7 is as shown in FIG. 9, for example.

FIG. 9A shows a case where the gain characteristics are the same and the phase margin is sufficient, and the output current of MOS transistor Q7 rises without overshoot. FIG.
(B) is a case where the gain characteristics are the same and there is almost no phase margin. The output current of the MOS transistor Q7 has overshoot and violently rings. Next, another example of the conventional current switch circuit will be described with reference to FIG.

This current switch circuit is basically the same as the current switch circuit of FIG. 7 as shown in FIG.
The difference is that the nodes N5 and N6 are directly connected (short-circuited). With such a configuration, the MOS
The response characteristic of the output current IOUT of the transistor Q7 has M
There is an advantage that the band characteristic of the source follower including the OS transistor Q11 is not related. This is MO
This is because the S transistor Q11 is the same transistor that exhibits the same behavior as the MOS transistor Q10.

[0012]

However, in the current switch circuit of FIG. 10, in addition to the MOS transistor Q10, M
A feedback circuit is configured by the OS transistor Q11.
Therefore, the load on the secondary pole of the feedback circuit increases. This is because the capacitance of the gate of the MOS transistor Q7 is increased.

As a result, in order for the feedback circuit to secure a sufficient phase margin, it is necessary to increase the transmission conductance gm of the MOS transistors Q10 and Q11. As a result, there is a disadvantage that current consumption increases. In addition,
Normally, a large current flows through MOS transistor Q7, so that the gate capacitance of MOS transistor Q7 also increases, and a large current needs to flow through MOS transistors Q10 and Q11.

In view of the above, an object of the present invention is to provide a high-speed current switch circuit capable of shortening the rise time of an output current and suppressing its overshoot without increasing current consumption. It is in.

[0015]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the inventions according to claims 1 to 6 are configured as follows. That is, according to the first aspect of the present invention, a current setting circuit for externally setting a current, and a current path of a set current set by the current setting circuit are connected to a first current path and a second current path according to an input signal. A switching circuit for switching to a current path, a current mirror circuit for extracting an output current having a predetermined current ratio with respect to a set current flowing in the first current path, and a current mirror circuit partially including a feedback circuit; An output current optimizing circuit for optimizing a rise of an output current of the current mirror circuit by adjusting a margin.

According to a second aspect of the present invention, a current setting circuit for externally setting a current, and a current path of a set current set by the current setting circuit are connected to a first current path and a second current path according to an input signal. A switching circuit including first and second transistors for selectively switching to two current paths, a third transistor connected in series to the first transistor, and a third transistor for driving the third transistor. One source follower, a fourth transistor that forms a current mirror relationship with the third transistor to extract a desired output current, and drives the fourth transistor under the same conditions as the first source follower. A second source follower, forming a feedback circuit between the third transistor and the first source follower;
And a current mirror circuit configured to drive the second source follower in accordance with the output of the third transistor;
An output current optimizing circuit for optimizing a rise of an output current of the current mirror circuit by adjusting a phase margin of the feedback circuit.

According to a third aspect of the present invention, in the high-speed current switch circuit according to the second aspect, the output current optimizing circuit includes an output side of the first source follower and the second side.
And a variable resistor element which is connected between the output side of the source follower and which can switch between low resistance and high resistance, and compares the output current with a predetermined value when the output current of the fourth transistor rises. Comparing means for switching the variable resistance element from low resistance to high resistance when the output current exceeds a predetermined value; and changing the variable resistance element from high resistance to low when the output current of the fourth transistor falls. And initialization means for switching to a resistor.

According to a fourth aspect of the present invention, in the high-speed current switch circuit according to the third aspect, the variable resistance element comprises a MOS transistor. According to a fifth aspect of the present invention, in the high-speed current switch circuit according to the second aspect, the output current optimizing circuit includes an output side of the first source follower and an output side of the second source follower. A resistance element having a predetermined resistance value is connected therebetween.

According to a sixth aspect of the present invention, in the high-speed current switch circuit according to the fifth aspect, the resistance element is made of polysilicon. As described above, in the present invention, a current mirror circuit including a feedback circuit is provided in part, and an output current optimization circuit that adjusts the phase margin of the feedback circuit to optimize the rise of the output current of the current mirror circuit is provided. I did it.

Therefore, according to the present invention, the rise time of the output current can be shortened and the overshoot can be suppressed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall circuit diagram showing a configuration of a first embodiment of a high-speed current switch circuit of the present invention. As shown in FIG. 1, the high-speed current switch circuit according to the first embodiment includes a current setting circuit 11 that externally sets a current, and a current path through which a current set by the current setting circuit 1 flows. Current path 17 and second current path 1
8, a current mirror circuit 13 for extracting an output current having a predetermined current ratio with respect to a set current flowing through the first current path 17, and an output current optimization circuit 14.

The current setting circuit 11 comprises a current mirror circuit comprising an N-type MOS transistor Q1 and an N-type MOS transistor Q2. When an external setting current II1 is set in the MOS transistor Q1, the current setting circuit II
The same current as 1 flows through the MOS transistor Q2. The switching circuit 12 includes an N-type MOS transistor Q3, an N-type MOS transistor Q4, and the like, and transfers the set current of the current setting circuit 11 to the first current path 17
The MOS transistor Q4 is turned on when the current flows through the second current path 18, and the MOS transistor Q3 is turned on when the set current flows through the second current path 18.

The current mirror circuit 13 includes a first current path 1
7, a P-type MOS transistor Q6 and a P-type output MOS transistor Q7 form a current mirror relationship. Therefore, the source voltages of the P-type MOS transistors Q10 and Q11 forming the source followers are applied to the gates of the MOS transistors Q6 and Q7, respectively.
Q11 is designed so that the voltage between its gate and source is the same.

As described above, the current mirror circuit 13 includes the MOS
The transistor Q6 and the MOS transistor Q10 include a feedback circuit (loop circuit) and an output circuit including an output MOS transistor Q7 and a MOS transistor Q11. The output current optimization circuit 14 includes the current mirror circuit 13
Is adjusted to optimize the rise of the output current from the current mirror circuit 13 by adjusting the phase margin of the feedback circuit included in the current mirror circuit.

Next, a detailed configuration of the high-speed current switch circuit according to the first embodiment will be described with reference to FIG. The current setting terminal 2 is connected to the drain of the MOS transistor Q1, and the drain is connected to each gate of the MOS transistors Q1 and Q2. MO
The sources of the S transistors Q1 and Q2 are commonly connected,
The common connection is grounded.

The input terminal 1 is connected to a MOS transistor Q4,
It is connected to the gates of Q8 and Q9 and to the gate of MOS transistor Q3 via inverter 3. The sources of the MOS transistors Q3 and Q4 are commonly connected, and the common connection portion is the MOS transistor Q3.
2 drain. MOS transistor Q
The drain of the transistor 3 is connected to the drain of the MOS transistor Q5, and the drain is connected to the gate of the MOS transistor Q5. The power supply voltage VDD is supplied to the source of the MOS transistor Q5.

The drain of the MOS transistor Q4 is M
Drains of OS transistors Q6 and Q8 and MO
It is connected to each gate of S transistors Q10 and Q11. The gate of the MOS transistor Q6 is M
The source is connected to the source of the OS transistor Q10 and the input side of the output current optimization circuit 14. Also,
The source of the MOS transistor Q6 is supplied with the power supply voltage VDD.

The gate of the MOS transistor Q8 is MOS
The power supply voltage VDD is supplied to the source of the MOS transistor Q8, which is connected to the gate of the transistor Q9. The drain of the MOS transistor Q10 is grounded, and the power supply voltage VDD is supplied to the source of the MOS transistor Q10 via the constant current source 4.

The output of the inverter 3 and the set current IIN of the current setting terminal 2 are input to the output current optimizing circuit 14, respectively. The output terminal of the output current optimization circuit 14 is connected to the drain of the MOS transistor Q9, the source of the MOS transistor Q11, and the gate of the MOS transistor Q7.

The source of the MOS transistor Q9 is supplied with the power supply voltage VDD. The drain of the MOS transistor Q11 is grounded, and the source of the MOS transistor Q11 is connected to the power supply voltage VD via the constant current source 5.
D is supplied. The source of the MOS transistor Q7 is supplied with the power supply voltage VDD, and the drain is connected to the output terminal 6.

Next, a specific configuration of the output current optimization circuit 14 will be described with reference to FIG. As shown in FIG. 2, the output current optimization circuit 14 includes an N-type MOS transistor Q21 as a variable resistance element and a comparison circuit 2
2 and an initialization circuit 23.

The MOS transistor 21 is connected between the source of the MOS transistor Q10 and the source of the MOS transistor Q11. The MOS transistor 21 is turned off based on the output from the comparison circuit 22 to function as a high resistance. It is turned on based on the output and functions as a low resistance. The comparison circuit 22 includes MOS transistors Q22, Q22
23, and a current comparator comprising an inverter 24. When the output current of the output MOS transistor Q7 rises, the output current is compared with a predetermined value, and when the output current exceeds a predetermined value, the MOS transistor Q21 Is to turn off.

Here, the predetermined value when the comparison circuit 22 makes a comparison is, for example, a value that is about 90% of the final value of the output current of the MOS transistor Q7. Initialization circuit 23
Consists of a MOS transistor Q24, and turns on and initializes the MOS transistor Q21 as soon as possible when the output current of the MOS transistor Q7 falls.

More specifically, the MOS transistor Q
The gate of 22 is connected to the source of MOS transistor 11 and the gate of MOS transistor Q7.
The source of the MOS transistor Q22 is at the power supply voltage V
DD is supplied. The drain of the MOS transistor Q22 is connected to the drain of the MOS transistor Q23, the drain of the MOS transistor Q24, and the input side of the inverter 24. The MOS transistor Q23 determines a threshold value when the comparison circuit 22 compares the output current of the MOS transistor Q7. The MOS transistor Q22 has an input setting current IIN supplied to the gate and a source grounded.

The output side of the inverter 24 is connected to the gate of the MOS transistor Q21. Also, MOS
The transistor Q24 has its gate supplied with the output of the inverter 3 and its source grounded. Next, the operation of the first embodiment having such a configuration will be described with reference to the drawings.

Now, when the input signal IN is at the "L" level, the input signal IN is applied to the MOS transistor Q9, so that the MOS transistor Q9 is on and the power supply voltage VDD is applied to the node N6. ing. Therefore, the power supply voltage VDD is applied to the gate of the MOS transistor Q22 of the output current optimization circuit 14, and M
OS transistor Q22 is turned off.

Therefore, the input side of the inverter 24 is at "L" level, the output side is at "H" level, and the MOS transistor Q21 is on.
Nodes N5 and N6 are short-circuited by low-resistance MOS transistor Q21. in this way,
When the node N5 and the node N6 are short-circuited,
In the feedback circuit composed of the MOS transistors Q6 and Q10, the capacitive load forming the secondary pole (pole) increases, so that the secondary pole is set to a low frequency and the phase margin is, for example, 30 ° or less. Become smaller.

On the other hand, when the input signal IN changes from "L" level to "H" level and starts rising, the MOS transistor Q4 is turned on.
The gate potential of 10 and its source potential (potential of nodes N3 and N5) start to fall according to the current value of external setting current IIN input from current setting terminal 2.

When the potential of the node N3 starts to fall, the source potential (potential of the node N6) is determined by the MOS transistor Q11, and this potential becomes the gate voltage of the MOS transistor Q7. The output current of the MOS transistor Q7 starts rising due to the gate potential. The potential of the node N6 is determined by the output current optimization circuit 1
4, the output voltage corresponding to the output current of the MOS transistor Q7 starts to flow through the MOS transistor Q22. When the output current exceeds a preset threshold, in other words, when the drain voltage of MOS transistor Q22 exceeds the threshold voltage of inverter 24 corresponding to the threshold, this inverter 24 is at the “L” level.

As a result, MOS transistor Q21 is turned off, so that node N5 and node N6
It is opened by the high-resistance MOS transistor Q21. As described above, when the node N5 and the node N6 are opened, the MOS transistors Q6, Q1
In the feedback circuit consisting of 0, the capacitive load constituting the secondary pole is reduced by the gate capacitance of the MOS transistor Q7, so that the secondary pole is set to a high frequency,
The phase margin is sufficiently ensured, for example, 60 ° or more.

Thereafter, when the input signal IN changes from "H" level to "L" level and falls, the input signal I
N is inverted by the inverter 3 and the output current optimization circuit 14
Is applied to the gate of the MOS transistor Q24. As a result, the MOS transistor Q24 is turned on, and the input side of the inverter 24 is immediately set to the “L” level, so that the inverter 24 initializes the MOS transistor Q21 to the on state.

FIG. 3 shows a summary of the change in the output current of the MOS transistor Q7 due to the above operation, which will be described below. That is, M
When the output current of the OS transistor Q7 rises, the MOS transistor Q21 is turned on to short-circuit the node N5 and the node N6 until the output current reaches a predetermined intermediate current value (for example, about 90% of the final value of the output current). I did it. For this reason, the rising period of the output current is accelerated as shown by the curve A in FIG.

On the other hand, at time t1 when the output current rises to the intermediate current value and overshoot occurs,
A MOS transistor Q is connected between nodes N5 and N6.
21 is turned off and opened, that is, the phase margin of the feedback circuit including the MOS transistors Q6 and Q10 is sufficiently secured. Therefore, overshoot of the output current is suppressed as shown by the curve B in FIG.

In FIG. 3, a curve C shows an example of the output current when the MOS transistor Q21 is kept on, and a curve D shows an example of the output current when the MOS transistor Q21 is kept off. As described above, according to the first embodiment, the rise time of the output current can be shortened and the overshoot can be suppressed without increasing the current consumption.

Further, according to the first embodiment, when the output current falls, the output current is returned to the initial state. Therefore, even if the output current is repeatedly turned on / off at a high speed by an input signal, the output is not repeated. No difference in the rise characteristics of the current appears. Next, the configuration of a high-speed current switch circuit according to a second embodiment of the present invention will be described with reference to FIG.

The high-speed current switch circuit according to the second embodiment is obtained by replacing the output current optimization circuit 14 of the first embodiment with a resistance element 31 having a predetermined resistance as shown in FIG. . The resistance element 31 is made of polysilicon or the like. The configuration of the other parts of the second embodiment is the same as that of the part except for the output current optimization circuit 14 of the first embodiment shown in FIG. The description is omitted here.

The second embodiment replaces the output current optimization circuit 14 of the first embodiment with a resistance element 31 for the following reason. That is, as shown by a curve C in FIG.
When short-circuiting between node N5 and node N6,
The output current of the MOS transistor Q7 rises quickly but has a large overshoot. Conversely, as shown by the curve D in FIG. 3, when the node N5 and the node N6 are opened, the output current of the MOS transistor Q7 rises slowly but has a small overshoot.

However, the resistance element 31 having a predetermined resistance value
Is inserted (connected) between nodes N5 and N6, the phase margin of the feedback circuit including MOS transistors Q6 and Q10 is adjusted. As a result, the rise characteristic of the output current of the MOS transistor Q7 has an intermediate characteristic as shown by the curve A in FIG. 5, and the overshoot is suppressed within an allowable range and the rise is accelerated. Can be.

In FIG. 5, curves A, B, and C,
The corresponding relationship of the phase margin θ is as follows. That is, the curve A is a case where 60 °>θ> 30 °,
Curve B is for θ> 60 ° and curve C is for θ <30
°. For example, the second embodiment is described as a CD-R
When applied to a / RW-based laser diode drive circuit, an overshoot amount of output current of up to 5% is allowed. For this reason, by adjusting the phase margin by the resistance element 31, it is possible to design to make the rising time of the output current the shortest within the range where the overshoot is within 5%. In this case, the current consumption of the circuit is not increased or decreased.

Next, a specific method of adjusting the phase margin of the feedback circuit including the MOS transistors Q6 and Q10 will be described with reference to FIG. FIG. 6 is an equivalent circuit of the node N5 of the circuit of FIG. From this equivalent circuit, assuming that the voltage at the node N3 is VN3 and the voltage at the node N5 is VN4,
The transfer function of the equivalent circuit is as shown in the following equation (1).

[0051] VN5 / VN5 = (gm1 / C1 ) × { [S + (1 / (C2 × R)) ] / ^{[S 2 + S ((C2 ×} R × (gm1 + gds1) + C1 + C2) / (C1 × C2 × R) ) + ((Gm1 + gds1) / (C1 × C2 × R)) Ｒ (1) where gm1 is the transfer conductance of the MOS transistor Q10, C1 is the gate capacitance of the MOS transistor Q6, and R is the resistance of the resistance element 31. The resistance value, gds1, is the body effect transfer conductance.

Now, if gm1≫gds1, (1)
The equation becomes the following equation (2). VN5 / VN5 = (gm1 / C1 ) × { [S + (1 / (C2 × R)) ] / ^{[S 2 + S ((gm1 /} C1) + (C1 + C2) / (C1 × C2 × R)) + (gm1 / (C1 × C2 × R)]｝ (2) According to the equation (2), a second-order low-pass filter (LPF) having a zero point is obtained.

When the primary pole frequency ω ₀ and the zero-point frequency Z _ero are obtained from the equation (2), the following equations (3) and (4) are obtained. ω ₀ = √ (gm1 / (C1 × C2 × R)) (3) Z _ero = 1 / (C2 × R) (4) Here, at the primary pole frequency ω ₀ the phase is rotated 90 °, the phase is returned at zero frequency Z _ero. Therefore, 1 The order pole frequency omega ₀ and Zeros Z _ero, can be adjusted by the resistance R of the resistor element 31. Therefore, by adjusting the resistance value of the resistance element 31, the phase margin of the feedback circuit can be adjusted.

In the second embodiment, the circuit is shown in FIG.
It is configured as shown in FIG. In such a circuit configuration, even if the step response of the feedback circuit overshoots,
It is the node N6 that ultimately determines the response of the output current. Therefore, from the response of the feedback circuit, overshoot hardly appears at the node N6 due to the effect of the low-pass filter due to the resistance of the resistor 31 and the capacitance of the node N6.

As described above, according to the second embodiment, since the resistance element is provided, the phase margin can be adjusted without increasing the current consumption of the circuit. Therefore, the output current can have its rise time as fast as possible while suppressing overshoot as much as possible.

[0056]

As described above, according to the present invention, the rise time of the output current can be shortened and its overshoot can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an output current optimization circuit.

FIG. 3 is a diagram illustrating characteristics of an output current according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 5 is a diagram illustrating characteristics of an output current according to the second embodiment.

FIG. 6 is an equivalent circuit of a feedback circuit when the output current rises according to the second embodiment.

FIG. 7 is a circuit diagram showing a configuration of a conventional circuit.

FIG. 8 is a diagram illustrating an example of a gain characteristic and a phase characteristic of a feedback circuit included in the conventional circuit.

FIG. 9 is a diagram illustrating characteristics of an output current of the conventional circuit.

FIG. 10 is a circuit diagram showing another configuration example of the conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Current setting circuit 12 Switching circuit 13 Current mirror circuit 14 Output current optimization circuit 17 1st current path 18 2nd current path 22 Comparison circuit 23 Initialization circuit 31 Resistance element

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX02 AX25 AX55 AX66 BX16 CX27 DX22 DX55 EX01 EX07 EX11 EX21 EY21 EZ00 EZ03 EZ04 EZ08 FX12 FX17 FX35 GX01 GX06 5J091 AA01 AA43 AA51 CA22 CA65 FA04 HA17 HA26 HA39 KA00 KA04 KA05 KA09 KA17 KA42 MA02 MA11 MA21 SA00 TA06

Claims (6)

[Claims] 1. A current setting circuit for externally setting a current, and a current path of a set current set by the current setting circuit,
A switching circuit for switching between a first current path and a second current path in accordance with an input signal; extracting an output current having a predetermined current ratio with respect to a set current flowing through the first current path; A high-speed current switch circuit comprising: a current mirror circuit including a circuit; and an output current optimization circuit that adjusts a phase margin of the feedback circuit to optimize a rise of an output current of the current mirror circuit. . 2. A current setting circuit for externally setting a current, and a current path of a set current set by the current setting circuit,
A switching circuit including first and second transistors for selectively switching between a first current path and a second current path in accordance with an input signal; and a third circuit connected in series to the first transistor. A transistor, a first source follower for driving the third transistor, a fourth transistor for forming a current mirror relationship with the third transistor to extract a desired output current, and a fourth transistor A second source follower driven under the same conditions as the first source follower; a feedback circuit is formed between the third transistor and the first source follower; A current mirror circuit for driving the source follower according to the output of the third transistor; and adjusting the phase margin of the feedback circuit to adjust the current follower. Fast current switch circuit comprising: the output current optimization circuit for optimizing the rise of the output current of the mirror circuit. 3. The output current optimizing circuit is connected between an output side of the first source follower and an output side of the second source follower, and is capable of switching between low resistance and high resistance. A variable resistance element, and at the time of rising of the output current of the fourth transistor,
Comparing the output current with a predetermined value, and when the output current exceeds a predetermined value, comparing means for switching the variable resistance element from a low resistance to a high resistance; and when the output current of the fourth transistor falls,
3. The high-speed current switch circuit according to claim 2, comprising: initialization means for switching the variable resistance element from high resistance to low resistance. 4. The high-speed current switch circuit according to claim 3, wherein said variable resistance element comprises a MOS transistor. 5. The output current optimizing circuit connects a resistance element having a predetermined resistance value between an output side of the first source follower and an output side of the second source follower. 3. The high-speed current switch circuit according to claim 2, wherein: 6. The high-speed current switch circuit according to claim 5, wherein said resistance element is made of polysilicon.