JP2002373123A - Data reading circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reading circuit in a data bus to be used in a computer system or the like capable of quickening a reading time for reading the same data from a plurality of registers or the like, and for confirming the data by comparing the data with an expected value. SOLUTION: This data reading circuit for reading a plurality of data through a data bus is provided with a logical sum means for calculating the logical sum of those data when there is not any inversion signal, and for outputting the logical sum data to the data bus and a logical product means for calculating the logical product of those data by inverting the data when there is any inversion signal, and for outputting the logical product data to the data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a read circuit on a data bus used in a computer system, a semiconductor test apparatus, and the like. In particular, when there are a large number of storage means such as registers connected to a data bus of a computer system or a semiconductor test device which store the same data due to parallelization, simultaneous measurement, or the like, a large number of the storage means may be used. The present invention relates to a reading circuit for quickly confirming whether or not the data is the same as an expected value.

[0002]

2. Description of the Related Art The configuration and operation of an example of the prior art will be described with reference to FIG. As shown in FIG. 6, a conventional main circuit of a read circuit on a data bus used in a computer system or the like includes a read control unit 10.
, 2n, AND gates 31, 32,... 3n, and an OR gate 70.

[0005] The read control unit 10 is, for example, a computer, and reads data of a large number of storage means such as registers connected to the data bus 100 via the data bus 100 and a selection signal 1 to be read from the large number of storage means.
~ N.

The registers 21, 22,... 2n are a large number of storage means for storing data of various control signals.
Data is read via the data bus 100.

The AND gates 31, 32,...
The output of a large number of registers 21, 22,... 2n is received at one end, and the other end receives the selection signal from the read control unit 10 and outputs the selected data.

The OR gate 70 outputs to the data bus 100 the logical sum of the selection signal output by the AND gates 31, 32,...

Next, the problem of the read operation of the read circuit on the data bus to which many registers are connected will be described.

For example, in a semiconductor test apparatus or the like, a large number (for example, 64
) Registers store the same data. In that case, it is necessary to read out to the read control unit 10 whether the same data is correctly written in many registers, and to compare it with expected values by software to confirm.

In the conventional read circuit shown in FIG. 6, the data of the registers 21, 22,.
One of the selection signals 1 to n of 1, 32,. Therefore, the time required to read all data from n registers is n times as long as the time required to read data once. If the number of registers is large, much time is required.

[0010]

As described above, in a read circuit on a data bus used in a computer system, a semiconductor test apparatus, or the like, the same data is read from a large number of registers and compared with an expected value to confirm. Reading time is very long, so that there is a practical problem. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to read out the same data from a large number of registers and compare it with an expected value in a read circuit on a data bus used in a computer system or a semiconductor test device. Another object of the present invention is to provide a read circuit in which the read time is shortened in the case of performing the check.

[0011]

That is, a first aspect of the present invention to achieve the above object is to output a logical sum of a plurality of data in a data reading circuit for reading a plurality of data via a data bus. A data read circuit comprising: a logical sum means; and a logical product means for outputting a logical product of the plurality of data, wherein the read logical sum output and the logical product output are respectively compared with expected values. The main point is.

A second aspect of the present invention, which has been made to achieve the above object, is a data reading circuit for reading a plurality of data via a data bus.
If there is no inverted signal, a logical sum means for performing a logical sum and outputting to the data bus, and if there is an inverted signal, inverting the plural data and then taking a logical sum to convert the logical product data into the data bus ANDing means for outputting to the bus;
A data reading circuit, comprising:

A third aspect of the present invention, which has been made to achieve the above object, is a data reading circuit for reading a plurality of data having the same expected value via a data bus, wherein the plurality of data are inverted by a plurality of inversion signals. A plurality of EXOR gates, and an OR gate for performing an OR operation on the outputs of the plurality of EXOR gates and outputting the result to the data bus;
The gist of the present invention is a data reading circuit characterized by having the following.

According to a fourth aspect of the present invention, there is provided a data reading apparatus for reading, via a data bus, a plurality of data expected to store data having the same expected value in storage means. A plurality of EXOR gates for inverting the plurality of data with a plurality of inversion signals, an OR gate for ORing outputs of the plurality of EXOR gates, and an output of the OR gate; And an EXOR gate for inverting the inverted data again by a signal obtained by logically ORing the data and outputting the inverted data to the data bus, and reading out the logical sum and the logical product of the plurality of data. The gist is a circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
The configuration and operation will be described with reference to FIG. As shown in FIG. 1, a main circuit of a read circuit in a data bus used in a computer system or the like according to the present invention includes a read control unit 10, registers 21, 22,.
, AND gates 31, 32,... 3n and EXOR
4n, an OR gate 70,
It is composed of an EXOR gate 80 and an OR gate 81. Here, the same components as those in the related art have the same numbers in the components of the invention. Then, the read circuit of the present invention performs reading twice in the case of "0" without an inverted signal and in the case of "1" with an inverted signal.

The read control unit 10 is, for example, a computer. The read control unit 10 reads data of a large number of storage units such as registers connected to the data bus 100 via the data bus 100, and a selection signal to be read from the large number of storage units. Generate an inverted signal.

The registers 21, 22,... 2n are a large number of storage means for storing data of various control signals.
Data is read via the data bus 100.

The AND gates 31, 32,...
The output of a large number of registers 21, 22,... 2n is received at one end, and the other end receives the selection signal from the read control unit 10 and outputs the selected data.

The AND gates 31, 32,...
The output of the plurality of registers 21, 22,... 2n is received at one end, and the selection signal from the read control unit 10 is received at the other end, and the selected data is output.

EXOR gates 41, 42,... 4n
Receives the outputs of the AND gates 31, 32,... 3n at one end, receives the inverted signals 1 to n from the read control unit 10 at the other end, and outputs exclusive ORs. That is,
As shown in FIG. 4, the EXOR gate outputs a through (non-inverted) output signal c, which is an exclusive logical output of the input signal a and the inverted signal b, that matches the input signal a when the inverted signal is “0”. When the inverted signal is "1", the input signal a and the inverted output signal c are obtained.

The OR gate 70 has an EXOR gate 41,
, 4n, and outputs a logical sum in response to the through or inverted output.

The EXOR gates 80 and 81 are connected to the EXOR gates 41 and 42 by the inverted signals 1 to n.
... The output inverted by 4n is again inverted and data bus 1
Output to 00. However, since it is known in advance whether or not to read the inverted signal in the read control unit 10, when the inverted signal is read from the data bus, the inverted signal can be inverted by software. And the OR gate 81 are not required.

Next, the logical operation of the read circuit of the present invention in the case of "0" without an inverted signal and in the case of "1" with an inverted signal will be described. However, for the sake of simplicity, the case where the number of registers is three and the read data is three in FIG. 1 will be described. It is also assumed that the expected values of data 1 and data 2 to be read are the same, and the expected values of data 3 and data 1 are not the same.

In FIG. 1, when there are three data and the inverted signal 1-3 is not output (all "0"), EX
The OR gates 41, 42, and 43 can be displayed as equivalent gates 51, 52, and 53 that output through signals shown in FIG. In FIG. 1, when the number of data is three and the inverted signals 1 to 3 are not output (all “0”),
The output of the R gate 81 becomes "0" and the EXOR gate 8
0 can be displayed as the equivalent gate 82 which is output as a through signal shown in FIG.

For example, in FIG. 2A, to select data 1 and data 2 having the same expected value, a selection signal 1-
3 are “1”, “1”, and “0”, respectively, AND
The gates 31, 32, and 33 output "data 1", "data 2", and "0", respectively, and the equivalent gates 51 and 52 output through signals, respectively.
The logical sum of data 1 and data 2 is output, and the equivalent gate 82
Outputs through. Therefore, the read data of FIG. 2A is the same as the output of the logical sum means of the data 1 and the data 2 by the equivalent gate 91 as shown in FIG. 2B.

On the other hand, in FIG. 1, there are three data, in order to read out data 1 and data 2 having the same expected value, inverted signals 1 and 2 are output ("1") and inverted signal 3 is not output. ("0"), EXOR gates 41 and 42
Are equivalent gates 71 of the inverter shown in FIG.
72. In addition, EXOR gate 80 and O
The R gate 81 can be represented as an equivalent gate 83 of an inverter that inverts and outputs any one of the inverted signals. The OR gate 70 shown in FIG. 1 becomes the NAND gate 61 having a negative logic input shown in FIG. 3A according to De Morgan's theorem. Here, De Morgan's theorem is expressed by the following equation (1) if the inversion of a is displayed as “/ a”. a + b = / (/ a./b) (1)

For example, in FIG. 3A, to select data 1 and data 2 having the same expected value, a selection signal 1-
3 are “1”, “1”, and “0”, respectively, AND
The gates 31, 32, and 33 output "data 1", "data 2", and "0", respectively, and the equivalent gates 71 and 72 output inverted data, respectively, so that "inverted data 1", "inverted data 2", and "0" are output. And the output of the NAND gate 61 is the inverse of (the logical product of "data 1" and "data 2"), and the logical product of "data 1" and "data 2" is output by the equivalent gate 83. . Accordingly, as shown in FIG. 3B, the read data of FIG. 3A is the same as the output of the logical product of the data 1 and the data 2 by the equivalent gate 91.

As described above, even if there are storage units storing different data in a large number of storage units, only the storage unit storing the same data is selected by the selection signal, and the logical sum or the logical product is calculated. Data can be read.

Next, a specific example will be described as to whether the operation of reading the same data from a large number of registers and comparing it with an expected value in the read circuit of the present invention can be performed by two readings. In FIG. 1, n is 3, and the same data is stored in all of the registers 21, 22, and 23. The expected value data to be sequentially read out by giving "1" to all of the selection signals 1-3 is "1". , 0, 1,
0 ".

The first reading is performed by the reading control unit 10.
Then, the through reading is performed without outputting the inverted signal 1-3. As shown in FIG. 5A, if the fourth data of the data 3 is “1” with respect to the data of the fourth expected value “0”, the result of the through read is data 1,
"1" is read as a logical sum of 2, 3 and becomes NG unlike the expected value. Also, as shown in FIG. 5B, even if the third data of the data 3 is “0” with respect to the data of the third expected value “1”, the result of the through reading is the data. "1" is read out as the logical sum of 1, 2, and 3, which is the same as the expected value, and is OK. That is, in the read by the logical sum, if "0" is set in the bit of the expected value "0", the expected value "
It is possible to verify the reading of the bit of "0", and it is not possible to confirm whether the bit of the expected value "1" is the same as the expected value.

The second read is performed by the read control unit 10
Then, an inverted signal 1-3 is output to perform inverted reading. As shown in FIG. 5C, the third expected value “1”
If the third data of the data 3 is “0” for the data of “1”, the result of the inversion read is “NG”, which is different from the expected value by reading “0” as the logical product of the data 1, 2, and 3.
Further, as shown in FIG. 5D, the fourth expected value “
The fourth data of data 3 is “4” for data “0”.
1 ", the result of the inversion read is data 1, 2,
"0" is read as the logical product of 3 and becomes the same as the expected value, and the result is OK. In other words, in reading by AND, if the bit of the expected value "1" is "1", the bit of the expected value "1" can be verified, and if the bit of the expected value "0" is the same, the bit is the same as the expected value. I can not confirm whether it is.

Therefore, if the read operation is performed twice, that is, the read operation by the logical sum and the read operation by the logical product, it is possible to ensure that the read data having the same expected value is the same as the expected value.

According to the above method, the conventional read circuit requires the number of reads (n times) as many as the number of registers, but the read circuit of the present invention expects all the contents of a large number of registers by reading twice. It can be checked whether the value is the same as the value, and the reading time can be greatly reduced. Therefore, among storage means such as registers connected to a data bus of a computer system or a semiconductor test apparatus, there are a plurality of (particularly a large number of three or more) storing the same data due to parallelization or simultaneous measurement. If
It is possible to quickly confirm that the contents of the plurality of registers are all correct values.

In this embodiment, for the sake of simplicity, the first inversion circuit is connected to each register, one by one. However, the output of a large number of registers such as an LSI is shown. In the case of outputting after ORing, if an inverting circuit is connected to each register, the circuit scale becomes large. In this case, in order to save the circuit, a group of registers not including the register storing the same data is set as one block, and the first inversion circuit is connected after ORing data in the block. The same effect can be obtained with a circuit configuration that takes a logical sum between blocks.

[0035]

The present invention is embodied in the form described above and has the following effects. That is,
When there are a plurality of (especially a large number of three or more) storage means such as a register connected to a data bus of a computer system or a semiconductor test apparatus for reasons of parallelization or simultaneous measurement, for example. In addition, there is an effect that it is possible to quickly confirm whether or not the contents of the plurality of registers are all the same as the expected values.

[Brief description of the drawings]

FIG. 1 is a data read circuit of the present invention.

FIG. 2 is a logic circuit without an inverted signal of the data read circuit of the present invention.

FIG. 3 is a logic circuit of the data read circuit according to the present invention with an inverted signal;

FIG. 4 is an explanatory diagram of a logical operation of an EXOR gate.

FIG. 5 is an explanatory diagram of a logical operation of read data.

FIG. 6 shows a conventional data read circuit.

[Explanation of symbols]

 10 Read control units 21, 22, 23, ... 2n registers 31, 32, 33, ... 3n AND gates 41, 42, 43 EXOR gates 51, 52, 53 Equivalent gate 61 NAND gate 62 Equivalent EXOR gate 70 OR Gate 71, 72, 73 Equivalent gate 80 EXOR gate 81 OR gate 82, 83 Equivalent gate 91, 92 Equivalent gate 100 Data bus

Claims (4)

[Claims] 1. A data read circuit for reading a plurality of data via a data bus, comprising: a logical sum means for outputting a logical sum of the plurality of data; and a logical product means for outputting a logical product of the plurality of data. A data read circuit for comparing the read logical sum output and logical product output with expected values. 2. A data reading circuit for reading a plurality of data via a data bus, wherein, if there is no inversion signal, a logical sum of the plurality of data and outputs the result to the data bus, And a logical AND means for outputting logical product data to the data bus by taking a logical sum after inverting if there is an inverted signal, and a logical reading means. 3. A data reading circuit for reading a plurality of data having the same expected value via a data bus, comprising: a plurality of EXOR gates for respectively inverting the plurality of data by a plurality of inversion signals; And an OR gate for summing and outputting the sum to the data bus. 4. A data reading circuit for reading, via a data bus, a plurality of data expected to store data having the same expected value in a storage means, wherein the plurality of data are inverted by a plurality of inversion signals, respectively. EXOR gate, and an OR for outputting a logical sum of outputs of the plurality of EXOR gates
An R gate; and an EXOR gate for inverting the output of the OR gate again with a signal obtained by logically ORing the plurality of inverted signals, and outputting the inverted data to the data bus. A data reading circuit for performing reading with a logical product.