JP2002368783A - Atm inverse multiplexing and base station for mobile communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM inverse multiplexing that selects a synchronizing signal such as a clock signal as required. SOLUTION: A line interface 23 of an ATM inverse multiplexing section 13 generates a reference signal from an ATM frame received via each transmission line 6 by each transmission line 6 and outputs the reference signal to an IMA(Inverse Multiplexing for ATM) circuit 20. The IMA circuit 20 transfers a plurality of the reference signals to a PLL circuit 21. The PLL circuit 21 sets the reference signal whose phase is most delayed among a plurality of the reference signals as a synchronizing signal. On the occurrence of a fault or the like in the transmission line corresponding to the reference signal set to be the synchronizing signal, the IMA circuit 20 outputs a synchronizing switching signal to the PLL circuit 21. The PLL circuit 21 in response to the synchronizing switching signal sets the reference signal whose phase is next delayed to the reference signal set at present as the synchronizing signal for a new synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
ATM inverse multiplexing processing (IMA: Inverse) including a round robin procedure, which is mounted on a base station of a DMA mobile communication system.
ATM demultiplexer that performs Multiplexing for ATM)
And the mobile communication base station.

[0002]

2. Description of the Related Art A W-CDMA mobile communication system, which is one of the third generation mobile phone systems scheduled to start services in 2001, is capable of transmitting a large amount of data as compared with the second generation. . In order to realize the transmission of the large amount of data, the base station and the base station controller are required
Construction using a TM network is being considered.

In this ATM network, a base station and a base station controller are connected to each other via a wired transmission line. As this transmission line, for example, a transmission line having a communication speed called T1 / E1 can be used. here,
T1 is a transmission line having a communication speed of 1.544 Mbit / s,
E1 is a transmission line having a communication speed of 2.048 Mbit / s.

[0004] However, with the development of the ATM technology for the wide area network and the increase in the number of users, it is expected that the demand for a transmission line faster than the T1 / E1 transmission line will increase. Therefore, in order to meet such demands, it is conceivable to use a transmission path called T3 / E3 as the transmission path. Here, T3 is a transmission line having a communication speed of 44.736 Mbit / s, and E3 is a transmission line having a communication speed of 34.368 Mbit / s.

[0005] However, the cost of the T3 / E3 transmission line is still high, and the cost ratio when the T3 / E3 transmission line is actually used for the entire speed is not always sufficient.
It is not something that TM companies find attractive. Therefore, T3 /
In order to provide a high-speed transmission line that is more cost-effective than the E3 transmission line, it is conceivable to employ IMA technology.

The IMA can multiplex a plurality of T1 / E1 transmission lines as one group and provide one virtual high-speed transmission line. More specifically, when transmitting and receiving ATM cells, a base station employing IMA transmits
A destination transmission path of a plurality of ATM cells constituting a cell stream is determined in accordance with a round robin procedure, or an original AT is transmitted from an ATM frame received through a plurality of transmission paths.
And restore the M cell stream. In other words, the plurality of ATM cells constituting the ATM cell stream are distributed and transmitted to the plurality of T1 / E1 transmission lines regardless of their order.

[0007] With this configuration, since a plurality of T1 / E1 transmission lines are used, a substantial transmission speed can be improved, and high-speed transmission comparable to one T3 / E3 transmission line can be realized. In addition, even if a plurality of T1 / E1 transmission lines are used to realize high-speed transmission equivalent to one T3 / E3 transmission line, the cost can be reduced as compared with the case where one T3 / E3 transmission line is used. .

[0008]

By the way, as a synchronization signal when IMA processing is executed in the base station, for example, any one of the reference signals extracted from each T1 / E1 transmission line is adopted. More specifically, a frame bit is added to the head of the ATM frame received via the T1 / E1 transmission line. The base station generates a frame pulse in response to the reception of the frame bit, and generates a clock based on the frame pulse and the transmission speed of the T1 / E1 transmission line. The base station adopts one of the generated clocks corresponding to each transmission path as a synchronization signal. Therefore, for example, when restoring the original ATM cell stream from the received ATM frame, the restoration process is started in response to the clock.

However, if the transmission of an ATM frame becomes impossible due to, for example, a failure in a transmission path corresponding to a clock employed as a synchronization signal, the clock cannot be generated. On the other hand, in a base station employing the conventional IMA technology, switching of a clock once adopted as a synchronization signal is not performed. Therefore, it is conceivable to use the clock that has been generated until then.

However, in the case where the clock which has been adopted as the synchronization signal corresponds to the transmission line whose phase lags behind that of the other transmission lines, for example, when restoring an ATM cell stream, it is necessary to pass through the other transmission lines. It is necessary to make the received ATM cells uselessly wait. for that reason,
It is not possible to use the clock generated up to that point.

An object of the present invention is to provide an AT which can switch a synchronization signal such as a clock as needed.
An M demultiplexer is provided.

Another object of the present invention is to provide the above-mentioned AT.
An object of the present invention is to provide a mobile communication base station capable of realizing highly reliable communication by providing an M demultiplexer.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an ATM demultiplexer having an IMA circuit for executing a round-robin procedure, comprising: a plurality of reference signals respectively corresponding to a plurality of transmission paths; Or the above IM
When the synchronization signal of the A circuit is used, another reference signal of the plurality of reference signals is newly used as a synchronization signal in accordance with a predetermined synchronization switching condition.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a conceptual diagram showing an overall configuration of a W-CDMA mobile communication system according to Embodiment 1 of the present invention. This W
The CDMA mobile communication system provides a voice and data communication service to a mobile station 1 such as a mobile phone, and includes an infrastructure device 4 including a plurality of base stations 2 and a base station control device 3. The base station 2 has a unique wireless zone (cell) 5 and wirelessly communicates with the mobile station 1 in the cell 5. The base station control device 3 is connected to a plurality of base stations 2 and controls each base station 2. Specifically, the base station control device 3 switches the radio line between the mobile station 1 and the base station 2 or changes the base station control device 3
And transfer communication data transmitted from a line control device to a predetermined base station.

The base station 2 and the base station controller 3 are connected via a wired transmission line 6 such as an optical fiber. The transmission line 6 includes a plurality of (for example, 16) transmission lines, and each of the transmission lines 6 has a relatively low transmission speed. Specifically, each transmission line 6 is a T1 / E1 transmission line that is slower than a T3 / E3 transmission line. Here, T1
Is a transmission line having a transmission rate of 1.544 Mbit / s, and E1
Is a transmission line having a transmission speed of 2.048 Mbit / s.

FIG. 2 is a block diagram showing the internal configuration of the base station 2. As shown in FIG. The base station 2 includes a wireless transmission / reception unit 10, a baseband processing unit 11, and a data processing unit 12. The wireless transmission / reception unit 10, the baseband processing unit 11, and the data processing unit 12 are each configured by a dedicated card, for example. The data processing unit 12 performs various processes on communication data. Data processing unit 12
Has an ATM inverse multiplexing unit 13. The ATM demultiplexing unit 13 should convert the communication data given from the baseband processing unit 11 into ATM cells and ATM frames, and give the ATM frames received via the plurality of transmission paths 6 to the baseband processing unit 11 Or convert it to communication data.

The baseband processing section 11 modulates communication data supplied from the data processing section 12 to create modulated communication data, or demodulates modulated communication data supplied from the radio transmission / reception section 10 to generate original communication data. Or restore data. The radio transmitting / receiving unit 10 includes a high-frequency CDMA including modulated communication data provided from the baseband processing unit 11.
A signal is created and wirelessly transmitted to the mobile station 1, or modulated communication data is extracted from a CDMA signal wirelessly transmitted from the mobile station 1 and transferred to the baseband processing unit 11. For example, when transmitting a CDMA signal, the wireless transmitting / receiving unit 10 sets a wireless frame for wirelessly transmitting the CDMA signal, and transmits the CDMA signal for each wireless frame.

FIG. 3 is a conceptual diagram showing a configuration example of an ATM frame. This ATM frame F is 1.5 Mbit / se
This corresponds to the communication line c (1.5 M Highway). In the first embodiment, A of another structure is used.
A TM frame can also be applied. This ATM frame F has a frame bit FB at the beginning, and a plurality of ATM cells S1, S1 following the frame bit FB.
,..., Sn (hereinafter collectively referred to as “ATM cell S”). The plurality of ATM cells S are not always arranged in the order of the original ATM cell stream, but are arranged in the order determined according to a round robin procedure described later. At a predetermined position from the beginning of the frame, A
A synchronization cell S3, which is a kind of TM cell, is arranged. The synchronization cell S3 is a cell having a synchronization bit SB. The synchronization bit SB is used for defining the start timing of a radio frame in the radio transmission / reception unit 10.

FIG. 4 is a block diagram showing the internal configuration of the ATM demultiplexing unit 13. The ATM demultiplexing unit 13 has an IMA circuit 20 that executes a round robin procedure, and executes the demultiplexing process described above. More specifically,
The ATM demultiplexing unit 13 is configured to transmit a plurality of ATMs included in a plurality of ATM frames received via the plurality of transmission paths 6 respectively.
An ATM cell stream is restored from a TM cell according to a round robin procedure. The ATM demultiplexing unit 13 converts the communication data provided from the baseband processing unit 11 into a plurality of ATM cells, determines a transmission path of the plurality of ATM cells according to a round-robin procedure, and then performs an ATM operation.
A frame is created, and the ATM frame is transmitted to a plurality of transmission paths 6.

ATM received via a plurality of transmission paths 6
The frame has a frame bit at the head as described above. The ATM demultiplexing unit 13 generates a frame pulse in response to detecting the frame bit. Further, the ATM demultiplexing unit 13 generates a clock corresponding to each transmission line as a reference signal based on the frame pulse and a predetermined transmission speed of each transmission line 6. Since the transmission paths 6 are different logical paths, reception timings are usually different from each other. Therefore, the phases of the reference signals are also different from each other.

The ATM demultiplexer 13 selects one of a plurality of reference signals respectively corresponding to the plurality of transmission paths 6 generated in this way, and converts the reference signal into the IMA circuit 2.
Used as a synchronization signal of 0. In this state, the AT
The M demultiplexer 13 has a function of newly setting another reference signal of the plurality of reference signals as a synchronization signal in accordance with a predetermined synchronization switching condition. In other words, the ATM demultiplexer 1
Reference numeral 3 switches a reference signal used as a synchronization signal when a predetermined synchronization switching condition is satisfied. The synchronization switching condition is, for example, that the ATM frame is not received from the transmission line 6 corresponding to the reference signal set as the synchronization signal for a predetermined time.

With this configuration, for example, even when a failure occurs in the transmission line 6 corresponding to the reference signal set as the synchronization signal and when a maintenance check is performed,
Another reference signal can be newly set as a synchronization signal. Therefore, communication can be continued while preventing unnecessary processing waiting.

The reference for switching the reference signal is the phase of each reference signal. More specifically, the ATM demultiplexing unit 13
First, the reference signal with the most delayed phase is set as the synchronization signal, and when switching the reference signal, the reference signal with the next delayed phase is set. That is, synchronization is achieved in accordance with the transmission path 6 whose reception timing is delayed. Therefore, for example, from a plurality of received ATM cells, the original A
When restoring the TM cell stream, the restoration of the ATM cell stream can be realized in accordance with the timing of the latest received ATM cell.

Further, when switching from the reference signal set as the synchronization signal to another reference signal, the ATM demultiplexing unit 13 performs a switching operation so that the phase of the synchronization signal changes continuously. More specifically, when switching from the reference signal set as the synchronization signal to another reference signal, the ATM demultiplexing unit 13 changes the phase of the synchronization signal from the phase of the reference signal before switching to the reference after switching. It includes a PLL circuit 21 that continuously changes the phase of the signal. More specifically, the ATM demultiplexing unit 13 controls the synchronization signal such that the phase of the synchronization signal continuously changes in one direction from the phase before the switching to the phase after the switching during a predetermined time from the switching start timing. Switch the reference signal for the synchronization signal. Here, the above-mentioned predetermined time is, for example, a minimum average time required for the wireless transmission / reception unit 10 to detect a synchronization bit in an ATM frame starting from the switching start timing and is predetermined.

With this configuration, unlike the case where the reference signal is instantaneously switched, data does not shift. Therefore, switching of the reference signal can be realized without affecting communication.

FIG. 5 is a block diagram showing the internal configuration of the ATM demultiplexer 13 in more detail. The ATM demultiplexing unit 13 includes a cell conversion circuit 22, an IMA circuit 20, a line interface 23, a PLL circuit 21, and a control circuit 24. The cell conversion circuit 22 includes the baseband processing unit 1
It converts the communication data from No. 1 into ATM cells to create an ATM cell stream, and restores the ATM cell stream from the IMA circuit 20 into communication data. The line interface 23 frames a plurality of ATM cells provided from the IMA circuit 20 or decomposes ATM frames received via the plurality of transmission paths 6 into individual ATM cells. The PLL circuit 21 is connected to the base station 2
This is for setting the synchronization signal used as a whole. The control circuit 24 includes, for example, a CPU and controls the operation of the ATM demultiplexing unit 13.

More specifically, the IMA circuit 20 includes a round robin execution unit 30, a buffer 31, a reference signal transfer unit 32, a synchronization signal output unit 33, and a switching signal output unit 34. The round robin execution unit 30 determines a transmission destination according to a round robin procedure, gives an ATM cell to the line interface 23, or sets an AT cell according to the round robin procedure.
Or disassemble the M cell. The buffer 31 temporarily holds an ATM cell (RB-cell) provided from the line interface 23. The reference signal transfer unit 32
A plurality of reference signals (ref) provided from the line interface 23 are transferred to the PLL circuit 21. The synchronization signal output unit 33 outputs a synchronization signal (syn) provided from the PLL circuit 21 to another unit. The switching signal output unit 34 outputs a synchronization switching signal (ch) for switching the reference signal to the PLL circuit 21.

The line interface 23 includes a frame creation unit 40, a frame decomposition unit 41, a reference signal generation unit 42, and a transmission line monitoring unit 43. Frame creation unit 40
Is an ATM cell (TA-cel) supplied from the IMA circuit 20.
An ATM frame is created from l). The frame disassembly unit 41 receives the A
Separate and extract ATM cells from TM frame and IMA circuit 2
0 is output. The reference signal generator 42 generates a frame pulse in response to each frame bit of the plurality of ATM frames received via the plurality of transmission paths 6. Further, the reference signal generation unit 42 generates a clock based on the frame pulse and the transmission speed of each transmission path 6. In the first embodiment, this clock is used as a reference signal. The transmission path monitoring unit 43 monitors the state of the plurality of transmission paths 6.

The PLL circuit 21 includes a reference signal holding unit 50,
A reference signal comparison unit 51 and a synchronization signal setting / switching unit 52 are provided. The reference signal holding unit 50 holds a plurality of reference signals (ref) provided from the IMA circuit 20. The reference signal comparing section 51 compares the phases of a plurality of reference signals held in the reference signal holding section 50 with each other. The synchronization signal setting / switching section 52 sets one of the reference signals as a synchronization signal (syn) based on the comparison result of the reference signal comparison section 51. More specifically, the synchronization signal setting / switching unit 52 sets a reference signal with the most delayed phase as a synchronization signal, and outputs the synchronization signal to the IMA circuit 20. In addition, the synchronization signal setting / switching unit 52 switches the synchronization signal to the reference signal having the next phase delay after the current reference signal in response to the synchronization switching signal given from the IMA circuit 20.

The details of each component will be described below. First, each component when transmitting and receiving ATM cells will be described. CDMA transmitted from mobile station 1
When the communication data included in the signal is provided from the baseband processing unit 11, the cell conversion circuit 22 sequentially divides the communication data into blocks each having a predetermined length of 53 bytes and adds control data to each block. Thus, an ATM cell is created. The cell conversion circuit 22 outputs the ATM cells in chronological order. That is, this output becomes an ATM cell stream, and the ATM cell stream is arranged in the order of communication data. The ATM cell stream is provided to the IMA circuit 20.

Round robin execution unit 3 of IMA circuit 20
0, upon receiving the ATM cell stream, determines an ATM cell transmission path according to a round robin procedure. More specifically, the round robin execution unit 30 determines to which of the plurality of transmission paths 6 the ATM cell is transmitted. In this case, the round robin execution unit 30 associates, for example, a plurality of ATM cells with a plurality of transmission paths 6 at predetermined intervals. The predetermined cycle corresponds to the number of transmission paths. Therefore, ATM cells to be transmitted to one transmission line are ATM cells appearing at predetermined intervals in the ATM cell stream. It is needless to say that the transmission order may be determined by a method other than the above as a round robin procedure. The round robin execution unit 30 sequentially provides the ATM cells to the line interface 23 in a state where the identification information (line number) of the transmission line is associated with each ATM cell.

Upon receiving the ATM cell from the IMA circuit 20, the frame creating unit 40 of the line interface 23
Based on the identification information associated with the ATM cell,
The ATM cell is transmitted to the corresponding transmission line 6. In this case, the frame creation unit 40 calculates the start timing of the ATM frame based on the frame pulse generated at the time of receiving the ATM frame, and sequentially transmits a plurality of ATM cells to the transmission line 6 in response to the start timing. Send out. Specifically, the frame creation unit 40 sends out frame bits to the transmission path 6 in response to the start timing of each ATM frame, and sends out ATM cells following the frame bits. Further, the frame creation unit 40 is configured to transmit a predetermined number of ATMs.
After transmitting the cell, the synchronization cell is transmitted to the transmission line 6.

On the other hand, when an ATM frame is transmitted from each transmission line 6, the frame decomposing unit 41 of the line interface 23 decomposes the ATM frame into individual ATM cells, and sequentially transmits the ATM cells to the IMA circuit 20. give. The IMA circuit 20 temporarily stores the plurality of ATM cells input from the line interface 23 in the buffer 31 instead of immediately processing the ATM cells. The buffer 31 has a PL
In response to the synchronization signal given from the L circuit 21, the held ATM cell is output to the round robin execution unit 30.

As a result, the round robin execution unit 30
The plurality of ATM cells are decomposed according to a round robin procedure to restore the original ATM cell stream. In this case, the round robin procedure is the same as that used in the ATM demultiplexing unit of the source base station. The round robin execution unit 30 supplies the restored ATM cell stream to the cell conversion circuit 22. Cell conversion circuit 22
Converts each ATM cell of the ATM cell stream into communication data, and converts the communication data into a baseband processing unit 1.
Output to 1.

Next, the setting of the synchronization signal will be described.
When receiving the ATM frame via each transmission line 6, the reference signal generation unit 42 of the line interface 23 responds to the frame timing of the received ATM frame by
A frame pulse is generated for each transmission path 6. Further, the reference signal generation unit 42 generates a clock as a reference signal for each transmission path 6 based on the generated frame pulse and the transmission speed of each transmission path 6. Reference signal generator 42
Is used to transfer all the reference signals for each transmission path 6 to the IMA circuit 20.
Output to

The reference signal transfer section 32 of the IMA circuit 20
All of the plurality of reference signals provided from the line interface 23 are transferred to the PLL circuit 21. As a result, PL
The L circuit 21 selects a predetermined reference signal from the plurality of reference signals, and supplies the selected reference signal to the IMA circuit 20 as a synchronization signal. Synchronization signal output unit 33 of IMA circuit 20
Converts the synchronization signal into the round robin execution unit 30 described above.
Is given to the buffer 31 for use in the processing in. The synchronization signal output unit 33 outputs the synchronization signal not only to the line interface 23 and the cell conversion circuit 22 in the ATM demultiplexing unit 13 but also to the baseband processing unit 11 and the wireless transmission / reception unit 10. That is, the first embodiment
Operates on the basis of the synchronization signal generated in the ATM demultiplexing unit 13.

Next, the setting of the synchronization signal in the PLL circuit 21 will be described in detail. When a plurality of reference signals are transferred from the IMA circuit 20, the reference signal holding unit 50 of the PLL circuit 21 temporarily holds the plurality of reference signals.
When receiving all of the plurality of reference signals, the reference signal holding unit 50 provides the plurality of reference signals to the reference signal comparison unit 51. The reference signal comparing section 51 compares the phases of the respective reference signals with each other. As a result, the reference signal comparison unit 51 gives the reference signal with the most delayed phase to the synchronization signal setting / switching unit 52. That is, the synchronization is performed in accordance with the transmission path whose reception timing is most delayed. The synchronization signal setting / switching section 52 uses the reference signal as a synchronization signal to generate the IMA circuit 2.
Output to 0. Thus, the setting of the synchronization signal is achieved.

As shown in FIG. 6, the reference signals corresponding to the plurality of transmission paths 6 do not always have the same phase but have different phases. That is, even when the ATM frame is transmitted, the ATM frame is received at different timing as a result of being transmitted through each transmission path.
For this reason, when processing is performed in the IMA circuit 20, the processing cannot be performed normally unless the timing is adjusted to the transmission path with the latest reception timing. Therefore, the reference signal with the most delayed phase is used as the synchronization signal. In the example of FIG. 6, among the reference signals 1, 2,..., M, the reference signal 1 has the most advanced phase and the reference signal m has the most delayed phase, so that the reference signal m is set as the synchronization signal. Is done.

Next, switching of the synchronization signal will be described. The transmission line monitoring unit 43 of the line interface 23 monitors the line states of the plurality of transmission lines 6. More specifically, the transmission path monitoring unit 43 monitors whether an ATM frame is received from each transmission path 6. If the ATM frame has not been received for a predetermined time,
The transmission path monitoring unit 43 outputs a failure detection signal to the control circuit 24. That is, if the ATM frame does not arrive for a predetermined time, it can be considered that the transmission line 6 has been disconnected due to the occurrence of a failure or maintenance. When the control circuit 24 receives the failure detection signal,
The failure detection signal is transferred to the IMA circuit 20.

The switching signal output unit 34 of the IMA circuit 20
When the failure detection signal is received from the control circuit 24, it is determined whether or not the synchronization signal should be switched. If it is determined that the synchronization signal should be switched, a synchronization switching signal is given to the PLL circuit 21. More specifically, the switching signal output unit 34 determines whether the transmission path corresponding to the given failure detection signal matches the transmission path corresponding to the reference signal selected as the synchronization signal. That is, the switching signal output unit 34 determines whether a predetermined synchronization switching condition is satisfied. If the transmission path corresponds to the selected reference signal, the reference signal cannot be generated from that transmission path thereafter, so the switching signal output unit 34 supplies the synchronization switching signal to the PLL circuit 21.

Synchronous signal setting / switching section 5 of PLL circuit 21
2 switches the synchronization signal when receiving the synchronization switching signal. Specifically, the synchronization signal setting / switching unit 52 replaces the reference signal that is delayed in phase after the reference signal currently set as the synchronization signal with a new one based on the comparison result output from the reference signal comparison unit 51. Select as sync signal. Specifically, when the IMA circuit 20 outputs the synchronization switching signal, the reference signal currently set as the synchronization signal is not output to the PLL circuit 21, so that the phase difference outputted from the reference signal comparing unit 51 is the most different. The reference signal is a reference signal whose phase is delayed next to the current reference signal.

When switching the synchronization signal, the synchronization signal setting / switching section 52 switches slowly, instead of instantaneously. More specifically, the synchronization signal setting / switching unit 52
Has a predetermined time constant, and performs the switching operation of the reference signal according to the time constant. More specifically, the synchronization signal setting / switching section 52 continuously changes the phase of the synchronization signal in one direction from the phase of the reference signal currently set as the synchronization signal to the phase of the new reference signal. That is, the synchronization signal setting / switching section 52 outputs the synchronization signal while continuously changing the phase, as shown in FIGS. Therefore, the synchronization signal is not switched instantaneously from the reference signal before switching, but is switched after a time based on the time constant elapses.

As described above, the switching of the synchronization signal with the time constant and the slow switching is performed by the AT corresponding to the 1.5 Mbit / sec communication line as in the first embodiment.
In the case of using the M frame, for example, the following reasons are given. As described above, the synchronization signal is transmitted to the ATM demultiplexer 1
3 as well as the baseband processing unit 11 and the wireless transmission / reception unit 10. That is, the wireless transmitting and receiving unit 10
It operates in synchronization with the synchronization signal generated in the TM demultiplexing unit 13.

On the other hand, the radio transmitting / receiving unit 10 detects the synchronization bit SB in the communication data obtained through the ATM demultiplexing unit 13 and the baseband processing unit 11, and detects the synchronization bit SB.
A radio frame is generated in response to B. Therefore, if the synchronization bit SB cannot be detected, a radio frame cannot be generated, and as a result, a CDMA signal cannot be transmitted.

Before the switching of the synchronization signal, the synchronization bit SB is detected at the timing synchronized with the synchronization signal before the switching, so that the radio transmission / reception unit 10 can easily detect the synchronization bit. However, if the synchronization signal is instantaneously switched, the synchronization timing is greatly shifted. Therefore, it takes some time until the synchronization bit SB is detected at the timing synchronized with the switched synchronization signal. As a result, synchronization is lost, and a wireless frame cannot be generated, and communication may be disconnected.

Therefore, the synchronization signal is not suddenly switched until the radio transmission / reception section 10 can reliably detect the synchronization bit SB, but is switched while gradually shifting the phase. The time required for this is a time during which the synchronization bit SB can be reliably detected at a timing synchronized with the switched synchronization signal. Then, since the synchronization timing does not greatly shift, the wireless transmission / reception unit 10 can detect the synchronization bit SB even during the switching of the synchronization signal. For this reason, the synchronization can be prevented from being lost, and as a result, the communication can be continued.

As described above, according to the first embodiment,
When a failure occurs in the transmission path corresponding to the reference signal set as the synchronization signal, or when maintenance and inspection of the transmission path is started, the synchronization signal can be switched to another reference signal. Therefore, the base station 2 can perform appropriate processing according to the situation at that time. For example, in performing an ATM cell stream restoration process, A
The above-described restoration processing can be performed satisfactorily while preventing unnecessary standby of the TM cell. Therefore, it is possible to provide an ATM demultiplexing processing unit and a base station with improved processing efficiency.

Further, since the synchronization signal is switched while changing the phase continuously for a predetermined time, instead of suddenly switching, the synchronization can be prevented from being lost in the radio transmitting / receiving unit and the continuation of communication can be realized. . Therefore, a base station that realizes highly reliable communication can be provided.

Second Embodiment In the first embodiment, the clock of each transmission line is set as a synchronization signal, and is switched as necessary. On the other hand, in the second embodiment, in addition, a frame pulse is set as a synchronization signal, and switching is performed as necessary. In the following, for convenience, the synchronization signal corresponding to the clock is referred to as “clock synchronization signal”, and the synchronization signal corresponding to the frame pulse is referred to as “frame synchronization signal”. In the following description, reference is made to FIG.

As described above, the frame pulse is generated in the line interface 23 in response to the first frame data of the ATM frame received via each transmission line 6. The frame pulse is used not only as a reference timing for generating a clock but also for defining the transmission timing of the ATM frame in the line interface 23.

More specifically, the line interface 23
Transmits the ATM frame in synchronization with the same timing when transmitting the ATM frame to each transmission path 6. On the other hand, since the frame pulse is obtained for each transmission path 6, the timing differs for each transmission path. Therefore, in the second embodiment, the frame pulse of the transmission line 6 whose timing is the most delayed is used as the frame synchronization signal, and the ATM frame is transmitted in synchronization with the frame synchronization signal.

However, when a failure occurs in the transmission line 6 corresponding to the frame pulse set as the frame synchronization signal, the frame synchronization signal cannot be generated, and the same problem as the clock in the first embodiment occurs. . Therefore, in the second embodiment, the frame synchronization signal is switched as needed.

More specifically, the line interface 1
The reference signal generation unit 42 of the IMA circuit 20 uses the generated frame pulse and clock as reference signals, respectively.
Output to The reference signal transfer unit 32 of the IMA circuit 20
Each reference signal corresponding to each of the transmission paths 6 is transmitted to the PLL circuit 2
Transfer to 1. Reference signal holding unit 50 of PLL circuit 21
Holds all of the plurality of reference signals, and outputs the reference signals to the reference signal comparison unit 51.

The reference signal comparing section 51 is provided in the first embodiment.
Similarly to the above, the phases of a plurality of clocks are compared with each other, and the clock with the most delayed phase is output to the synchronization signal setting / switching unit 52. Further, the reference signal comparing unit 51 compares the phases of a plurality of frame pulses with each other, and outputs the frame pulse with the most delayed phase to the synchronization signal setting / switching unit 52. Note that the transmission path corresponding to the clock output to the synchronization signal setting / switching unit 52 and the transmission path corresponding to the frame pulse are usually the same transmission path.

The synchronization signal setting / switching section 52 outputs the input clock to the IMA circuit 20 as a clock synchronization signal as in the first embodiment. In addition, the synchronization signal setting / switching section 52 supplies the input frame pulse to the line interface 23 as a frame synchronization signal as shown by a broken line in FIG. When receiving the frame synchronization signal, the frame creation unit 40 of the line interface 23 receives
The ATM frame is simultaneously transmitted to each transmission path 6 at a timing synchronized with the frame synchronization signal.

Further, a failure detection signal is transmitted from the transmission line monitor 43 of the line interface 23 via the control circuit 24 to the IM.
When given to the A circuit 20, the switching signal output unit 34 of the IMA circuit 20 checks a transmission path corresponding to the failure detection signal. If the checked transmission path is a transmission path corresponding to a clock and / or a frame pulse set as a synchronization signal, the switching signal output unit 34 outputs the synchronization switching signal to P
Output to the LL circuit 21.

Synchronous signal setting / switching section 5 of PLL circuit 21
In the second embodiment, similarly to the first embodiment, a clock whose phase is delayed next to the clock currently set as the synchronization signal is newly set as the clock synchronization signal. Further, the synchronization signal setting / switching section 52 sets a frame pulse whose phase is delayed next to the frame pulse currently set as the frame synchronization signal as a new frame synchronization signal.

In this case as well, the synchronization signal setting / switching section 52 changes the phase continuously from the phase of the clock / frame pulse before switching to the phase of the clock / frame pulse after switching. , And outputs a clock synchronization signal / frame synchronization signal.

As described above, according to the second embodiment,
Since not only the clock synchronization signal but also the frame synchronization signal can be switched as required, the transmission of the ATM frame can be performed satisfactorily.

In the above description, a case where both the clock and the frame pulse are used as reference signals is taken as an example. However, needless to say, for example, only the frame pulse may be used as the reference signal and the reference signal may be output to the IMA circuit 20.

Third Embodiment In the first and second embodiments, all of the clocks and / or frame pulses corresponding to a plurality of transmission paths are converted to PLL.
Circuit 21. That is, all reference signals are set as synchronization signal candidates. On the other hand, in the third embodiment, some of the reference signals corresponding to the plurality of transmission paths 6 are set as synchronization signal candidates.

More specifically, the line interface 23
The reference signal generation unit 42 of I.I. uses clocks and / or frame pulses corresponding to all the transmission lines 6 as reference signals.
Output to MA circuit 20. On the other hand, the reference signal transfer unit 32 of the IMA circuit 20 specifies two of the plurality of transmission paths 6 in advance, and outputs only the reference signals corresponding to the two transmission paths to the PLL circuit 21. I have to. The two transmission lines to be candidates for the synchronization signal are, for example, previously checked the transmission state of a plurality of transmission lines 6, and among them, a transmission line having the highest phase delay frequency and a transmission line having the next highest phase delay frequency are selected. Can be set.

After holding the two reference signals in the reference signal holding section 50, the PLL circuit 21
At 1, the phases are compared with each other. Reference signal comparison unit 51
Supplies the reference signal whose phase is delayed to the synchronization signal setting / switching section 52. Synchronous signal setting / switching unit 52
Outputs the reference signal to the IMA circuit 20. In addition,
When a frame pulse is included as a reference signal, the frame pulse is output to the line interface 23 as a frame synchronization signal. Also, the IMA circuit 20
Is output to the PLL circuit 21 from
The synchronization signal setting / switching section 52 of the PLL circuit 21 outputs the other of the currently set reference signals as a synchronization signal. Also in this case, the synchronization signal setting / switching unit 52
Outputs a synchronization signal such that the phase continuously changes from the phase of the reference signal before switching to the phase of the reference signal after switching.

As described above, according to the third embodiment as well, the synchronization signal can be switched.
In this case, processing according to the situation at that time can be appropriately performed. In addition, when the synchronization signal is switched, the switching is performed while the phase is continuously changed over a predetermined period of time, instead of suddenly switching, so that loss of synchronization or the like can be prevented. In addition, since the number of reference signal candidates to be set as the synchronization signal is reduced to two in advance, the processing of the PLL circuit 21 can be simplified.

[0066]

As described above, according to the present invention, since the synchronization signal can be switched, it is possible to execute the processing in the IMA circuit in a form appropriate for the situation at that time. If the above-described ATM demultiplexing device is provided in the mobile communication base station, highly reliable communication can be realized.

[Brief description of the drawings]

FIG. 1 shows W-CDMA according to Embodiment 1 of the present invention.
FIG. 1 is a conceptual diagram illustrating an overall configuration of a mobile communication system.

FIG. 2 is a block diagram illustrating an internal configuration of a base station.

FIG. 3 is a conceptual diagram showing a configuration of an ATM frame.

FIG. 4 is a block diagram showing an internal configuration of an ATM demultiplexing unit.

FIG. 5 is a block diagram showing the internal configuration of the ATM demultiplexing unit in further detail.

FIG. 6 is a diagram showing each reference signal corresponding to a plurality of transmission paths.

FIG. 7 is a diagram illustrating a phase relationship between synchronization signals when the synchronization signals are switched.

[Explanation of symbols]

2 base stations, 6 transmission lines, 13 ATM demultiplexer, 20
IMA circuit, 21 PLL circuit, 23 line interface, 30 round robin execution unit, 34 switching signal output unit, 42 reference signal generation unit, 43 transmission line monitoring unit, 51
Reference signal comparison unit, 52 synchronization signal setting / switching unit.

Continued on the front page F term (reference) 5K022 EE01 EE13 EE36 5K028 AA14 BB06 CC05 KK03 KK35 MM16 NN31 QQ01 5K030 HA10 HB15 HB29 HC09 JA01 JT09 5K047 AA11 BB01 BB16 CC02 GG07 KK18 MM11

Claims (11)

[Claims] 1. An ATM demultiplexer having an IMA circuit for executing a round robin procedure, wherein one of a plurality of reference signals respectively corresponding to a plurality of transmission paths is transmitted to the IM.
An ATM demultiplexer characterized in that, when the synchronization signal of the A circuit is used, another reference signal of the plurality of reference signals is newly used as a synchronization signal in accordance with a predetermined synchronization signal switching condition. . 2. An ATM demultiplexer for restoring an ATM cell stream from a plurality of ATM cells included in a plurality of ATM frames received via a plurality of transmission lines in accordance with a round-robin procedure. Synchronizing signal setting means for setting a predetermined reference signal among a plurality of reference signals corresponding to the synchronizing signal; determining means for determining whether a predetermined synchronizing signal switching condition is satisfied; An ATM demultiplexing device, comprising: a synchronizing signal switching means for switching a reference signal set as the synchronizing signal to another of the plurality of reference signals in the event of the occurrence. 3. The synchronizing signal switching means according to claim 2, wherein, when switching from the reference signal set as the synchronizing signal to the other reference signal, the phase of the synchronizing signal changes continuously. An ATM demultiplexer for performing a switching operation. 4. The synchronization signal switching means according to claim 3, wherein when switching from the reference signal set as the synchronization signal to the other reference signal, the synchronization signal switching means changes the phase of the reference signal before switching. An ATM demultiplexing device comprising a PLL circuit which continuously changes the phase of a reference signal after switching from a predetermined period to a predetermined period. 5. The method according to claim 4, wherein the predetermined time is set to a time required to detect synchronization data included in any of the plurality of received ATM frames. ATM demultiplexer. 6. The method according to claim 2, further comprising: generating a plurality of reference signals corresponding to each transmission path based on a reception timing of the ATM frame received via the plurality of transmission paths. ATM demultiplexing means for setting a predetermined reference signal from among a plurality of reference signals generated by the reference signal generating means. apparatus. 7. The method according to claim 6, wherein the reference signal is an ATM signal.
An ATM demultiplexer which is a clock obtained based on a frame pulse of a frame and / or the frame pulse. 8. The apparatus according to claim 2, further comprising: a reference signal comparing unit that compares phases of the plurality of reference signals with each other, wherein the synchronization signal setting unit includes a plurality of reference signals. And setting the reference signal having the most delayed phase as a synchronization signal. The synchronization signal switching means includes a reference signal having a phase delayed next to the reference signal set as the synchronization signal among the plurality of reference signals. An ATM demultiplexer characterized by switching to (1). 9. The ATM demultiplexer according to claim 2, wherein any two of said plurality of reference signals are candidates to be set as a synchronization signal. 10. The method according to claim 1, wherein
The ATM demultiplexer is such that the synchronization switching condition is that an ATM frame is not received for a predetermined time from a transmission path corresponding to a reference signal set as a synchronization signal. 11. The communication system according to claim 1, wherein the communication data is converted into ATM cells and transmitted to a plurality of transmission lines, and the communication data is restored and output from the ATM cells received via the plurality of transmission lines. And a baseband process for outputting modulated communication data to the ATM demultiplexer and demodulating and outputting communication data output from the ATM demultiplexer. Receiving a CDMA signal wirelessly transmitted from a mobile station, and
The communication data included in the DMA signal is extracted and output to the baseband processing device, and C including the communication data output from the baseband processing device is extracted.
And a radio transmitting / receiving unit that generates a DMA signal and wirelessly transmits the generated CDMA signal according to a radio frame generated at a timing synchronized with a synchronization signal set in the ATM demultiplexer. Mobile communication base station.