JP2002359332A - Semiconductor package and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sharply downsize a package as compared with a conventional one. SOLUTION: A semiconductor package 10 includes a semiconductor chip 2. The semiconductor chip includes the first and second electrodes 15 and 8 arranged above and the third electrode 16 arranged on bottom side. A heat spreader 6 is joined with the third electrode 16. Conductive first and second leads 11 and 12 are electrically connected via conductive first and second junction members 7a and 7b to the first and second electrodes 15 and 8, respectively. Each of the first and second leads 11 and 12 has feet L3 which are arranged side by side on the first side of the heat spreader 6, at its lower end. The bottom of the heat spreader 6 and the bottoms of the feet L3 of the first and second leads 11 and 12 are exposed from the bottom of an insulating sealing body 5, and besides are arranged on the same plane.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor package incorporating a semiconductor chip including a vertical MOS transistor and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 17A is a plan view showing a conventional semiconductor package incorporating a power semiconductor chip including a vertical MOS transistor. FIG. 17 (b), (c)
FIG. 18 is a sectional view taken along a longitudinal direction and a direction orthogonal to the longitudinal direction of the semiconductor package shown in FIG.

As shown in FIGS. 17A to 17C, a device mounting portion (bed portion) 110 of a lead frame 101 is provided.
Then, the power semiconductor chip 102 is mounted via the solder 103. The lead frame 101 is made of Cu, Cu alloy,
It is made of a material such as an Fe-42Ni alloy. The lead frame 101 has a bed 110, a first lead 111, a second lead 112, and a third lead 113 that is continuously connected to the bed 110. The chip 102 has a MOS transistor formed by a source region, a base region, a drain region, a gate electrode, and the like.

A metal electrode 107a of Al or the like and a metal electrode 10 of gold or Al
7b is provided. The metal electrode 107a is electrically connected to a source region and a base region via a source electrode (including a source lead electrode). The metal electrode 107b is electrically connected to a gate electrode (including a gate lead electrode).

[0005] The metal electrodes 107a, 107 of the chip 102
b is electrically connected to the first and second leads 111 and 112 via bonding wires 116 and 114 such as Au wires. The chip 102, the bed 110, the bases of the first, second and third leads 111 to 113, and the bonding wires 116 and 114 are resin-sealed by a resin sealing body 105 such as epoxy resin.

[0006]

Problems to be Solved by the Invention FIGS. 17 (a) to 17 (c)
The conventional semiconductor package shown in (1) has the following problems. A power semiconductor device, for example, a chip including a vertical MOS transistor is connected by a plurality of Au wires in order to reduce the wiring resistance of the Au wires.
In this case, as the number of electrode pads is increased and the number of connected Au wires is increased, the index of the assembling process is increased. Also, in terms of design, it is difficult to further reduce the wiring resistance due to the relationship of the wire length.

In the power semiconductor chip, it is important to secure heat radiation characteristics. From the viewpoint of improving the heat radiation characteristics, it is advantageous to make the bed portion of the lead frame on which the device is mounted thicker. In this case, the lead frame itself needs to be thick, and the entire semiconductor package becomes large. In addition, increasing the thickness of only the bed portion of the lead frame significantly increases the component cost. Therefore, it is not practical to use such a lead frame in a product.

US Pat. No. 6,040,626 (JP-A-20
Japanese Patent Application Laid-Open No. 00-114445) discloses a structure in which a first lead is directly bonded to a semiconductor chip of a vertical MOS transistor via a conductive adhesive in order to reduce wiring resistance. With this structure, however, the heat radiation characteristics of the semiconductor chip are not improved, and miniaturization is difficult because the leads protrude from the resin sealing body.

[0009] From such a background, even when a larger rated large current semiconductor chip such as a power semiconductor chip including a vertical MOS transistor is incorporated,
There is a need for a semiconductor package that does not require an increase in overall size.

[0010]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
A semiconductor package including a first and a second electrode disposed on an upper side, and a third electrode disposed on a bottom side; a heat spreader joined to the third electrode; A conductive first electrode electrically connected to the first and second electrodes via conductive first and second joining members, respectively.
And the second lead, and each of the first and second leads,
Having a foot extending laterally at a lower end thereof and arranged side by side on the first side of the heat spreader; and at least part of the foot of the semiconductor chip, the heat spreader, and the first and second leads. An insulating sealing body that embeds and seals the bottom, the bottom surface of the heat spreader, the bottom surface of the foot of the first and second leads,
Being exposed from the bottom surface of the sealing body and being arranged on substantially the same plane.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising a first and a second electrode disposed on an upper side, and a third electrode disposed on a bottom side. Bonding a heat spreader to the third electrode of the chip, electrically connecting conductive first and second leads to the first and second electrodes via conductive first and second bonding members, respectively. Connecting, each of the first and second leads has a foot extending laterally at a lower end and arranged side by side on a first side of the heat spreader;
The semiconductor chip, the heat spreader, and at least a part of the foot of the first and second leads,
Burying and sealing with an insulative sealing body, wherein the bottom surface of the heat spreader, the bottom surface of the foot of the first and second leads are exposed from the bottom surface of the sealing body, and are substantially And being arranged on the same plane.

According to a third aspect of the present invention, there is provided a semiconductor package comprising: a semiconductor chip including first and second electrodes disposed on an upper side and a third electrode disposed on a bottom side; A conductive heat spreader joined to the third electrode, wherein the heat spreader is electrically connected to the third electrode via a conductive third joining member, and functions as a third lead; First and second conductive leads electrically connected to the first and second electrodes via first and second conductive bonding members, respectively, and each of the first and second leads is a conductive strip. Where the heat spreader has a thickness t1 while the conductive strip has a thickness t2 and a thickness ratio condition 1 <t1 / t.
2 ≦ 3, and each of the first and second leads includes a base facing the upper side of the semiconductor chip;
A leg bent from the base and extending along the sides of the semiconductor chip and the heat spreader; and a leg bent from the leg and extending away from the heat spreader; The foot of the lead is arranged side by side on a first side of the heat spreader, and the entirety of the semiconductor chip, the heat spreader, the base and the legs of the first and second leads, and the first An insulating sealing body that embeds and seals at least a part of the foot of the second lead; and the sealing body is substantially made of a material selected from the group consisting of a thermosetting resin including an epoxy resin. And the bottom surface of the heat spreader and the bottom surfaces of the feet of the first and second leads are exposed from the bottom surface of the sealing body and are disposed on substantially the same plane. Characterized by comprising a being, a.

Furthermore, the embodiments of the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when an invention is extracted by omitting some constituent elements from all the constituent elements described in the embodiment, when implementing the extracted invention, the omitted part is appropriately supplemented by a well-known common technique. It is something to be done.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1A is a plan view showing a semiconductor package according to a first embodiment of the present invention incorporating a power semiconductor chip including a vertical MOS transistor. . FIGS. 1 (b) and 1 (c) show the state shown in FIG.
FIG. 2 is a cross-sectional view taken along a line IB-IB in the figure and a cross-sectional view taken along a line IC-IC. 2A and 2B are a bottom view of the semiconductor package shown in FIG. 1A and a side view on a side where leads are formed.

The semiconductor package 10 according to this embodiment
Has a power semiconductor chip 2 including a vertical MOS transistor. As will be described later, a source electrode (including a source lead electrode) and a gate lead electrode 8 are provided above the chip 2. A drain electrode is provided on the bottom side of the chip 2. The semiconductor chip 2 is mounted on a conductive heat spreader 6 via a solder (conductive bonding member) 3.

On the source electrode and the gate lead-out electrode 8, bump contacts (conductive joining members) 7a and 7b made of a conductive material such as Au are provided, respectively. First and second leads 11 and 12 made of a conductive strip are joined to the bump contacts 7a and 7b, respectively. Therefore, the first lead 11 is electrically connected to the source electrode via the bump contact 7a. The second lead 12 is electrically connected to the gate electrode lead-out electrode 8 via the bump contact 7b. The heat spreader 6 functions as a third lead because it is electrically connected to the drain electrode at the bottom of the semiconductor chip 2 via the solder 3.

The heat spreader 6 is made of a plate member made of Cu, Mo, W or the like, or a bonded structure of plate members, for example, a CKC material (Cu
/ Kovar / Cu). The conductive strips of the first and second leads 11 and 12 are formed of Cu, Cu alloy, or the like. The thickness t1 of the heat spreader 6 is larger than the thickness t2 of the conductive strip of the first and second leads 11 and 12 (t1> t2). The thickness t1 of the heat spreader 6 is 0.15 to 0.5 mm, preferably 0.15 to 0.5 mm.
It is set to 0.3 mm. The thickness t2 of the conductive strip of the lead is 0.1 to 0.3 mm, preferably 0.12 to 0.32 mm.
It is set to 0.15 mm. The ratio (t1 / t2) of the thickness t1 of the heat spreader 6 to the thickness t2 of the conductive strip of the lead is set to 1 <t1 / t2 ≦ 3.
Thereby, the heat radiation characteristic of the chip 2 via the heat spreader 6 becomes high. In the present embodiment, for example, the thickness of the conductive strip of the lead is about 0.5.
15mm, heat spreader 6 thickness is about 0.3mm
It is.

Each of the first and second leads 11 and 12 is
It has a base L1, a leg L2, and a foot L3. Base L1
Is parallel (horizontally) opposed to the upper surface of the chip 2. The leg L2 is bent from the base L1 and extends vertically along the sides of the semiconductor chip 2 and the heat spreader 6. The foot L3 bends from the leg L2 and extends horizontally to the side away from the heat spreader 6. First and second leads 11, 12
Are drawn out on only one side of the heat spreader 6, and their feet L3 are arranged side by side on the same side.

In the present embodiment, the base L1, the leg L
2, and the bending angle of the foot L3 are set to approximately 90 degrees.
This configuration contributes to miniaturization of the semiconductor package 10. In the conventional semiconductor package, since the lead has a supporting function, the leg of the lead (corresponding to the leg L2 shown in FIG. 1B) forms a large angle with respect to a horizontal plane (package mounting surface). It is formed as follows. On the contrary,
In the semiconductor package 1 according to the present embodiment, the legs L2 of the leads are arranged at an angle of 90 ° ± 10 °, preferably 90 ° ± 5 ° with respect to a horizontal plane (package mounting surface). Is established.

An insulating sealing body 5 is formed so as to embed and seal the semiconductor chip 2, the solder 3, the heat spreader 6, the first and second leads 11 and 12, and the bump contacts 7a and 7b. The sealing body 5 is substantially made of a material selected from the group consisting of a thermosetting resin such as an epoxy resin. Bottom surface of heat spreader 6, first and second leads 1
The bottom surfaces of the foot portions L <b> 3 of 1 and 12 are exposed from the bottom surface of the sealing body 5. The bottom surfaces of the members 6, L3, 5 are arranged on substantially the same horizontal plane (package mounting surface).

The toes of the feet L3 of the first and second leads 11 and 12 can be exposed on the side surface of the sealing body 5. Thereby, when the semiconductor package 10 is mounted, the first and second leads 11, 1
2 can be visually confirmed. However, foot L3
The protruding length d of the toe (see FIG. 4) is 0 to 0.3 m
m, preferably 0.1 to 0.2 mm. Even if a sealing body made of a transparent resin or the like is used instead of this configuration, the first
The joining state of the second leads 11 and 12 can be visually recognized.

FIG. 3 is a sectional view showing the internal structure of the semiconductor chip 2 of the semiconductor package 10. FIG. 4 is a cross-sectional view showing the relationship between the semiconductor chip 2, the heat spreader 6, and the first leads 11.

The chip 2 is formed using, for example, an n-type silicon semiconductor substrate Sub. A p-type base region 42 is formed in the surface of the substrate Sub. p-type base region 4
An n-type source region 43 is formed in the surface of No. 2. In the surface of p-type base region 42, p-type contact region 4 is also provided.
2a is formed. The back side of the substrate Sub where the p-type base region 42 is not formed becomes the n-type drain region 41.

A plurality of trenches 40 are formed vertically downward from the surface of the substrate Sub. The trench 40 penetrates the n-type source region 43 and the p-type base region 42 and reaches a predetermined depth of the drain region 41. That is, the bottom surface of the trench 40 is formed in the drain region 41. On the inner wall of the trench 40, a gate insulating film 44 such as a silicon oxide film formed by thermal oxidation is formed. The gate insulating film 44 is formed substantially up to the opening end of the trench 40. The gate insulating film 44 may be formed somewhat below the main surface of the substrate Sub by the etching process. In the trench 40, a gate electrode 4 made of polysilicon or the like is further covered with a gate insulating film 44.
5 is embedded. An interlayer insulating film 46 is formed on the substrate Sub so as to close the entrance of the trench 40, that is, to cover the tops of the gate electrode 45 and the gate insulating film 44. The interlayer insulating film 46 is made of, for example, BP having a high reflow property.
It is made of a material such as SG, and its surface is flattened by reflow.

The gate electrode 45 is electrically connected to a gate lead electrode 8 made of aluminum or the like formed on the main surface of the substrate Sub. Source electrode 15 made of aluminum or the like is provided on interlayer insulating film 46. Source electrode 15 is electrically connected to n-type source region 43 and p-type contact region 42a through a contact hole formed in interlayer insulating film 46. The source electrode 15
And n-type source region 43 and p-type contact region 42a
And a barrier metal layer such as a TiW film can be interposed between them. On the source electrode 15 and the gate lead-out electrode 8, a passivation film 4 made of a silicon nitride film or the like for covering and protecting the chip 2 is provided. On the other hand, the drain electrode 16 is provided on the back surface of the substrate Sub so as to be electrically connected to the drain region 41.

As described above, the bump contacts 7a, 7b
And the first and second leads 11 and 12 are electrically connected. The heat spreader 6 is electrically connected to the drain electrode 16 via the solder 3. As shown in FIG. 4, the bump contacts 7 a and 7 b are joined to the source electrode 15 and the gate extraction electrode 8 through the openings of the passivation film 4 and protrude above the passivation film 4. Each of the bump contacts 7a and 7b is 0.00
It has a cross-sectional area of 7-0.07 mm ² . First and second
The ends of the bases L1 of the leads 11, 12 extend to the center of the chip 2 beyond the bump contacts 7a, 7b.

FIG. 5 is a flowchart showing a method of manufacturing a semiconductor package according to the first embodiment. FIG.
(A)-(e) is a figure which shows the change of the processed goods in the same manufacturing method in order.

First, a semiconductor wafer W of silicon or the like is prepared. A large number of semiconductor devices having the above-described structure, that is, a large number of portions to be vertical MOS transistors are formed on the wafer W (step S1). Next, bump contacts 7a and 7b made of a conductive material such as Au are respectively formed on portions of the wafer W corresponding to the source electrodes and the gate lead electrodes of many semiconductor devices (step S2: FIG. 6).
(A)). The bump contacts 7a and 7b can be formed by a method using a stud bump bonder, a method using plating, or the like.

Next, the bottom of the wafer W, that is, the drain electrode of the semiconductor device and the disk HS for the heat spreader are joined by soldering (step S3: FIG. 6B). At this time, the solder may be deposited on the back surface of the wafer W in advance, or may be plated on the surface of the heat spreader disk HS. As a form of bonding, for example, bonding at the chip level after dicing can be performed in addition to bonding at the wafer level.

Next, the wafer W is diced together with the heat spreader disk HS. Thereby, a large number of intermediate structures MS in which the semiconductor chip 2 is mounted on the heat spreader 6 via the solder 3 are cut out (step S4: FIG. 6).
(C)).

Next, the intermediate structure MS is bonded to a lead frame which is a material of the first and second leads 11 and 12 (step S5: FIG. 6D). At this time, the chip 2 is turned upside down, that is, the main surface of the chip 2 (the bump contact 7
Face-down bonding is performed with the side on which a and 7b are disposed) facing down. FIG. 7 is a bottom view showing the relationship between the chip 2 and the lead frame 1 that is the material of the first and second leads 11 and 12 during face-down bonding. At this time, as a bonding method, for example, an ultrasonic thermocompression bonding method is used. In this case, for example, a plated PPF (Pre-Plating Lead)
Frame) etc. are used. The plating is made of a material such as Ni / Pd / Au.

Next, with respect to the structure obtained in the above step,
The insulating sealing body 5 is formed by, for example, molding (step S6: FIG. 6E). The material of the sealing body 5 is
For example, it is selected from the group consisting of a thermosetting resin such as an epoxy resin. The semiconductor chip 2, the solder 3, the heat spreader 6, and the first and second leads 11 and 12 are buried and sealed by the sealing body 5 thus formed. In the state after the resin sealing, the bottom surface of the heat spreader 6,
The bottom surfaces of the feet L3 of the first and second leads 11 and 12 are exposed from the bottom surface of the sealing body 5. The bottom surfaces of the members 6, L3, 5 are substantially the same horizontal plane (package mounting surface).
Placed on top.

As described above, in the method of manufacturing the semiconductor package 10 according to the first embodiment, the semiconductor chip 2 is mounted on the heat spreader 6, and then on the lead frame 1 via the bump contacts 7a and 7b. Face down bonding. As a result, it is possible to reduce wiring resistance and thermal resistance, which have been bottlenecks in characteristics in a conventional semiconductor package in which a semiconductor chip is mounted on a lead frame.

In the semiconductor package 10 according to the first embodiment, the terminal portion of the third lead (drain lead) formed by the heat spreader 6 and the first and second leads arranged on one side of the heat spreader 6 are arranged. The terminal portions of the (source lead, gate lead) 11 and 12 are arranged on substantially the same horizontal plane (package mounting surface) on the bottom surface of the sealing body 5. Thus, the size can be significantly reduced as compared with a conventional semiconductor package in which a plurality of leads are taken out from both side surfaces of a resin sealing body. In addition, it is also possible to accommodate multiple high-current semiconductor chips with higher ratings in the same package.
The area efficiency can be improved.

(Second Embodiment) FIG. 8 shows a vertical type MOS.
FIG. 9 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention, in which a power semiconductor chip including a transistor is incorporated. FIG. 9 is a sectional view showing the internal structure of a semiconductor chip in the semiconductor package shown in FIG.

The semiconductor package 50 of this embodiment
Has a power semiconductor chip 2 including a vertical MOS transistor similar to that of the first embodiment. That is, as shown in FIG. 9, a source electrode (including a source lead electrode) 15 and a gate lead electrode 8 are arranged on the upper side of the chip 2. A drain electrode 16 is provided on the bottom side of the chip 2. The semiconductor chip 2 is made of solder (conductive bonding member)
3 and is mounted on a conductive heat spreader 6.

Source electrode 15 and gate lead electrode 8
Bump contacts (conductive bonding members) 27a and 27b made of solder are provided thereon. A Pd layer (or Au layer) 23 / Ni is provided between the bump contacts 27a and 27b and the source electrode 15 and the gate extraction electrode 8.
Metal laminate structure 20 composed of layer 22 / Ti layer 21
Is arranged. When the source electrode 15 and the gate lead-out electrode 8 are made of an aluminum film, usually, direct solder connection is not performed (in some cases, direct connection can be performed). Therefore, by connecting the barrier metal laminated structure 20 between the two, the connection state between the two is improved. The barrier metal layers 21, 22, and 23 are formed by, for example, a vacuum evaporation method or the like. Bump contact 27
a and 27b are joined to the Pd layer and further to the Ni layer beyond this layer.

The bump contacts 27a and 27b have first and second leads 11 and 12 made of conductive strips.
Are respectively joined. Therefore, the first lead 11 is electrically connected to the source electrode 15 via the bump contact 27a. The second lead 12 is electrically connected to the gate electrode lead-out electrode 8 via the bump contact 27b.
Note that the heat spreader 6 functions as a third lead because it is electrically connected to the drain electrode 16 via the solder 3.

The insulating sealing body 5 is formed so as to embed and seal the semiconductor chip 2, the solder 3, the heat spreader 6, the first and second leads 11 and 12, and the bump contacts 27a and 27b. The bottom surface of the heat spreader 6 and the bottom surfaces of the feet L3 of the first and second leads 11 and 12 are exposed from the bottom surface of the sealing body 5. The bottom surfaces of the members 6, L3, 5
They are arranged on substantially the same horizontal plane (package mounting surface).

FIG. 10 is a flowchart showing a method for manufacturing a semiconductor package according to the second embodiment. The change of the processed product in this manufacturing method is the same as that shown in FIGS.

First, a semiconductor wafer W of silicon or the like is prepared. A large number of semiconductor devices having the above-described structure, that is, a large number of portions to be vertical MOS transistors are formed on the wafer W (step S11). Next, the wafer W corresponding to the source electrode and the gate lead electrode of many semiconductor devices
Are formed in this order on the barrier metal layers 21, 22, and 23 (step S12). Barrier metal layers 21, 22, 2
3 can be formed using, for example, a vacuum evaporation method or the like.

Next, bump contacts 27a and 27b made of solder are respectively formed on the barrier metal layer 23 (step S13: FIG. 6A). Bump contact 27a, 2
7b can be formed using, for example, a solder printing method, a solder plating method, a solder ball mounting method, or the like.

Thereafter, as described above, according to steps S3 to S6, soldering, dicing, face-down bonding and molding of the heat spreader disk HS are performed to form the semiconductor package 50 shown in FIGS. 8 and 9. . In the second embodiment, since the bump contacts 27a and 27b are made of solder, the process S
In the five-face-down bonding, for example, a pulse heating method can be used.

Also in the method of manufacturing the semiconductor package 50 according to the second embodiment, it is possible to reduce the wiring resistance and the thermal resistance, which have conventionally been a bottleneck in characteristics. Further, the semiconductor package 5 according to the second embodiment
Even at 0, the package size can be significantly reduced as compared with the related art.

(Third Embodiment) FIG. 11A is a plan view showing a semiconductor package according to a third embodiment of the present invention incorporating a power semiconductor chip including a vertical MOS transistor. . FIG. 11B and FIG.
(A) Cross-sectional view taken along line XIB-XIB in the figure, and XIC-
It is sectional drawing along the XIC line. FIG. 12 is a sectional view showing the internal structure of a semiconductor chip in the semiconductor package shown in FIG.

Semiconductor package 60 of this embodiment
Has a power semiconductor chip 2 including a vertical MOS transistor similar to those of the first and second embodiments. That is, as shown in FIG. 12, a source electrode (including a source lead electrode) 15 and a gate lead electrode 8 are provided on the upper side of the chip 2. A drain electrode 16 is provided on the bottom side of the chip 2. The semiconductor chip 2 is connected to a conductive heat spreader 6 via a solder (conductive bonding member) 3.
Mounted on top.

Source electrode 15 and gate lead electrode 8
Accordingly, a large opening is formed in the passivation film 4 made of a silicon nitride film or the like that covers and protects the chip 2. Bonding members made of solder (conductive bonding members) so as to be connected to the electrodes and protrude upward in these openings.
62a and 62b are provided respectively. The bonding member 62a on the source electrode 15 has a cross-sectional area of 0.2 mm ² or more, which is much larger than a normal bump contact.

The first and second leads 11 and 12 made of a conductive strip are joined to the joining members 62a and 62b, respectively. Therefore, the first lead 11 is electrically connected to the source electrode 15 via the bonding member 62a. The second lead 12 is electrically connected to the gate electrode lead electrode 8 via the joining member 62b. In addition, heat spreader 6
Functions as a third lead because it is electrically connected to the drain electrode 16 via the solder 3.

The semiconductor chip 2, the solder 3, the heat spreader 6, the first and second leads 11, 12 and the joining member 62
The insulating sealing body 5 is formed so as to embed and seal a and 62b. The bottom surface of the heat spreader 6 and the bottom surfaces of the feet L3 of the first and second leads 11 and 12 are exposed from the bottom surface of the sealing body 5. The bottom surfaces of the members 6, L3, 5 are arranged on substantially the same horizontal plane (package mounting surface).

FIG. 13 is a flowchart showing a method of manufacturing a semiconductor package according to the third embodiment.

First, a semiconductor wafer such as silicon is prepared. A large number of semiconductor devices having the above-described structure, that is, a large number of portions to be vertical MOS transistors are formed on a wafer (step S21). At this time, a large opening is formed in the passivation film 4 at a corresponding position where the bonding members 62a and 62b of each semiconductor device are formed.

Next, the bottom of the wafer, ie, the drain electrode of the semiconductor device and the disk for the heat spreader are joined by soldering (step S22). At this time, the solder may be vapor-deposited on the back surface of the wafer in advance, or may be plated on the surface of the heat spreader disk. As a form of bonding, for example, bonding at the chip level after dicing can be performed in addition to bonding at the wafer level.

Next, the wafer is diced together with a heat spreader disk. Thereby, a large number of intermediate structures in which the semiconductor chip 2 is mounted on the heat spreader 6 via the solder 3 are cut out (step S23).

Next, an intermediate structure is joined to a lead frame which is a material of the first and second leads 11 and 12 (step S24). At this time, first, solder as a material of the joining members 62a and 62b is arranged on the lead frame. Next, the chip 2 is turned upside down to perform positioning with respect to the lead frame, and the solder as the material of the joining members 62a and 62b is reflowed. In this way, the face down bonding of the chip 2 is performed on the lead frame.

Next, with respect to the structure obtained in the above step,
The insulating sealing body 5 is formed, for example, by molding (step S25). The semiconductor chip 2, the solder 3, the heat spreader 6, and the first and second leads 11 and 12 are buried and sealed by the sealing body 5 thus formed.

Also in the method of manufacturing the semiconductor package 60 according to the third embodiment, it is possible to reduce the wiring resistance and the thermal resistance, which have been a bottleneck in the conventional characteristics. In addition, since the solder of the joining members 62a and 62b connecting the first and second leads 11 and 12 is directly supplied in the face-down bonding process, the manufacturing method can be simplified as compared with the first embodiment. Can be. Further, also in the semiconductor package 60 according to the third embodiment, the package size can be significantly reduced as compared with the related art.

(Fourth Embodiment) FIG. 14 shows a vertical MO.
FIG. 14 is a cross-sectional view illustrating a semiconductor package according to a fourth embodiment of the present invention in which a power semiconductor chip including an S transistor is incorporated. FIG. 15 is a sectional view showing the internal structure of the semiconductor chip in the semiconductor package shown in FIG.

Semiconductor package 70 of this embodiment
Has a power semiconductor chip 2 including a vertical MOS transistor as in the first to third embodiments. That is, as shown in FIG. 15, a source electrode (including a source lead electrode) 15 and a gate lead electrode 8 are arranged on the upper side of the chip 2. A drain electrode 16 is provided on the bottom side of the chip 2. The semiconductor chip 2 is connected to a conductive heat spreader 6 via a solder (conductive bonding member) 3.
Mounted on top.

Source electrode 15 and gate lead electrode 8
Accordingly, a large opening is formed in the passivation film 4 made of a silicon nitride film or the like that covers and protects the chip 2. Bonding members made of solder (conductive bonding members) so as to be connected to the electrodes and protrude upward in these openings.
72a and 72b are provided respectively. The bonding member 72a on the source electrode 15 has a cross-sectional area of 0.2 mm ² or more, which is much larger than a normal bump contact.

The joining members 72a and 72b and the source electrode 15
A Pd layer (or A)
A barrier metal laminated structure 20 composed of a u layer 23 / Ni layer 22 / Ti layer 21 is provided. When the source electrode 15 and the gate lead-out electrode 8 are made of an aluminum film, usually, direct solder connection is not performed (in some cases, direct connection can be performed). Therefore, by connecting the barrier metal laminated structure 20 between the two, the connection state between the two is improved. Barrier metal layers 21, 22, 23
Is formed by, for example, a vacuum evaporation method. The joining members 72a and 72b join the Pd layer and the Ni layer beyond this layer.

The first and second leads 11 and 12 made of a conductive strip are joined to the joining members 72a and 72b, respectively. Therefore, the first lead 11 is electrically connected to the source electrode 15 via the bonding member 72a. The second lead 12 is electrically connected to the gate electrode lead-out electrode 8 via the joining member 72b. In addition, heat spreader 6
Functions as a third lead because it is electrically connected to the drain electrode 16 via the solder 3.

The semiconductor chip 2, the solder 3, the heat spreader 6, the first and second leads 11, 12 and the joining member 72
An insulating sealing body 5 is formed so as to embed and seal a and 72b. The bottom surface of the heat spreader 6 and the bottom surfaces of the feet L3 of the first and second leads 11 and 12 are exposed from the bottom surface of the sealing body 5. The bottom surfaces of the members 6, L3, 5 are arranged on substantially the same horizontal plane (package mounting surface).

FIG. 16 is a flowchart showing a method of manufacturing a semiconductor package according to the fourth embodiment.

First, a semiconductor wafer W of silicon or the like is prepared. A large number of semiconductor devices having the above-described structure, that is, a large number of portions to be vertical MOS transistors are formed on the wafer W (step S31). At this time, a large opening is formed in the passivation film 4 at a corresponding position where the bonding members 72a and 72b of each semiconductor device are formed. Next, barrier metal layers 21, 22, and 23 are sequentially formed at positions corresponding to the large openings in the passivation film 4 (step S32). The barrier metal layers 21, 22, 23
For example, it can be formed using a vacuum evaporation method or the like.

Thereafter, as described above, steps S22 to S2
5, soldering, dicing, face-down bonding, and molding of the heat spreader disk are performed, and the semiconductor package 7 shown in FIGS.
0 is formed.

Also in the method of manufacturing the semiconductor package 70 according to the fourth embodiment, it is possible to reduce the wiring resistance and the thermal resistance, which have conventionally been a bottleneck in characteristics. In addition, since the solder of the joining members 72a and 72b connecting the first and second leads 11 and 12 is directly supplied in the face-down bonding process, the manufacturing method can be simplified as compared with the second embodiment. Can be. Further, also in the semiconductor package 70 according to the fourth embodiment, the package size can be significantly reduced as compared with the related art.

In the first to fourth embodiments, a vertical MOS transistor has been described as a semiconductor device in a power semiconductor chip. However, this semiconductor device is an IGBT (Insulated Gate Bipolar Transistor).
Other devices may be used.

In addition, in the scope of the concept of the present invention, those skilled in the art can come up with various modified examples and modified examples, and these modified examples and modified examples fall within the scope of the present invention. I understand.

[0070]

As described above, according to the present invention,
The package size can be significantly reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1A is a plan view showing a semiconductor package according to a first embodiment of the present invention in which a power semiconductor chip including a vertical MOS transistor is incorporated, and FIG.
(C) is a cross-sectional view taken along line IB-IB in FIG.
FIG. 2 is a cross-sectional view taken along line IC-IC.

FIGS. 2A and 2B are a bottom view and a side view of a side on which leads are formed, of the semiconductor package shown in FIG. 1A.

FIG. 3 is a sectional view showing an internal structure of a semiconductor chip in the semiconductor package shown in FIG.

FIG. 4 is a cross-sectional view showing a relationship between a semiconductor chip, a heat spreader, and a first lead in the semiconductor package shown in FIG.

FIG. 5 is a flowchart illustrating a method of manufacturing the semiconductor package according to the first embodiment.

6 (a) to 6 (e) are diagrams sequentially showing changes in processed products in the manufacturing method of the flowchart shown in FIG.

FIG. 7 is a bottom view showing a relationship between a chip and a lead frame which is a material of first and second leads during face-down bonding.

FIG. 8 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention incorporating a power semiconductor chip including a vertical MOS transistor.

9 is a cross-sectional view showing an internal structure of a semiconductor chip in the semiconductor package shown in FIG.

FIG. 10 is a flowchart illustrating a method of manufacturing a semiconductor package according to a second embodiment.

11A is a plan view showing a semiconductor package according to a third embodiment of the present invention incorporating a power semiconductor chip including a vertical MOS transistor, and FIG.
11C is a cross-sectional view taken along the line XIB-XIB in FIG. 11A and a cross-sectional view taken along the line XIC-XIC.

FIG. 12 is a sectional view showing an internal structure of a semiconductor chip in the semiconductor package shown in FIG.

FIG. 13 is a flowchart illustrating a method of manufacturing a semiconductor package according to a third embodiment.

FIG. 14 is a sectional view showing a semiconductor package according to a fourth embodiment of the present invention incorporating a power semiconductor chip including a vertical MOS transistor.

15 is a cross-sectional view showing an internal structure of a semiconductor chip in the semiconductor package shown in FIG.

FIG. 16 is a flowchart illustrating a method of manufacturing a semiconductor package according to a fourth embodiment.

17 (a) is a plan view showing a conventional semiconductor package incorporating a power semiconductor chip including a vertical MOS transistor, and FIGS. 17 (b) and (c) are FIG. 17 (a).
FIG. 2 is a sectional view taken along a longitudinal direction and a direction perpendicular to the longitudinal direction of the illustrated semiconductor package.

[Explanation of symbols]

10, 50, 60, 70 ... semiconductor package 2 ... semiconductor chip 3 ... solder (conductive bonding member) 4 ... passivation film 5 ... resin sealing body 6 ... heat spreader 8 ... gate lead electrode 11, 12 ... lead 15 ... source Electrode 16: drain electrode 20: barrier metal laminated structure 7a, 7b, 27a, 27b: bump contact (conductive bonding member) 62a, 62b, 72a, 72b: bonding member (conductive bonding member)

Claims (28)

[Claims] A semiconductor chip including first and second electrodes disposed on an upper side and a third electrode disposed on a bottom side; a heat spreader joined to the third electrode; Conductive first and second leads electrically connected to the first and second electrodes via conductive first and second joining members, respectively, and the first and second leads each have a lower end. Extending laterally at the section and the first of the heat spreaders
Having a foot arranged side by side; and an insulative sealing body that embeds and seals at least a part of the foot of the semiconductor chip, the heat spreader, and the first and second leads. And the bottom surface of the heat spreader and the bottom surfaces of the feet of the first and second leads are exposed from the bottom surface of the sealing body and are disposed on substantially the same plane. A semiconductor package characterized by the above-mentioned. 2. The heat spreader according to claim 1, wherein the heat spreader is conductive and is electrically connected to the third electrode via a conductive third bonding member, and functions as a third lead. The semiconductor package as described. 3. The semiconductor package according to claim 1, wherein the first, second, and third electrodes are electrically connected to a source electrode, a gate electrode, and a drain electrode, respectively. 4. The semiconductor device according to claim 1, wherein the foot portions of all the leads including the first and second leads connected to the upper side of the semiconductor chip are arranged side by side only on the first side of the heat spreader. The semiconductor package according to claim 1. 5. The semiconductor package according to claim 1, wherein the first and second leads are the only terminals that receive the first and second voltages applied to the semiconductor chip, respectively. 6. The semiconductor package according to claim 1, wherein each of the first and second leads is formed by a conductive strip. 7. The heat spreader has a thickness t1, while the conductive strip has a thickness t2, and satisfies a thickness ratio condition of 1 <t1 / t2 ≦ 3. A semiconductor package according to claim 1. 8. The sealer embeds and seals substantially the entire foot of the first and second leads,
The semiconductor package according to claim 1, wherein a toe of the foot is exposed on a side surface of the sealing body. 9. The semiconductor package according to claim 8, wherein the toes of the foot project from the side surface of the sealing body by 0 to 0.3 mm. 10. The semiconductor device according to claim 10, wherein each of the first and second leads includes a base facing the upper side of the semiconductor chip, a leg bent from the base and extending along a side of the semiconductor chip and the heat spreader; 2. The semiconductor package according to claim 1, further comprising: a leg bent from a leg and extending away from the heat spreader. 3. 11. The sealing body includes at least the semiconductor chip, the heat spreader, the entire base and the legs of the first and second leads, and at least the feet of the first and second leads. The semiconductor package according to claim 10, wherein a part of the package is embedded and sealed. 12. The leg according to claim 1, wherein said leg is 90 ° ± 90 ° with respect to said plane.
The semiconductor package according to claim 10, wherein the semiconductor package forms an angle of 10 °. 13. The first and second joining members each include:
The semiconductor package according to claim 1, further comprising a bonding member having a cross-sectional area of 0.007 to 0.07 mm ² . 14. The semiconductor package according to claim 1, wherein at least one of the first and second joining members includes a joining member having a cross-sectional area of 0.2 mm ² or more. 15. The semiconductor package according to claim 1, wherein the sealing body is substantially made of a material selected from the group consisting of a thermosetting resin including an epoxy resin. 16. The semiconductor package according to claim 1, wherein each of said first and second joining members is substantially made of a material selected from the group consisting of gold and solder. 17. A semiconductor device further comprising a barrier metal layer interposed between the first and second electrodes and the first and second joining members, respectively, wherein each of the first and second joining members is substantially made of solder. 17. The semiconductor package according to claim 16, wherein: 18. The semiconductor package according to claim 1, wherein the heat spreader is substantially made of a different material from the first and second leads. 19. A first and second electrode disposed on an upper side,
Bonding a heat spreader to the third electrode of the semiconductor chip including: a third electrode disposed on the bottom side; and electrically conductive first and second bonding members to the first and second electrodes, respectively. Electrically connecting the conductive first and second leads via the first and second leads, wherein each of the first and second leads extends laterally at a lower end and is arranged side by side on the first side of the heat spreader. Having a foot portion, at least a part of the foot portion of the semiconductor chip, the heat spreader, and the first and second leads,
Burying and sealing with an insulative sealing body, wherein the bottom surface of the heat spreader, the bottom surface of the foot of the first and second leads are exposed from the bottom surface of the sealing body, and substantially Being arranged on the same plane. A method for manufacturing a semiconductor package, comprising: 20. Disposing the material of the first and second joining members on the first and second electrodes before electrically connecting the first and second leads and before joining the heat spreader. 20. The method of claim 19, further comprising the step of: 21. The method according to claim 19, wherein the step of electrically connecting the first and second leads is performed by face-down bonding. 22. The method according to claim 22, further comprising, before electrically connecting the first and second leads, arranging a material of the first and second joining members on the first and second leads. 22. The method of manufacturing a semiconductor package according to claim 21, wherein: 23. The heat spreader is conductive.
20. The method according to claim 19, wherein the semiconductor device is electrically connected to the third electrode via a conductive third bonding member to function as a third lead. 24. The method according to claim 24, wherein the first and second leads are part of a lead frame, and the method further comprises connecting the first and second leads to the first and second electrodes, respectively. 20. The method according to claim 19, further comprising a step of separating the first and second leads from the first package. 25. A first and a second electrode disposed on the upper side,
A semiconductor chip including a third electrode disposed on the bottom side; a conductive heat spreader bonded to the third electrode; and the heat spreader connected to the third electrode via a conductive third bonding member. Electrically connected to function as a third lead; and conductive first and second electrodes electrically connected to the first and second electrodes via conductive first and second bonding members, respectively. The second lead and each of the first and second leads is formed by a conductive strip, wherein the heat spreader has a thickness t1, while the conductive strip has a thickness t2, and a thickness ratio Satisfies the condition 1 <t1 / t2 ≦ 3, and each of the first and second leads includes a base facing the upper side of the semiconductor chip, and the semiconductor chip and the heat spreader bent from the base. A leg extending along the side, and a leg bent from the leg and extending away from the heat spreader; and The semiconductor chip, the heat spreader, and the entirety of the base and the legs of the first and second leads, and at least a part of the feet of the first and second leads. An insulating sealing body that embeds and seals the sealing body, wherein the sealing body is substantially made of a material selected from the group consisting of a thermosetting resin including an epoxy resin, and a bottom surface of the heat spreader, A bottom surface of the foot portion of each of the first and second leads is exposed from a bottom surface of the sealing body and is disposed on substantially the same plane. 26. The semiconductor package according to claim 25, wherein the first and second leads are the only terminals that receive the first and second voltages applied to the semiconductor chip, respectively. 27. The semiconductor package according to claim 26, wherein said first, second, and third electrodes are electrically connected to a source electrode, a gate electrode, and a drain electrode, respectively. 28. The sealing body embeds and seals substantially the entirety of the foot of the first and second leads, however, the toes of the foot are provided on the sides of the sealing body. 26. The semiconductor package according to claim 25, which is exposed above.