JP2002358798A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which efficiency of a conduction test can be improved and by which a more detailed test can be performed. SOLUTION: In a test in which the same value is written in a plurality of memory cells and written data is read out again and it is tested whether the data is surely written and read out or not. At the time, as each read out data is simultaneously outputted from each corresponding output terminal, when all output terminals are not connected to a tester, efficiency is low. Then, a data compression circuit is provided in a SDRAM, if all data read out from each output terminal are the same value, an output signal is outputted from one output terminal previously determined, while when at least one data out of data read out from each output terminal is different from the other, it is not required that all output terminals are connected to the tester and an efficient test can be performed by making one output terminal previously determined have a high impedance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for a semiconductor device having a test mode for testing an SDRAM itself before board mounting.

[0002]

2. Description of the Related Art In general, during a test on a semiconductor device, the same value (H level or L level) is written in a plurality of predetermined memory cells, and the written data is read again to accurately write and read. There is something to test. At this time, since each data to be read is simultaneously output from the corresponding output terminal, all the output terminals must be connected to the tester.
The number of connection terminals between the tester and the SDRAM increases. The large number of connection terminals means that the number of SDRAMs that can be tested simultaneously by the tester is small, resulting in poor efficiency.

Therefore, a data compression circuit is provided in the SDRAM, and if all the data read from the respective output terminals have the same value, for example, if the data is all at H level, it is at H level, and if it is all L level, it is at L level. An output signal is output from one predetermined output terminal, and when at least one of the data read from each output terminal has a different content from the others, the predetermined one output terminal is set to a high impedance state. By doing so, it is not necessary to connect all output terminals to the tester, and an efficient test can be performed.

A test performed using this data compression circuit is generally called a data compression test. The data compression circuit used in this data compression test is, for example, in the case of an SDRAM having four output terminals DQ0, DQ1, DQ2, and DQ3, a group of output terminals DQ0 and DQ2 and an output terminal It is divided into DQ1 and DQ3 groups and provided for each group. The data compression circuits of the output terminals DQ0 and DQ2 compress data read from the output terminals DQ0 and DQ2, and output the compressed data from the output terminal DQ0. On the other hand, the data compression circuits of the output terminals DQ1 and DQ3 compress the data read from the output terminals DQ1 and DQ3 and output the compressed data from the output terminal DQ1.

[0005]

By the way, SDRAM
Has a function of masking input / output data with a mask signal. More specifically, the SDR provided with the four input / output terminals DQ0, DQ1, DQ2, and DQ3 described above.
In the case of AM, it is divided into a group of input / output terminals DQ0 and DQ1 and a group of input / output terminals DQ2 and DQ3, which are masked in units of the groups. A mask signal is provided for each group, and a first mask signal φMSK0 is applied to the group of input / output terminals DQ0 and DQ1 for input / output terminals DQ0 and DQ1.
A second mask signal φMSK1 is provided for the group of 2, DQ3.

When the first mask signal φMSK0 is at the H level, the data and output data input to the input / output terminals DQ0 and DQ1 are masked so as not to be input or output. When the first mask signal φMSK0 is at L level, data and output data input to the input / output terminals DQ0 and DQ1 are input and output without being masked.

Similarly, when the second mask signal φMSK1 is at the H level, the data and output data input to the input / output terminals DQ2 and DQ3 are masked so as not to be input or output. When the second mask signal φMSK1 is at the L level, data and output data input to the input / output terminals DQ2 and DQ3 are input and output without being masked.

Therefore, for example, when the first mask signal φMSK0 is L
When the level and the second mask signal φMSK1 are at the H level, the data input to the input / output terminals DQ0 and DQ1 and the output data are not masked, and the input / output terminals DQ2 and DQ3 are masked.

Thus, an SDRA having a mask function is provided.
In M, it is preferable that the data compression test can be performed by operating the mask function. However, as described above, in the data compression test, the group of the output terminals DQ0 and DQ2 and the group of the output terminals DQ1 and DQ3, which are arranged side by side, are data compression targets. In contrast, the mask function
Group of I / O terminals DQ0 and DQ1 arranged in parallel and I / O terminal DQ
Group 2 and DQ3 are masked. Therefore,
In the past, data compression tests could not be performed using the mask function.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to execute a data compression test mode by operating a mask function to improve test efficiency and perform more detailed tests. It is to provide a semiconductor device.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device capable of masking a plurality of input / output data groups by a plurality of mask signals. And a first data compression circuit for compressing a plurality of first output data belonging to the first data input / output terminal group and outputting the compressed data to the outside. First belonging to the input / output terminal group
The gist is that the input / output data is masked. Thus, the first data compression circuit compresses the plurality of first output data belonging to the first data input / output terminal group and outputs the data to the outside. By performing mask control of the first input / output data using the first mask signal, the test efficiency can be improved, and a more detailed test can be performed.

Further, the invention according to claim 2 further comprises a second data compression circuit for compressing a plurality of second output data belonging to the second data input / output terminal group and outputting the compressed data to the outside. In a state where the plurality of second output data are masked by the mask signal of 2, the first data compression circuit compresses the plurality of first output data and outputs the same to the outside. . Accordingly, the apparatus further includes a second data compression circuit for compressing the plurality of second output data belonging to the second data input / output terminal group and outputting the compressed data to the outside.
The plurality of first output data are compressed from the first data compression circuit and output to the outside while the plurality of second output data are masked by the mask signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference Example First, a semiconductor memory device as a semiconductor device according to a reference example of the present invention is shown in FIGS.
It will be described according to.

FIG. 1 shows an SDRA as a semiconductor memory device.
FIG. 2 is a circuit diagram of a test mode entry circuit provided in an M (Synchronous Dynamic Random Access Memory).
In FIG. 1, the test mode entry circuit includes a starter circuit 11 as a power-on detection circuit, a normal operation mode recognition circuit section 12, a test mode recognition circuit section 13, and a test mode determination circuit section 14.

The starter circuit 11, as shown in FIG.
It has an NMOS transistor T1 and three resistors R1 to R3. The resistor R1 and the resistor R2 are connected in series to form a voltage dividing circuit, and the voltage dividing circuit is connected between a power supply line supplied with the external power supply voltage Vcc and a power supply line supplied with the ground voltage. And the divided voltage from the voltage dividing circuit is NMOS
It is supplied to the gate terminal of the transistor T1. NMO
The drain terminal of the S transistor T1 is connected via a resistor R3 to a power supply line to which an external power supply voltage Vcc is supplied. N
The source terminal of the MOS transistor T1 is connected to a power supply line to which a ground voltage is supplied.

Therefore, as shown in FIG. 5, when the external power supply voltage Vcc is applied from the external device to the SDRAM and the external power supply voltage Vcc rises to the reference voltage value, the divided voltage of the voltage dividing circuit becomes relatively high. To rise. Then, when the external power supply voltage Vcc becomes almost half of the reference voltage value,
The NMOS transistor T1 changes from the off state to the on state. That is, the potential of the drain terminal of the NMOS transistor T1 is changed from L level to H level, and subsequently from H level to L level.
Level, and the L level state is maintained thereafter. Then, the potential applied to the drain terminal of the NMOS transistor T1 is output as the power-on signal φon. That is, when the external power supply Vcc is turned on, the starter circuit 11 raises the power supply from the L level to the H level before the external power supply voltage Vcc reaches the reference voltage value, and falls again from the H level to the L level. The input signal φon is supplied to the normal operation mode recognition circuit section 12 and the test mode recognition circuit section 13.
Output to

The normal operation mode recognition circuit section 12 is a circuit for detecting an all precharge (PALL) mode, which is a normal operation mode as the second mode. The normal operation mode recognition circuit unit 12 receives a clock signal CL from an external device.
K, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are input via input terminals, and detection is performed based on the respective signals. Each signal / CS, / RAS, / CA
“/” In S and / WE indicates a signal of negative logic, and the other indicates a signal of positive logic. Then, the normal operation mode recognition circuit unit 1
2, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE based on the clock signal CLK.
From an external device, and a combination of the received signals is a predetermined all-bank precharge (PAL).
L) It is determined whether the combination is a combination of commands.

The PALL command is one of the normal commands output to the SDRAM, and is a command for precharging all the banks. And PAL
After the power is turned on, the L command is issued before an active command issued before a read command, a write command, or the like output from an external device. When the combination of the received signals is a combination of the PALL commands, the normal operation mode recognition circuit unit 12
An H-level normal operation mode detection signal φsx is output as a second mode detection signal indicating that a command has been input from an external device. Also, the normal operation mode recognition circuit section 12 is PALL
When the signal is a combination other than the command, PALL
An L level normal operation mode detection signal φsx indicating that the command is not a command is output.

In this embodiment, when the chip select signal / CS is at L level, the row address strobe signal / RAS is at L level, the column address strobe signal / CAS is at H level and the write enable signal / WE is at L level, P
ALL command.

FIG. 2 is a circuit diagram for explaining the circuit configuration of the normal operation mode recognition circuit section 12. As shown in FIG. In FIG. 2, the normal operation mode recognition circuit unit 12 includes first to fourth latch circuits 21 to 24. First latch circuit 21
Inputs and latches the row address strobe signal / RAS via the inverter circuit 25 and the first gate transistor TG1 including an NMOS transistor. The latched row address strobe signal / RAS is output from the inverter circuit 2
6 to the NAND circuit 27.

The second latch circuit 22 inputs and latches the column address strobe signal / CAS via an inverter circuit 28 and a second gate transistor TG2 comprising an NMOS transistor. The latched column address strobe signal / CAS is input to the NAND circuit 27.

The third latch circuit 23 inputs and latches the write enable signal / WE via an inverter circuit 29 and a third gate transistor TG3 comprising an NMOS transistor. The latched write enable signal / WE
Is input to the NAND circuit 27 via the inverter circuit 29a.

The fourth latch circuit 24 inputs and latches the chip select signal / CS via the inverter circuit 30 and the fourth gate transistor TG4 comprising an NMOS transistor. The latched chip select signal / CS is input to the NAND circuit 27 via the inverter circuit 31.

The NAND circuit 27 receives a signal obtained by inverting the row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a signal obtained by inverting the chip select signal / CS. When all signals are at H level, an L level signal is output. That is, row address strobe signal / RAS, write enable signal
When / WE and the chip select signal / CS are at L level and the column address strobe signal / CAS is at H level (ie, when a PALL command is input from an external device), the NAND circuit 27 outputs an L level signal SG1. . The NAND circuit 27 outputs an H level signal when at least one of the signals is at an L level.

The output signal SG1 of the NAND circuit 27 is inverted via the inverter circuit 32 and output as the normal operation mode detection signal φsx. Therefore, PAL from the external device
When the L command is input, the normal operation mode detection signal φ
sx goes high, and when a command other than the PALL command is input from an external device, the detection signal φsx goes low.

The NOR circuit 33 receives the normal operation mode detection signal φsx and a clock signal CLK from an external device. When the normal operation mode detection signal φsx is at the L level, the NOR circuit 33 inverts the clock signal CLK and outputs the inverted signal to the NOR circuit 34 of the next stage, and also outputs the NOR signal to the NOR circuit 34 via the three inverter circuits 35 to 37. Is output. Therefore, the NOR circuit 34 outputs the clock signal CLK.
Every time rises to the H level, the gate pulse signal GP whose pulse width matches the delay time determined by the three inverter circuits 35 to 37 is output to the gate terminals of the first to fourth gate transistors TG1 to TG4.

Therefore, the first to fourth gate transistors TG
1 to TG4 respond to the gate pulse signal GP in response to the chip select signal / CS, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / W.
E is taken in and latched by the first to fourth latch circuits 21 to 24, respectively.

When the normal operation mode detection signal φsx is at the H level, the NOR circuit 33 does not output the clock signal CLK but always outputs the H level signal. Therefore, the next-stage NOR circuit 34 does not output the gate pulse signal GP.

That is, while a command other than the PALL command is being input from an external device, the normal operation mode recognition circuit section 12 fetches the external command at that time based on the gate pulse signal GP. When a PALL command is input from an external device for the first time, the normal operation mode recognition circuit unit 12 outputs the H level normal operation mode detection signal φsx.
Is output, and subsequent external commands are not fetched. In other words, the normal operation mode recognition circuit unit 12 continues the determination operation until the PALL command is input. When the PALL command is input, the normal operation mode recognition circuit unit 12 outputs the H-level normal operation mode detection signal φsx and performs the recognition operation. To end.

A signal line connecting the fourth gate transistor TG4 and the fourth latch circuit 24 is an NMOS transistor
It is connected to the power supply line to which the ground voltage is supplied via T2. The power-on signal φon from the starter circuit 11 is input to the gate of the NMOS transistor T2. That is, the NMOS transistor T2 is momentarily turned on based on the power-on signal φon which rises to the H level and then falls to the L level when the external power supply Vcc is turned on. This NMO
Fourth latch circuit 24 based on turning on of S transistor T2
Latches the H level. In other words, the external power supply Vc
The latch circuit 24 is initially set so that a signal having the same combination as that of the PALL command is not accidentally latched based on the input of c.

Next, the test mode recognition circuit section 13 will be described. In FIG. 1, a test mode recognition circuit 1
Reference numeral 3 denotes a circuit for detecting a continuity test mode as a first mode. In this embodiment, a chip select signal / CS, a column address strobe signal / CAS and a clock enable signal CKE output from an external device are input. Input via a terminal and detect based on each signal. In this reference example, the chip select signal / CS, the column address strobe signal / CAS and the clock enable signal
When both the CKEs are at the L level, entry into the continuity test mode is assumed.

The column address strobe signal / CAS is 4
NAND circuit 45 through the inverter circuits 41 to 44
Is input to The NAND circuit 45 is a NAND circuit having two input terminals, and the other input terminal is connected to the inverter circuit 41.
Input the column address strobe signal / CAS via the. Therefore, the inverter circuit 46 connected to the output terminal of the NAND circuit 45 outputs the column address strobe signal / C
When AS falls from the H level to the L level, H is delayed for a delay time determined by the three inverter circuits 42 to 44.
The one-shot pulse signal S1 rising to the level is output.

The inverter circuit 46 is connected to the gate of the NMOS transistor T3. Therefore, the NMOS transistor T3 outputs the column address strobe signal / CAS of H level.
When the level falls from the L level to the L level, it is turned on for a delay time determined by the three inverter circuits 42 to 44 based on the one-shot pulse signal S1.

The NMOS transistor T3 is connected to the latch circuit 47
It is connected to the. Then, when the NMOS transistor T3 is turned on (when the column address strobe signal / CAS falls from H level to L level), the signal whose output signal becomes H level is latched. The H level output signal of the latch circuit 47 is output as a detection signal SGX. Then, the H level detection signal SGX is maintained at H level even if the column address strobe signal / CAS rises to H level and falls to L level again to generate the one-shot pulse signal S1.

The output terminal of the latch circuit 47 is an NMOS.
It is connected to a power supply line to which a ground voltage is supplied via a transistor T4. A power-on signal φ from the starter circuit 11 is supplied to the gate terminal of the NMOS transistor T4.
on is input. That is, when the external power supply Vcc is turned on,
The NMOS transistor T4 is momentarily turned on based on the power-on signal φon which rises to the level and then falls to the L level. Based on the turning on of the NMOS transistor T4, the latch circuit 47 latches a signal whose output signal becomes L level. In other words, when the external power supply Vcc is turned on, the latch circuit 47 is initially set.

The detection signal SGX of the latch circuit 47 is output to the NAND circuit 48. The NAND circuit 48 is a NAND circuit having three input terminals. The NAND circuit 48 receives the chip select signal / CS via the inverter circuit 49 in addition to the detection signal SGX, and receives the clock enable signal CKE via the inverter circuit 50. Therefore, the output of the NAND circuit 48 is output when all three input signals are at the H level, that is, when the detection signal SGX
Is at the H level, the chip select signal / CS is at the L level, and the clock enable signal CKE is at the L level. The L-level output signal of the NAND circuit 48 is output to the NOR circuit 72 as a test mode detection signal φ1 as a first mode detection signal.

The detection signal SGX of the latch circuit 47 is
Is output to the NAND circuit 58 via the seven inverter circuits 51 to 57. The NAND circuit 58 is a NAND circuit having two input terminals, and inputs the detection signal SGX to the other input terminal via four inverter circuits 51 to 54. Accordingly, when the detection signal SGX falls from the H level to the L level, the inverter circuit 59 connected to the output terminal of the NAND circuit 58 outputs the three inverter circuits 55 to 57.
Rises to H level for a delay time determined by 1
The shot pulse signal S2 is output.

The detection signal SGX of the latch circuit 47 is
Is output to the NAND circuit 60. The NAND circuit 60
In addition to the detection signal SGX, the column address strobe signal / CAS
Enter The NAND circuit 51 outputs both signals SGX,
When both CAS signals go to the H level, an output signal from the H level to the L level is output. That is, when the column address strobe signal / CAS rises from the L level to the H level after the detection signal SGX at the H level is output from the latch circuit 47, the output of the NAND circuit 60 falls from the H level to the L level.

The output of the NAND circuit 60 is input to the NOR circuit 64 via three inverter circuits 61 to 63.
The NOR circuit 64 is a NOR circuit having two input terminals. The output signal of the NAND circuit 60 is directly input to the other input terminal. Therefore, when the output signal of the NAND circuit 60 falls from the H level to the L level, the NOR circuit 64 outputs a one-shot pulse signal S3 which rises to the H level for a delay time determined by the three inverter circuits 61 to 63.

The one-shot pulse signal S3 is supplied to the latch circuit 6
5 is input to the gate terminal of the NMOS transistor T5 connected to the input terminal of No. 5. And a one-shot pulse signal
When the NMOS transistor T5 is turned on in response to S3, the output of the latch circuit 65 is latched at the H level. An input terminal of the latch circuit 65 has an NMOS transistor T6 which is turned on in response to the power-on signal φon.
Is connected. Therefore, when the NMOS transistor T6 is turned on in response to the power-on signal φon, the content of the output of the latch circuit 65 at the H level is latched.

The output terminal of the latch circuit 65 has an NMOS which is turned on in response to the one-shot pulse signal S2.
The transistor T7 is connected. Therefore, when the NMOS transistor T7 is turned on in response to the one-shot pulse signal S2, the content of which the output of the latch circuit 65 becomes L level is latched.

That is, the output signal SGY of the latch circuit 65
Goes high based on a power-on signal φon at the time of power-on, goes low based on a one-shot pulse signal S2 output subsequently, and outputs a one-shot pulse signal S3 output after the one-shot pulse signal S2. To the H level based on.

The output signal SGY of the latch circuit 65 is 3
NAND circuit 69 via the inverter circuits 66 to 68
Is output to The NAND circuit 69 is a NAND circuit having two input terminals, and the output signal SGY is directly input to the other input terminal. Therefore, when the output signal SGY rises from the L level to the H level, the inverter circuit 70 connected to the output terminal of the NAND circuit 69 rises to the H level for a delay time determined by the three inverter circuits 66 to 68. The pulse signal S4 is output.

The one-shot pulse signal S4 is supplied to the latch circuit 7
The signal is input to the gate terminal of the NMOS transistor T8 connected to the first input terminal. And a one-shot pulse signal
When the NMOS transistor T8 is turned on in response to S4, the output from the latch circuit 71 is latched at the H level. An output terminal of the latch circuit 71 has an NMOS transistor T9 which is turned on in response to the power-on signal φon.
Is connected. Accordingly, when the NMOS transistor T9 is turned on in response to the power-on signal φon, the latch circuit 71 is initially set and latches the content whose output becomes L level.

That is, the output signal of the latch circuit 71 goes low based on the power-on signal φon when the power is turned on, and goes high based on the one-shot pulse signal S4 output thereafter. The H level output signal of latch circuit 71 is output to NOR circuit 72 as continuity test end signal φext.

In other words, the latch circuit 71 outputs the H-level detection signal SGX generated based on the first fall of the column address strobe signal / CAS, and outputs the low-level column signal SGX. An H level continuity test end signal φext is output to the NOR circuit 72 based on the rise of the address strobe signal / CAS. And
The H-level continuity test end signal φext is held until the power-on signal φon is input again and is initially set.

Next, the test mode determination circuit section 14 will be described. The mode determination circuit section 14 includes a NOR circuit 72. The NOR circuit 72 is a NOR circuit having three input terminals, and receives the test mode detection signal φ1, the continuity test end signal φext, and the normal operation mode detection signal φsx from the normal operation mode recognition circuit unit 12. NOR circuit 72
Is at H level when each of the signals φ1, φext, φsx is at L level, and at L level when at least one of the signals φ1, φext, φsx is at H level. The output of NOR circuit 72 is output as test mode signal φts. Then, the test mode signal φts of the NOR circuit 72 becomes H
When it is at the level, the SDRASM enters the continuity test mode, and the continuity test is executed. When the test mode signal φts is at the L level, the continuity test mode is established.

Therefore, as shown in FIG.
The column address strobe signal / CAS, the chip select signal / CS, and the clock enable signal CKE all become H level for the first time after Vcc is input and before the normal operation mode recognition circuit unit 12 determines the PALL command. At this time, the NOR circuit 72 outputs the test mode signal φ of the H level.
Output ts.

Thereafter, the H level continuity test end signal φex
When t is output, the NOR circuit 72 outputs the test mode signal φts from H level to L level. That is, the H level continuity test end signal φext is a signal for ending the continuity test, and the column address strobe signal / CAS is set to L level.
The continuity test is completed by rising from the level to the H level. Moreover, the H level continuity test end signal φext is a power-on signal φo output at power-on.
Since it remains at H level until n is input,
AM does not enter the continuity test mode until the external power supply voltage Vcc is turned off.

Similarly, when H-level normal operation mode detection signal φsx is output, NOR circuit 72 outputs H-level to L-level test mode signal φts. Therefore, also in this case, the continuity test is terminated. In addition, since the normal operation mode detection signal φsx at the H level remains at the H level until the power-on signal φon output at the power-on is input as described above, the SDRAM will continue to operate until the external power supply voltage Vcc is cut off. There is no continuity test mode.

On the other hand, as shown in FIG.
When the normal operation mode recognition circuit unit 12 determines the PALL command after the input of the signal c and before the column address strobe signal / CAS, the chip select signal / CS, and the clock enable signal CKE all become H level for the first time. , Test mode signal φts remains at L level. That is, when the normal operation mode detection signal φsx at the H level is output before the test mode signal φts changes from the H level to the L level, the continuity test mode is not set.

By the way, the test mode signal φts is
It is supplied to each internal circuit for executing a continuity test provided in the SDRAM. FIG. 4 shows an active power supply generating circuit 75 which is one of the internal circuits and generates an active power supply voltage Vss from an external power supply voltage Vcc. The active power supply generation circuit 75 is a circuit that supplies an operation power supply (active power supply voltage Vss) of each internal circuit unit operated in a normal operation.

In FIG. 4, active power supply generating circuit 7
5 has a NOR circuit 76. The NOR circuit 76 receives the test mode signal φts and the normal operation mode detection signal φsx.

Therefore, the output of the inverter circuit 77 connected to the output terminal of the NOR circuit 76 becomes the test mode signal φ.
When both ts and normal operation mode detection signal φsx are at L level,
It becomes L level. The output of the inverter circuit 77 goes high when at least one of the test mode signal φts and the normal operation mode detection signal φsx goes high.

The output signal of the inverter circuit 76 is NMO
It is connected to the S transistor T10. The NMOS transistor T10 has a drain connected to an NMO
The source terminals of the S transistors T11 and T12 are connected, and the drain terminals of the respective NMOS transistors T11 and T12 are connected to the PMOS transistor T1 forming a current mirror circuit.
3, connected to the power supply line to which the external power supply voltage Vcc is supplied via T14. Also, P which constitutes a current mirror circuit
PMOS transistors for the MOS transistors T13 and T14 respectively
Transistors T15 and T16 are connected in parallel, and their PMOS
The gate terminals of the transistors T15 and T16 are connected to the output terminal of the inverter circuit 77.

A gate terminal of one NMOS transistor T11 of the differential amplifying section has a predetermined reference voltage Vref.
Is applied. The drain terminal of the NMOS transistor T11 is connected to the gate terminal of a PMOS transistor T17 constituting an output unit. The source terminal of the PMOS transistor T17 is connected to a power supply line to which the external power supply voltage Vcc is supplied. Also, PMOS transistor
The drain terminal of T17 is connected to the gate terminal of the NMOS transistor T12 and to the power supply line to which the ground voltage is supplied via the resistor R4.

Therefore, when the NMOS transistor T10 is turned on, the NMOS transistors T11 and T12 of the amplifying section operate, and the voltage determined by the on-resistance of the PMOS transistor T17 of the output section and the voltage dividing ratio of the resistor R4 is set as the active power supply voltage Vss. Supply to the circuit. The active power supply voltage Vss is output to the gate terminal of the NMOS transistor T12, is differentially amplified with the reference voltage Vref, and controls the PMOS transistor T17 in the output section. Therefore, the active power supply voltage Vss
Is controlled to have the same value as the reference voltage Vref.

Therefore, the active power supply generating circuit 75
When a PALL command is generated and the normal operation mode detection signal φ
When sx goes to the H level, the active power supply voltage Vss is generated and supplied to each internal circuit in order to perform a normal operation.

When test mode signal φts attains an H level, active power supply generation circuit 75 generates and supplies an active power supply voltage Vss to each internal circuit in order to perform a continuity test operation. That is, even when the continuity test mode is set, the active power supply generation circuit 75 can generate the active power supply voltage Vss.

Next, the features of the SDRAM configured as described above will be described below. (1) The test mode entry circuit provided in the SDRAM uses the column address strobe signal / CAS and the chip select signal / CS in the test mode recognition circuit unit 13.
And three signals of the clock enable signal CKE, ie, 3
A continuity test mode can be entered with a very small number of signal combinations.

Further, after the H-level test mode signal φts is generated after the power is turned on and the continuity test mode is entered, the H-level continuity test end signal φext or the H-level detection signal φsx is output. The test mode is stopped.

That is, the H level continuity test end signal φex
Since the normal operation mode detection signal φsx at t or H level is maintained at the H level until the power is turned off,
The SDRAM does not enter the continuity test mode until the power is turned off. Therefore, even in the continuity test mode in which entry is made by a very small number of combinations of three signals having a high probability of erroneous entry, erroneous entry is surely prevented during normal use.

Moreover, once before normal use, S
Since the DRAM can only be entered into the continuity test mode, it does not hinder normal use.
Before the continuity test mode signal φts becomes H level,
The configuration is such that the continuity test mode is not set when the level normal operation mode detection signal φsx is generated. Therefore, it is possible to immediately shift to the normal operation, and when the device is used normally, the unnecessary continuity test mode is omitted and the normal operation can be smoothly performed.

(2) PAL output from an external device after power-on and prior to other normal commands
The normal operation mode detection signal φsx at the H level is obtained by detecting the L command. Therefore, the probability of entering the continuity test mode can be extremely low, and normal operations based on the PALL command and various commands following the PALL command can be immediately executed.

(3) In the present embodiment, the active power supply generating circuit 75 used in the normal operation can be used also in the continuity test. Therefore,
There is no need to provide an active power supply generating circuit only for the continuity test, and it is possible to suppress an increase in circuit scale.

(Embodiment) Next, the SD before implementing the present invention is described.
An embodiment embodied in a test mode for testing the RAM itself will be described with reference to FIGS.

The present embodiment is different from the reference example in the contents of the first mode in which a test can be performed. Further, in the present embodiment, an example will be described in which a data compression test is executed using a mask function. In FIG. 7, a test mode entry circuit 80 includes a test mode recognition circuit section 80.
a, a normal operation mode recognition circuit section 80b, a test mode determination circuit section 80c, and a starter circuit 80d.

The test mode recognizing circuit section 80a includes a chip select signal / CS, a row address strobe signal / RAS, and a column address strobe signal / RAS from an external device.
CAS, a write enable signal / WE (that is, an external command) and memory address signals A0 to An are input.
Then, the test mode recognition circuit unit 80a determines the combination (command) of each signal of each signal input from the external device.
Is a data compression test mode command. When a command from an external device is in the data compression test mode, a test mode detection signal φ1 is output.

The normal mode recognition circuit section 80b is the same circuit as the normal operation mode recognition circuit section 12 of the above-mentioned reference example.
A normal operation mode detection signal φsx of a level is output.

The test mode recognition circuit 80
a and the normal operation mode recognizing circuit section 80b receive the power-on signal φon from the starter circuit 80d in the same manner as in the above-described reference example, and detect the respective modes after being initially set.

The test mode determination circuit section 80c receives the test mode detection signal φ from the test mode recognition circuit section 80a.
1 and a normal operation mode detection signal φsx from the normal mode recognition circuit unit 80b.

When the test mode detection signal φ1 at the L level is input earlier than the normal operation mode detection signal φsx at the H level, the determination circuit section 80c outputs an H level test mode signal for executing the test mode. Output φts. Further, the determination circuit unit 80c outputs the H level normal operation mode detection signal φs from the L level test mode detection signal φ1.
When x is input first, an L-level test mode signal φts is output to prevent transition to the test mode even if an L-level test mode signal φ1 is input later.

FIG. 8 shows input / output terminals DQ0 and DQ1 of the SDRAM.
FIG. 3 is a main part circuit diagram for explaining an input / output circuit portion leading to FIG. In this embodiment, the SDRAM has a large number (for example, 16 or 32) of input / output terminals.
For convenience of explanation, in the present embodiment, an SDRAM having the four input / output terminals DQ0, DQ1, DQ2, and DQ3 will be described. The input / output circuit connected to the two input / output terminals DQ0 and DQ1 will be described, and the output circuit will be described because the output of the input / output circuit has characteristics. Further, the input / output circuit portions of the other input / output terminals DQ2 and DQ3 are omitted for convenience of explanation.

The input / output terminals DQ read from the memory cells
Output data DC0X and DC0Z output from 0 are input to NOR circuits 81a and 81b, respectively. The output data DC0X and the output data DC0Z are complementary signals. On the other hand, output data DC1X and DC1Z read from the memory cell and output from the input / output terminal DQ1 are input to the NOR circuits 82a and 82b, respectively. The output data DC1X and the output data DC1Z are complementary signals.

Each of the NOR circuits 81a, 81b, 82a, 82
b denotes a NOR circuit having two input terminals, to which a first data mask signal φMSK0 is input in addition to the output data. The first data mask signal φMSK0 is a signal input from an external device, and outputs whether data to be written to a memory cell is input via the input / output terminals DQ0 and DQ1, and data read from the memory cell. It is a signal to determine whether or not.
Then, when the first data mask signal φMSK0 is at the H level,
A mask mode in which data is not input / output via the input / output terminals DQ0 and DQ1 is set. When the first data mask signal φMSK0 is at the L level, input / output of data as usual is performed with the input / output terminals DQ0 and DQ0.
It becomes the non-mask mode performed through Q1.

In the SDRAM, in addition to the first data mask signal φMSK0, although not shown, a second data mask signal φMSK1 is input from an external device from an external device. The second data mask signal φMSK1 is connected to another input / output terminal.
This signal determines whether to input data to be written to the memory cell via DQ2 and DQ3 and whether to output data read from the memory cell. When the second data mask signal φMSK1 is at the H level, a mask mode in which no data is input / output via the input / output terminals DQ2 and DQ3 is set. When the second data mask signal φMSK1 is at the L level, the normal data input A non-mask mode in which output is performed via the input / output terminals DQ2 and DQ3.

Therefore, each of the NOR circuits 81a, 81b, 82
a, 82b connected to the output terminals
3a, 83b, 84a, and 84b output corresponding output data DC0X, DC0Z, DC1X, DC1Z when the first data mask signal φMSK0 is at L level (in a non-mask mode).
Further, each of the inverter circuits 83a, 83b, 84a, 84b
Indicates that when the first data mask signal φMSK0 is at the H level (in the mask mode), the corresponding output data DC0X, DC0Z, DC1
It does not output X and DC1Z, but outputs an H level signal.

The inverter circuits 83a and 83b are connected to an output buffer 86 via transfer gates 85a and 85b, respectively. Transfer gate 8
Reference numerals 5a and 85b each include a PMOS transistor and an NMOS transistor. The test mode signal φts is input to the gates of the PMOS transistors via inverter circuits 87 and 88, respectively. The test mode signal φts is connected to the gates of the NMOS transistors of the transfer gates 85 a and 85 b via an inverter circuit 88.
Enter

When the test mode signal φts is at the H level (in the test mode), the transfer gate 85
a and 85b are turned off. Also, when the test mode signal φts is L
At the time of the level (in the non-test mode), the transfer gates 85a and 85b are turned on.

Therefore, in the non-test mode and the non-mask mode, the inverter circuits 83a and 83b output the output data DC0X and DC0Z to the output buffer 86. or,
In the non-test mode and the mask mode, the inverter circuits 83a and 83b output an H level signal to the output buffer 86.

On the other hand, in the test mode, regardless of the mask mode and the non-mask mode, the inverter circuit 83
The output signals a and 83b are not output to the output buffer 86. The output buffer 86 includes a PMOS transistor T21 and an NMOS transistor T22. The source terminal of the PMOS transistor T21 is connected to the power supply line of the external power supply voltage Vcc, and the drain terminal of the PMOS transistor T21 is connected to the drain terminal of the NMOS transistor T22. The source terminal of the NMOS transistor T22 is connected to a ground voltage power supply line. In addition, PMO
The drain terminals of the S transistor T21 and the NMOS transistor T22 are connected to the input / output terminal DQ0.

The gate terminal of the PMOS transistor T21 is connected to the output terminal of the transfer gate 85a via inverter circuits 86a and 86b. Also, the gate terminal of the NMOS transistor T22
Transfer gate 8 via inverter circuit 86c
5b is connected to the output terminal.

Therefore, when the H level output data DC0X and the L level output data DC0Z are input to the output buffer 86, the PMOS transistor T21 is turned off and the NMOS transistor T22 is turned on, so that the input / output terminal DQ0
Output L-level output data. Incidentally, when the L-level output data DC0X and the H-level output data DC0Z are input, H-level output data is output from the input / output terminal DQ0.

The inverter circuits 84a and 84b are connected to an output buffer 90 via transfer gates 89a and 89b, respectively. The transfer gates 89a and 89b are composed of a PMOS transistor and an NMOS.
The test mode signal φts is input to the gates of the PMOS transistors via inverter circuits 87 and 88, respectively. The test mode signal φts is input to the gates of the NMOS transistors of the transfer gates 85 a and 85 b via the inverter circuit 88. That is, the transfer gate 89
a, 89b are transfer gates 85a, 85
It operates similarly to b.

Therefore, in the non-test mode and the non-mask mode, the inverter circuits 84a and 84b output the output data DC1X and DC1Z to the output buffer 90. or,
In the non-test mode and the mask mode, inverter circuits 84 a and 84 b output an H level signal to output buffer 90.

On the other hand, in the test mode, regardless of the mask mode and the non-mask mode, the inverter circuit 84
The output signals a and 84b are not output to the output buffer 90. The output buffer 90 includes a PMOS transistor T23 and an NMOS transistor T24. The source terminal of the PMOS transistor T23 is connected to the power supply line of the external power supply voltage Vcc, and the drain terminal of the PMOS transistor T23 is connected to the drain terminal of the NMOS transistor T24. The source terminal of the NMOS transistor T24 is connected to a ground voltage power supply line. In addition, PMO
The drain terminals of the S transistor T23 and the NMOS transistor T24 are connected to the input / output terminal DQ1.

The gate terminal of the PMOS transistor T23 is connected to the output terminal of the transfer gate 89a via inverter circuits 90a and 90b. Also, the gate terminal of the NMOS transistor T24
Transfer gate 8 via inverter circuit 90c
9b is connected to the output terminal.

Therefore, when the output data DC1X at the H level and the output data DC1Z at the L level are input to the output buffer 90, the PMOS transistor T23 is turned off and the NMOS transistor T24 is turned on, so that the input / output terminal DQ1
Output L-level output data. Incidentally, when the L level output data DC1X and the H level output data DC1Z are input, the H level output data is output from the input / output terminal DQ1.

The signal lines connecting the output buffer 90 and the transfer gates 89a and 89b are respectively connected to the PM
The power supply line is supplied with the external power supply voltage Vcc via the OS transistors T25 and T26. The gates of the PMOS transistors T25 and T26 receive the test mode signal φts via the inverter circuit 88. When the test mode signal φts is at the H level (during the test mode), the PMOS transistors T25 and T26 are turned on. When the test mode signal φts is at the L level (in the non-test mode), the PMOS transistors T25 and T26 are turned off.

That is, the PMOS transistors T25 and T26 form a clamp circuit for clamping the signal line to the H level in the data compression test mode. A data compression circuit section 91 is provided in the input / output circuit. The data compression circuit section 91 of the present embodiment is significantly different from a conventional data compression circuit section. The data compression circuit unit 91 of the present embodiment is configured such that output data output from two input / output terminals DQ0 and DQ1 among the four input / output terminals DQ0 to DQ3 are all the same (level) or mutually different. Different content (level)
This is a circuit for judging whether or not to output the result to the input / output terminal DQ0. Although not shown, the SDRAM includes:
A data compression circuit is provided for the remaining two input / output terminals DQ2 and DQ3, and whether the output data output from the input / output terminals DQ2 and DQ3 are all the same (level) or different from each other (level) Is determined, and the result of the determination is output to the input / output terminal DQ2.

That is, the data compression circuit 91 of this embodiment
Are input / output terminals DQ0-DQ masked by the first data mask signal φMSK0 and the second data mask signal φMSK1.
The point that it matches the classification of Q3 is a big difference from the conventional data compression circuit.

The data compression circuit 91 includes first and second exclusive NOR circuits (exclusive OR circuits) 92 and 93.
have. The first exclusive NOR circuit 92 receives the output data DC0X and the output data DC1X. Therefore, when both the output data DC0X and the output data DC1X have the same content (level), the first exclusive NOR circuit 92 outputs an L-level signal. By the way, the output data DC0X and the output data DC1X have different contents (levels).
, The first exclusive NOR circuit 92 outputs H
Output level signal.

The second exclusive NOR circuit 93 receives the output data DC0Z and the output data DC1Z. Therefore, when the output data DC0Z and the output data DC1Z have the same content (level), the second exclusive NOR circuit 93 outputs an L-level signal. By the way, the output data DC0Z and the output data DC1Z have different contents (levels).
, The second exclusive NOR circuit 93 outputs H
Output level signal.

First and second exclusive NOR circuits 9
Output signals 2 and 93 are output to a NOR circuit 95. That is, based on the output data DC0X, DC0Z, the input / output terminal DQ0
And the output data output to the input / output terminal DQ1 based on the output data DC1X and DC1Z have the same content (level), the output signal SG of the NOR circuit 95
3 becomes H level.

On the other hand, the output data output to the input / output terminal DQ0 and the output data output to the input / output terminal DQ1 are:
When the content (level) is not the same, the output signal of the NOR circuit 95
SG3 goes to L level.

The output signal SG3 of the NOR circuit 95 is output to the first and second NOR circuits 96a and 96b. First and second NOR circuits 96a and 96b receive the output signal SG3 and the first data mask signal φMSK0.

Therefore, the inverter circuit 97 connected to the output terminal of the first NOR circuit 96a outputs the output signal SG3 of the NOR circuit 95 when the first data mask signal φMSK0 is at the L level (in the non-mask mode). I do. When the first data mask signal φMSK0 is at the H level (in the mask mode), the inverter circuit 97 outputs the output signal of the NOR circuit 95.
H level signal is output without outputting SG3.

When the first data mask signal φMSK0 is at L level (in a non-mask mode), the second NOR circuit 96b outputs a signal obtained by inverting the output signal SG3. or,
When the first data mask signal φMSK0 is at the H level (in the mask mode), the second NOR circuit 96b does not output a signal obtained by inverting the output signal SG1, but outputs a signal at the L level.

That is, in the non-mask mode, the output data output to the input / output terminal DQ0 does not match the output data output to the input / output terminal DQ1 (level).
, The inverter circuit 97 outputs an L-level signal,
The second NOR circuit 96b outputs an H level signal to the first and second transfer gates 98a and 98b, respectively.

In the non-mask mode, when the output data output to the input / output terminal DQ0 and the output data output to the input / output terminal DQ1 have the same content (level), the inverter circuit 97 operates as follows. The second NOR circuit 96b outputs the H-level signal to the first and second L-level signals, respectively.
Output to transfer gates 98a and 98b.

On the other hand, in the mask mode, the NOR circuit 95
Irrespective of the output signal SG3 of the first and second transfer gates 98a and 98, the inverter circuit 97 outputs an H level signal and the second NOR circuit 96b outputs an L level signal.
8b.

The first and second transfer gates 98a and 98b as a gate circuit are composed of a PMOS transistor and an NMOS transistor.
The test mode signal φts is input to the gate of the transistor via an inverter circuit 88. The test mode signal φts is input to the gates of the NMOS transistors of the first and second transfer gates 98a and 98b via inverter circuits 87 and 88.

When the test mode signal φts is at the H level (during the test mode), the first and second transfer gates 98a and 98b are turned on. When the test mode signal φts is at the L level (in the non-test mode), the first
And the second transfer gates 98a and 98b are turned off.

Therefore, in the test mode, the output signal of the inverter circuit 97 is output to the inverter circuit 86b of the output buffer 86, and the output signal of the second NOR circuit 96b is output to the inverter circuit 86b of the output buffer 86. At this time, the transfer gate circuits 85a, 85b,
89a and 89b are off.

On the other hand, in the non-test mode, the output signals of the inverter circuit 97 and the second NOR circuit 96b are not output to the output buffer 86. At this time, the transfer gate circuits 85a, 85b, 89a, 89b are on.

As described above, for example, when the second data mask signal φMSK1 is at the H level (in the mask mode) and the first data mask signal φMSK0 is at the L level (the non-mask mode), the H level test mode signal φts is generated, and the data compression test mode is executed. Then, H-level write data is input from the external device to the input / output terminals DQ0 and DQ1, respectively, and written to the memory cell at a predetermined address.

Subsequently, when the data written to the predetermined address is read out again from the input / output terminals DQ0 and DQ1, the test mode signal φts at the H level is output, so that the transfer gates 85a, 85b, 89a and 89b are turned on. The first and second transfer gates 9 are turned off.
8a and 98b are turned on. That is, the compressed data from the data compression circuit section 91 is output.

Therefore, the output data DC0X and the output data DC1X
Are the same (output data DC0Z and output data DC1Z
The H level output signal is output to the output buffer 86 via the first transfer gate 98a, and the L level output signal is output to the output buffer 86 via the second transfer gate 98b. Therefore,
An L level match signal is output from the input / output terminal DQ0.

At this time, when the contents of output data DC0X and output data DC1X do not match each other (output data DC0X).
When the contents of 0Z and the output data DC1Z do not match), the output buffer 8 is transferred via the first transfer gate 98a.
An output signal of L level is output to 6. Further, the output buffer 86 is supplied with H level through the second transfer gate 98b.
A level output signal is output. Therefore, the input / output terminals DQ
A mismatch signal of 0 to H level is output.

In other words, the data compression test mode for the input / output terminals DQ0 and DQ1 can be performed in a state where the mask function, which cannot be performed conventionally, is operated (a state where the input / output terminals DQ2 and DQ3 are masked). Become. Therefore, the number of terminals that the tester must connect to the SDRAM for the test can be reduced, and the number of SDRAMs tested simultaneously by the tester can be increased by the reduced number of terminals.

Next, the features of the SDRAM configured as described above will be described below. (1) The test mode entry circuit 80 provided in the SDRAM is used in the test mode recognition circuit 80a.
A data compression test mode using the mask function can be entered.

Further, similarly to the reference example, the SDRAM may only be entered into the data compression test mode once before normal use, so that there is no obstacle to normal use.

When the normal operation mode detection signal φsx at the H level is generated before the test mode signal φts attains the H level, the data compression test mode in which the mask function is activated is not set. Therefore, it is possible to immediately shift to the normal operation, and to use the device normally, the unnecessary data compression test mode is omitted, and the normal operation can be performed smoothly.

(2) PAL output from an external device after power-on and prior to other normal commands
The L command is determined, and the H level detection signal φsx is obtained. Therefore, a normal operation based on the PALL command and various subsequent commands can be immediately executed without entering the test mode.

(3) Further, in the present embodiment, when testing the SDRAM before shipment, the data compression test mode can be executed by using the mask function which could not be performed conventionally. did. This allows
The efficiency of the test can be improved, and a more precise test can be performed, so that a highly accurate SDRAM can be shipped.

The embodiments of the present invention are not limited to the above reference examples and embodiments, but may be implemented as follows. In the reference example and the embodiment, when the PALL command is generated, the H-level detection signal φsx is obtained. However, the present invention is not limited to this, and various types of normal commands such as a single bank precharge command, a bank active command, a mode register set command, a refresh command, a read command, and a write command may be used. Good.
In particular, a command output sooner after the power is turned on is more effective.

In the reference example and the embodiment, the normal operation mode recognition circuit section 12 has been described as being provided only for the test mode. However, the detection signal φsx is output from the command decoder provided in the SDRAM. It may be obtained.

In the reference example, the continuity test mode is entered by a combination of the three signals of the column address strobe signal / CAS, the chip select signal / CS, and the clock enable signal CKE. This is done by entering the continuity test mode with a combination of a part of the three signals and a signal other than the three, or by entering the continuity test mode with a combination of a signal other than four. Is also good. In the case of four or more combinations, the smaller the number is, the more convenient the actual continuity test is.

In the reference example, the continuity test mode is entered by combining three signals. This may be a combination of two or four or more signals. Of course, the continuity test mode may be entered with one signal.

In the reference example, the active power supply generating circuit 75 provided for generating the active power supply Vss for normal operation is configured to be used at the time of the continuity test. May be provided and provided.

In the above reference example and embodiment, the SDR
Although the present invention has been embodied in AM, if there is a device having a first mode in which a test can be performed and a second mode in which other operations are performed, the present invention is embodied in other semiconductor memory devices and semiconductor devices other than semiconductor memory devices. You may.

The test in the first mode is not limited to the continuity test shown in the above reference example and the data compression test shown in the embodiment, but may be any test that is not performed during normal operation.

[0123]

According to the present invention, the data compression test mode can be executed by operating the mask function, so that the test efficiency can be improved and more detailed tests can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a test mode entry circuit.

FIG. 2 is a circuit diagram of a normal operation mode recognition circuit unit;

FIG. 3 is a circuit diagram of a starter circuit.

FIG. 4 is a circuit diagram of an active power generation circuit.

FIG. 5 is an operation waveform diagram when a continuity test mode signal is generated;

FIG. 6 is an operation waveform diagram when a continuity test mode signal is not generated;

FIG. 7 is a block circuit diagram for explaining a test mode entry circuit according to the embodiment;

FIG. 8 is a main part circuit diagram for explaining an input / output circuit part of the embodiment.

[Explanation of symbols]

 11, 80d Starter circuit 12, 80b Normal operation mode recognition circuit 13, 80a Test mode recognition circuit 14, 80c Test mode determination circuit 75 Active power generation circuit 80 Test mode entry circuit 98a First transfer gate circuit 98b Second transfer Gate circuit φts Test mode signal φ1 Test mode detection signal φsx Normal operation mode detection signal φMSK0 First data mask signal φMSK1 Second data mask signal

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2G132 AA00 AA08 AB01 AC04 AD06 AD15 AG01 AG03 AH02 AK07 AK08 AK15 AK21 AL09 AL11 4M106 AA01 AA02 AA04 AA08 AC01 CA26 5L106 AA01 AA15 DD02 DD11 5M024 AA09 BB30 BB20 BB30 BB30 BB20 BB30 BB33 MM10 PP01 PP02 PP03 PP07

Claims (2)

[Claims] 1. A semiconductor device capable of masking a plurality of input / output data groups by a plurality of mask signals, comprising: a plurality of data input / output terminal groups; and a plurality of first outputs belonging to the first data input / output terminal group. A first data compression circuit for compressing the data and outputting the compressed data to the outside, wherein the first mask signal mask-controls first input / output data belonging to the first data input / output terminal group. Semiconductor device. And a second output unit that compresses a plurality of second output data belonging to the second data input / output terminal group and outputs the compressed data to the outside.
Wherein the first data compression circuit compresses the plurality of first output data in a state where the plurality of second output data are masked by the second mask signal. 2. The semiconductor device according to claim 1, wherein the signal is output to the outside.