JP2002358724A - Data reproduction apparatus and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce data read errors due to the offset of read signals. SOLUTION: A data reproducing device uses a level determining unit 10 provided with: a differentiation circuit 12 for obtaining a second order differential V(t) of an output signal V(t) outputted from an AGC 82; an arithmetic circuit (14) for obtaining a time difference between the first intersection Pz0 (time Tz0) of the output signal V(t) and a slice level Vr, and the second intersection Pz2 (time Tz2) of the second order differential V"(t) and a zero level detected in a zero cross detection circuit 84; a comparator circuit (14) for comparing the length of the obtained time difference and prescribed time; and a control means (14) for changing the convergence speed of the error of the amplitude of the output signal V(t) of the AGC(automatic gain control) 82 and a prescribed amplitude value, and the convergence speed of the error of a frequency obtained by the cycle of a time cell set by a PLL 88 and the frequency of the output signal V(t) corresponding to the comparison result of the comparator circuit (14).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for reproducing data recorded on a data recording medium, and more particularly, to a method for reproducing a read signal according to an offset of the read signal read from the data recording medium. The present invention relates to a reproducing apparatus and a reproducing method for changing a convergence speed of an amplitude or frequency error.

[0002]

2. Description of the Related Art HD (magnetic disk), DVD (digital video disk or Digital Versatile Disc), MO (magneto-optical disk), CD (compact disk), There are media such as LD (laser disk). FIG. 5A shows the media 72.
1 shows an outline of a data reproducing apparatus 70 for reproducing data from. A read signal read from the medium 72 is binarized by a level determiner 74, and a bit string composed of “0” and “1”
(Hereinafter referred to as binary data). The binary data is sent to the decoder 76 and reproduced. In the medium 72, for example, as shown in FIG. 5B, a sync mark (Sync) for synchronization, an address mark (AM) and data (DATA)
Is recorded.

FIG. 5C shows an example of the configuration of a level determiner 74. The read signal read from the medium 72 is kept at a constant amplitude by an automatic gain control circuit (hereinafter, referred to as AGC) 82. The AGC output signal V (t) kept at a constant amplitude is sent to the zero cross detection circuit 84. The zero-cross detection circuit 84, for example, as shown in FIG.
A threshold level (hereinafter referred to as a slice level) Vr is set based on the maximum value and the minimum value of the read signal V (t), and a first intersection (Pz) of the output signal V (t) and the slice level Vr is set.
0-1,2,3,4) is detected. The zero-cross detection circuit 84
The detection signal Z0 of the first intersection is sent to the binarization circuit 86.
The binarization circuit 86 includes a phase locked loop circuit (hereinafter, PLL).
A time cell having a cycle determined by the frequency of the output signal V (t) is set at 88, and the first intersections Pz0-1, 2, 3, 4 (time Tz0-1, Binary data is generated based on the presence or absence of (2,3,4).

The AGC 82 keeps the amplitude of the output signal V (t) at a predetermined amplitude value Ao even if the amplitude of the input signal fluctuates. The amplitude is controlled by a voltage αVca (α is a constant) proportional to an error between the amplitude of the output signal V (t) and the predetermined amplitude value Ao. α is the voltage V
It can be adjusted by changing the gain of the amplifier that amplifies ca.
Hereinafter, α is referred to as the feedback gain of the AGC 82.

[0005] The PLL 88 sets a time cell having a period determined by the frequency of the output signal V (t). The cycle is controlled by a voltage βVcp (β is a constant) proportional to an error between the frequency of the output signal V (t) and the frequency of the time cell (the reciprocal of the cycle). β can be adjusted by changing the gain of the amplifier that amplifies the voltage Vcp. Hereinafter, β is referred to as a feedback gain of the PLL 88.

When the feedback gains α and β of the AGC 82 and the PLL 88 are both set to large values, the error is greatly amplified and the sensitivity to the error is increased, so that the error convergence speed is increased. Conversely, if the feedback gains α and β are set to small values,
The error is not amplified so much and the sensitivity to the error is low, so that the error convergence speed is low.

Generally, at the beginning of the operation of the AGC 82 and the PLL 88, the feedback gains α and β are increased to rapidly converge the error. When the error converges and the operation becomes stable, the feedback gains α and β are reduced to prevent malfunction due to disturbance. AG
Switching of the feedback gains α and β of C82 and PLL 88 is performed by signals AGC-H / L and PLL-H / L from the timer circuit 80, respectively. The timer circuit 80 instructs to operate with a high feedback gain at the beginning of the operation, and instructs to operate with a low feedback gain after a predetermined time has elapsed. The feedback gain at the high setting and the low setting differs by several times to several hundred times, and the convergence speed of the error is proportional to the feedback gain.

For example, as shown by a dashed line in FIG.
The error is rapidly converged by setting the feedback gain high (High), and then the feedback gain is set low (Low). However, for example, the feedback gain is set from a high setting (High) to a low setting (Lo).
When noise occurs immediately before switching to w), the error gradually converges at a low feedback gain as shown by the solid line in FIG. Since the convergence of the error is slow, there is a possibility that the convergence of the error may not be completed before the reading of the address mark (AM). If the error has not converged, the address mark cannot be read, and the data cannot be read in some cases.

Even if noise indicated by a solid line in FIG. 7A is generated, the error can be converged before the address mark is read out, for example, as shown in FIG.
By repeatedly recording marks and address marks,
There is also a data recording format in which a margin is provided for an error convergence time. However, since the sync mark and the address mark are recorded redundantly, the recording capacity is wasted.

When an MR (magnetic resistance) head is used as a read / write head of a hard disk, if the MR head contacts the surface of the magnetic disk and generates heat, the heat generated changes the magnetic resistance. The change in magnetic resistance causes thermal
Noise called asperity (Thermal Asperity) occurs. The thermal asperity can be approximated by et-τ ^{/ τ} (τ is a constant) as shown by the dotted line in FIG. Thermal asperity causes an error at the intersection of the output signal V (t) and the slice level Vr.

[0011] The thermal asperity is determined by the generated MR.
Since the head continues until the temperature returns to the original temperature, the time until the error converges is long. As shown in FIG. 5C, when the read signal is binarized, the level determiner 74 performs ECC (Error Correlation).
recting Code) is generated and sent to the decoder 76. The decoder 76 corrects the error of the binary data by ECC in the error correction circuit 78. However, the error convergence time due to thermal asperity often exceeds the time when ECC can be applied, and error correction using ECC cannot be performed.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to reduce a data read error due to a read signal offset.

[0013]

A data reproducing apparatus according to the present invention comprises a differentiating circuit for obtaining a second derivative of an output signal output from an AGC, an output signal detected by a zero-cross detecting circuit, and a slice level. At the first intersection Pz0 (time Tz
0), an arithmetic circuit for calculating the time difference between the second intersection Pz2 (time Tz2) of the second derivative of the output signal and the zero level, a comparison circuit for comparing the calculated time difference with a predetermined time,
The convergence speed of the error between the amplitude of the output signal of the AGC and the predetermined amplitude value is set in accordance with the comparison result of the comparison circuit, and the error between the frequency obtained by the period of the time cell set by the PLL and the frequency of the read signal. And control means for changing the setting of the convergence speed.

According to the data reproducing method of the present invention, a step of obtaining a second derivative of the output signal output from the AGC, a step of detecting a second intersection Pz2 between the second derivative of the output signal and the zero level, Determining a time difference between a first intersection Pz0 between the output signal and the slice level and the detected intersection Pz2; comparing the determined time difference with a predetermined time; and comparing the time difference with a predetermined time The convergence speed of the error between the amplitude of the read signal for obtaining the first and second intersections and the predetermined amplitude value, and the error between the frequency obtained by the period of the time cell set by the PLL and the frequency of the read signal. Changing the convergence speed of.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a data reproducing apparatus and a reproducing method according to the present invention will be described in detail with reference to the drawings. As shown in FIG. 1A, a level determiner 10 for binarizing a read signal read from the medium 72.
The following describes an example of a data reproducing device 20 including a decoder 22 for decoding binary data. Level determiner 1
0 is an automatic gain control circuit (hereinafter referred to as AGC) 82 for keeping the amplitude of the read signal at a predetermined value, as shown in FIG.
And a first crossing point Pz0 between an output signal V (t) output from the AGC 82 and a predetermined threshold level (hereinafter, referred to as a slice level) Vr.
And a phase locked loop circuit (hereinafter referred to as P) for setting a time cell having a period determined by the frequency of the output signal V (t).
LL) 88 and the intersection Pz in each time cell.
Binarization circuit 2 for generating binary data based on the presence or absence of 0
6 is included.

The level determiner 10 includes a differentiating circuit 12 for obtaining a second derivative V "(t) of the output signal V (t) output from the AGC 82, and an operation / comparison circuit 14. The second derivative V ″ (t) of the output signal V (t) is sent to the zero-cross detection circuit 84. Zero cross detection circuit 84
Is the second intersection P between the second derivative V "(t) and the zero level
Detect z2. When the intersection Pz2 is detected, the detection signal Z
2 is sent to the operation / comparison circuit 14. The detection signal Z0 of the intersection Pz0 between the output signal V (t) and the slice level Vr is also sent from the zero-cross detection circuit 84 to the calculation / comparison circuit 14.

The operation / comparison circuit 14, for example, as shown in FIG. 2 (b), generates a time difference ΔT (=) between the intersection Pz0 (time Tz0) and the intersection Pz2 (time Tz2) detected by the zero-cross detection circuit 84. | Tz0−Tz2 |), a comparison circuit for comparing the length of the obtained time difference ΔT with the predetermined time dT, and the amplitude and the predetermined amplitude value of the output signal V (t) of the AGC 82 according to the comparison result. Setting the convergence speed of the error with Ao,
It functions as control means for changing the setting of the convergence speed of the error between the frequency determined by the time cell cycle set by the LL 88 and the frequency of the output signal V (t).

Here, the second derivative V "(t) in FIG. 2 (b) is shown assuming that the slice level Vr is a zero level. As in the conventional case, the output signal V (t) of the AGC 82 is shown. The convergence speed of the error between the amplitude and the predetermined amplitude value Ao can be changed by the feedback gain α of the AGC 82, and the frequency and the output signal V obtained by the period of the time cell set by the PLL 88.
The convergence speed of the error with the frequency of (t) can be changed by the feedback gain β of the PLL 88.

The operation / comparison circuit 14 detects the occurrence and convergence of the offset of the read signal based on the result of the comparison between the time difference ΔT and the predetermined time dT. The occurrence of the offset and the detection of the convergence are performed, for example, based on the comparison result of this time and the comparison results of the past two times. The operation / amplification circuit 14 includes a memory (not shown) for storing the results of the past two comparisons. If all the comparison results of this time and the past two times are ΔT = | Tz0−Tz2 |> dT, it is determined that an offset has occurred. If two or more comparison results of the current comparison result and the past two comparison results are ΔT = | Tz0−Tz2 | <dT, it is determined that the offset has converged.

Here, the predetermined time dT is, for example, PLL8.
8 is set based on the fluctuation value of the time difference ΔT expected to malfunction. The PLL 88 has a value D having a time difference ΔT.
Even if it fluctuates below, the period of the time cell can be set while following the frequency fluctuation of the output signal V (t). However, if the time difference ΔT fluctuates beyond a certain value D, the PLL 88 malfunctions. The predetermined time dT can be set to, for example, a value D.

When the occurrence or convergence of the offset is detected, the operation / comparison circuit 14 instructs to change the feedback gain α of the AGC 82 and / or the feedback gain β of the PLL 88. AG
The feedback gain α of C82 is calculated by the AGC
It is controlled by the signal AGC-H / L sent to the control signal. PLL88
Is controlled by a signal PLL-H / L sent from the operation and comparison circuit 14 to the PLL 88.

The arithmetic / comparison circuit 14 sets the feedback gain of the AGC 82 to a high gain (first gain) at the start of input of the read signal, and detects the convergence of the offset while the AGC 82 is operating at the high feedback gain. Then, the first in AGC82
It instructs to operate with a feedback gain lower than the gain, and instructs the PLL 88 to operate with a high feedback gain (second gain). Further, after a predetermined time TR elapses after switching the feedback gain of the PLL 88 to the high feedback gain, the PLL 8
8 is instructed to operate with a feedback gain lower than the second gain. Here, the predetermined time TR is set in accordance with the time required for the PLL 88 to synchronize the frequency obtained by the cycle of the time cell with the frequency of the output signal V (t). Within a predetermined time TR, PLL 88 completes synchronizing the frequency determined by the time cell period with the frequency of output signal V (t).

The operation / comparison circuit 14 comprises an AGC 82 and a P
When the convergence of the offset generated while the LL 88 is operating at the low feedback gain (third gain and fourth gain) is detected, the PLL 88 is instructed to operate at a feedback gain higher than the fourth gain. Further, after a predetermined time TR elapses after switching the feedback gain of the PLL 88 to the high feedback gain, the PLL 88 is instructed to operate at the low feedback gain (fifth gain).

The operation / comparison circuit 14 includes an AGC 82 and a P
When an offset occurs while the LL 88 is operating at a low feedback gain (third gain and fourth gain), a signal VAL indicating that the binary data is invalid is sent to the binarization circuit 26. . When the AGC 82 and the PLL 88 are operating at a low feedback gain, for example, when thermal asperity occurs, the amplitude and frequency become abnormal values. Since the signal VAL indicates that the read signal is in an abnormal state, it can be used as error position information. The decoder 22 performs error correction of binary data by combining the ECC and the signal VAL.

The AGC 82 sends a signal CZ2 for invalidating the detection of the intersection Pz2 to the zero-cross detection circuit 84 based on the waveform of the read signal. For example, the peak of the read signal
The intersections other than the intersection Pz2 detected near the intermediate level of the peak value are invalidated.

Next, the operation of data reproduction using such a data reproduction apparatus will be described.

The amplitude of the read signal read from the medium 72 is adjusted to a predetermined amplitude value Ao by the AGC 82, and the intersection Pz0 between the output signal V (t) and the slice level Vr is set to zero.
A time cell having a period determined by the cross detection circuit 84 and determined by the frequency of the output signal V (t) is set by the PLL 88, and the binarization circuit 26 sets the intersection P in each time cell.
Binary data is generated based on the presence or absence of z0.

The present invention changes the feedback gains α and β of the AGC 82 and the PLL 88 according to the occurrence or convergence of the offset of the read signal. FIG. 3 shows an example of a procedure for detecting occurrence or convergence of an offset. The occurrence and convergence of the offset depends on the intersection P between the output signal V (t) and the slice level Vr.
It is detected based on a deviation between z0 (time Tz0) and an intersection Pz2 (time Tz2) between the second-order derivative V "(t) of the output signal V (t) and the zero level.

The output signal V (t) output from the AGC 82
Is obtained by the differentiating circuit 12. An intersection Pz2 between the obtained second differential V "(t) and the zero level is detected by the zero-cross detecting circuit 84. The AGC 82 generates a signal C that invalidates the detection of the intersection Pz2 based on the waveform of the read signal.
Z2 is sent to the zero-cross detection circuit 84. With the signal CZ2, for example, the intersection Pz2 detected in a noise portion generated near the peak of the output signal V (t) can be invalidated.

The time difference ΔT between the intersection Pz0 (time Tz0) and the intersection Pz2 (time Tz2) is obtained by the calculation / comparison circuit 14 (S1).
Ten). The calculated and compared circuit 14 compares the calculated time difference ΔT with the predetermined time dT (S112). If ΔT = | Tz0−Tz2 | <dT, ER (n) = 0 is set (S114). If ΔT = | Tz0−Tz2 |> dT, ER (n) = 1 is set (S116). Here, ER (n) represents the result of this comparison. For example, ER (n-1) indicates the comparison result of one time before, and ER (n-2) indicates the comparison result of two times before.

The operation / comparison circuit 14 calculates the current comparison result ER
(n) and the past two comparison results ER (n-1) and ER (n-2)
Detection of occurrence and convergence of the offset of the read signal is performed. If all the comparison results are “1” (S118), it is determined that an offset has occurred (S120). Two or more comparison results are "0"
(S122), it is determined that the offset has converged (S12
Four).

When occurrence or convergence of the offset is detected, the operation / comparison circuit 14 changes the feedback gain α of the AGC 82 and / or the feedback gain β of the PLL 88. AGC82
FIG. 4 shows a procedure for changing the feedback gains α and β of the PLL 88 and the PLL 88.

At the beginning of data reproduction, the feedback gain of the AGC 82 is set to a high gain (first gain) in order to quickly adjust the amplitude of the read signal to the predetermined amplitude value Ao (S130). P
LL88 is set to low feedback gain, binary data is valid
(valid). When the convergence of the offset is detected while the AGC 82 is operating at a high feedback gain (S132), the arithmetic and comparison circuit 14 instructs the AGC 82 to operate at a feedback gain lower than the first gain (S134). . A at this time
The amplitude of the output signal V (t) output from the GC 82 is stable.

After the amplitude of the output signal V (t) is stabilized, PL
In order to synchronize the frequency determined by the period of the time cell set by L88 with the frequency of the output signal V (t) in a short time, the operation and comparison circuit 14 operates the PLL 88 with a high feedback gain (second gain). Instruct (S134). Calculation·
The comparison circuit 14 instructs the PLL 88 to operate with a feedback gain lower than the second gain after a lapse of a predetermined time TR after switching the feedback gain of the PLL 88 to the high gain (S136) (S13).
8). At this time, the frequency determined by the cycle of the time cell set by the PLL 88 is synchronized with the frequency of the read signal.

If the occurrence of an offset is detected in a state where both the AGC 82 and the PLL 88 are operating at low feedback gains (third and fourth gains) (S142), the operation
The binary data is invalid from the comparison circuit 14 to the binarization circuit 26 (i
nvalid) is transmitted (S144). 2
The value conversion circuit 26 outputs the ECC and the signal VAL together with the binary data.
To the decoder 22. The decoder 22 receives the ECC and the signal
Using the VAL, the error correction circuit 24 corrects the error of the binary data.

The ECC may obtain a maximum of n error positions and a maximum of n error patterns, or may obtain a maximum of 2n error patterns, depending on the solution of the 2n-order error polynomial. By using the signal VAL as the error position information, the data length for which error correction can be performed is twice as long as the conventional one. Error correction of a long-lasting offset such as thermal asperity becomes possible.

When the convergence of the offset generated while the AGC 82 and the PLL 88 are operating at the low feedback gains (third and fourth gains) is detected (S132), the operation / comparison circuit 14 causes the PLL 88 to send a signal to the PLL 88. An instruction is issued to operate with a feedback gain higher than the fourth gain (S134). The binary data is valid. By operating the PLL 88 with a high feedback gain, the error between the frequency determined by the period of the time cell set by the PLL 88 and the frequency of the output signal V (t) is quickly converged. When the predetermined time has elapsed (S136),
The PLL 88 operates with a low feedback gain (fifth gain) (S13).
8). When data reading from the medium 72 is completed (S
140), the process shown in FIG. 4 ends.

While the embodiment of the present invention has been described above, the present invention can be implemented in other embodiments.
For example, in the flowchart shown in FIG. 4, the error of the AGC 82 is made to converge (S130, S132) and the error of the PLL 88 is made to converge (S134, S136), but the convergence of the error of the AGC 82 and the convergence of the error of the PLL 88 are almost equal. It can be done at the same time.

In a general data reproducing apparatus, the adjustment of the amplitude of the output signal V (t) to the predetermined amplitude value Ao by the AGC is often performed only at the beginning of the operation. The change of the feedback gain of the AGC can be performed not by the operation / comparison circuit but by a timer circuit as in the conventional case.

The error in the amplitude and frequency of the read signal due to the offset generated in the state where the AGC 82 and the PLL 88 have a low feedback gain (S142) may be so large that data cannot be read. If the data cannot be read out even if the convergence of the offset generated in the state where the AGC 82 and the PLL 88 have a low feedback gain (S142) is detected (S132), the error convergence of the AGC 82 (S130, S132) and the PLL 8 are again performed.
8, error convergence (S134, S136) can also be performed.

In the flowchart of FIG. 3, the occurrence and convergence of the offset are determined based on the results of the past three comparisons. However, the present invention is not limited to the past three times, and the occurrence and convergence are determined based on an arbitrary number of comparison results. Can be determined. The condition for the occurrence of the offset is not limited to two out of three times, but may be any number. The condition for offset convergence is not limited to all three times, but may be any number.

While the invention has been described with reference to particular embodiments, the invention is not limited thereto.
The present invention can be practiced in various modified, modified, and modified forms based on the knowledge of those skilled in the art without departing from the spirit of the present invention. As long as the same operation or effect is produced, any of the invention-specifying matters can be replaced with another technology. The present invention can be embodied in a form in which the invention-specific matter integrally formed is composed of a plurality of elements, or in a form in which the invention-specific matter composed of a plurality of elements is integrally constructed.

[0043]

According to the present invention, the output gain of the PLL is stabilized in a short time by increasing the feedback gain of the PLL after the offset of the read signal occurs. It is possible to suppress the occurrence of the read error of the read signal after the occurrence of the offset. By using the signal VAL for the error position information, it is possible to correct the error of the offset that continues for a long time. The reliability of data read from the medium can be improved.

[Brief description of the drawings]

FIG. 1A is a block diagram illustrating a configuration example of a data reproducing apparatus according to the present invention, and FIG. 1B is a block diagram illustrating a configuration example of a level determination device illustrated in FIG.

2A is a diagram showing an outline of noise due to thermal asperity, and FIG. 2B is an enlarged view of a main part of FIG.

FIG. 3 is a flowchart illustrating an example of a procedure for detecting occurrence and convergence of an offset.

FIG. 4 is a flowchart illustrating an example of a procedure for changing the feedback gain of the AGC and the PLL.

FIG. 5A is a block diagram illustrating an example of a configuration of a conventional data reproducing apparatus, FIG. 5B is a diagram illustrating an example of a data recording format of a medium, and FIG. FIG. 3 is a block diagram illustrating a configuration example of a level determiner.

FIG. 6 is a diagram illustrating an outline of generation of binary data.

7A is a diagram illustrating an example of convergence of an error, and FIG.
FIG. 4 is a diagram showing another example of a data recording format of a medium.

[Explanation of symbols]

 10: Level determiner 12: Differentiating circuit 14: Operation / comparison circuit (arithmetic circuit, comparison circuit, control means) 20: Data reproduction device 22, 76: Decoder 24, 78: Error correction circuit 26, 86: Binarization circuit 70: Conventional data reproducing device 72: Media 74: Conventional level determiner 80: Timer circuit 82: AGC (automatic gain control circuit) 84: Zero cross detection circuit 88: PLL (Phase locked loop circuit)

Continued on the front page (72) Inventor Toshio Kanai 800 Miyake, Yasu-cho, Yasu-cho, Yasu-gun, Shiga Prefecture IBM Japan, Ltd. F-term in Yasu Office (Reference) 5D044 AB05 AB07 BC01 BC02 BC08 CC04 DE32 DE39 DE46 FG05 FG18 GK12 GK14 GK19 HH17 5D090 AA01 BB02 EE13 EE17 FF02 FF41 JJ02

Claims (14)

[Claims] An automatic gain control circuit for maintaining the amplitude of a read signal read from a data recording medium at a predetermined amplitude value, and a first intersection between an output signal output from the automatic gain control circuit and a required threshold level , A phase-locked loop circuit for setting a time cell having a period determined by the frequency of the output signal, and a binary circuit based on the presence or absence of the first intersection in each time cell. What is claimed is: 1. A data reproducing apparatus comprising: a binarizing circuit for generating data; and a decoder for decoding binary data, wherein: a differentiating circuit for obtaining a second derivative of an output signal output from the automatic gain control circuit; An arithmetic circuit for calculating a time difference between a second intersection of the second derivative of the output signal detected by the cross detection circuit and the zero level, and a time difference between the first intersection and the calculated time difference; A comparison circuit that compares the lengths of the signals; and a setting of a convergence speed of an error between an amplitude of the output signal of the automatic gain control circuit and the predetermined amplitude value, and a setting of the phase locked loop circuit according to a comparison result of the comparison circuit. Control means for changing the setting of the convergence speed of the error between the frequency determined by the period of the time cell to be read and the frequency of the read signal. 2. The control unit includes: a unit that detects occurrence of an offset of a read signal from a comparison result of the comparison circuit; a unit that detects convergence of an offset of a read signal from a comparison result of the comparison circuit; 2. The data reproducing apparatus according to claim 1, further comprising means for instructing a change in a convergence speed of an error between said automatic gain control circuit and a phase locked loop circuit when occurrence or convergence of said error is detected. 3. The means for detecting the occurrence of the offset includes: means for storing the past n comparison results (n is an integer of 1 or more) of the comparison circuit; 3. The data reproducing apparatus according to claim 2, further comprising means for checking whether or not the comparison result of j or more (j is an integer of 1 or more and n + 1 or less) is determined to be longer than the time difference. 4. A means for detecting the convergence of the offset, a means for storing the past n comparison results of the comparison circuit, and a comparison result of the comparison circuit and a comparison result of the past n times. 3. The data reproducing apparatus according to claim 2, further comprising means for checking whether or not the comparison result of k or more (k is an integer of 1 or more and n + 1 or less) determines that the time difference is shorter. 5. The automatic gain control circuit according to claim 1, wherein the means for instructing the change of the error convergence speed is such that when the error convergence speed of the automatic gain control circuit is a first speed and the convergence of the offset is detected, Means for instructing the phase-locked loop circuit to reduce the error convergence speed from the second speed after a predetermined time has elapsed after the error convergence speed of the phase-locked loop circuit has reached the second speed. Means for instructing the automatic gain control circuit and the phase-locked loop circuit to converge at a third speed and a fourth speed, respectively. 5. The data reproducing apparatus according to claim 2, further comprising: means for instructing the error convergence speed to be faster than the fourth speed. 6. The control means according to claim 1, wherein said binary data is output during a period from the time when the convergence speeds of the errors of the automatic gain control circuit and the phase locked loop circuit converge after the occurrence of the offsets at the third speed and the fourth speed, respectively. 6. The data reproducing apparatus according to claim 5, further comprising means for sending a signal indicating invalidity to said binarizing circuit. 7. The data reproducing apparatus according to claim 1, wherein said automatic gain control circuit includes means for invalidating detection of said second intersection based on a waveform of a read signal. 8. A step of adjusting an amplitude of a read signal read from a data recording medium to a predetermined amplitude value by an automatic gain control circuit, and a first intersection between an output signal from the automatic gain control circuit and a required threshold level. Detecting; and setting time cells of a period determined by the frequency of the output signal; and generating binary data based on the presence or absence of the first intersection in each time cell; Decoding a binary data, comprising: obtaining a second derivative of an output signal whose amplitude is adjusted to the predetermined amplitude value; and calculating a second derivative of the output signal and a zero level. Detecting a second intersection; obtaining a time difference between the first intersection and the second intersection; comparing a length of the obtained time difference with a predetermined time. And a convergence speed of an error between the amplitude of the read signal for obtaining the first and second intersections and the predetermined amplitude value, and a period of the time cell, according to a result of the comparison between the time difference and a predetermined time. Changing the convergence speed of the error between the determined frequency and the frequency of the read signal. 9. The method according to claim 1, wherein the step of changing the convergence speed of the error includes the step of detecting occurrence of an offset of the read signal from a result of the comparison between the time difference and a predetermined time; 9. The data reproducing method according to claim 8, further comprising the steps of: detecting a convergence of the offset; and, when the occurrence or convergence of the offset is detected, instructing a change in a convergence speed of the error between the amplitude and the frequency. 10. The step of detecting the occurrence of the offset includes determining that the time difference is longer than a comparison result of the time difference and a past m times (m is an integer of 1 or more) of a predetermined time. A step of determining the number of comparison results; and a step of determining that an offset has occurred if the comparison result of p or more (p is an integer of 1 or more and m or less) is determined to be longer than the time difference. Item 9. The data reproducing method according to Item 9. 11. The step of detecting the convergence of the offset comprises: comparing the time difference with a result of the past m times of a predetermined time;
The step of examining the number of comparison results for which the time difference is determined to be shorter, and if the comparison result of q or more (q is an integer of 1 to m) is determined to be shorter, the offset is 10. The data reproducing method according to claim 9, comprising the step of determining that convergence has occurred. 12. The step of instructing a change in the convergence speed of the error, wherein the convergence speed of the amplitude error is set to a first speed when the convergence speed of the offset is detected at a first speed. Instructing to make the convergence speed of the frequency error slower than the second speed after a lapse of a predetermined time after the convergence speed of the frequency error becomes the second speed. When the convergence speed of the offset generated at the third speed and the fourth speed is detected as the convergence speed of the amplitude and frequency errors, respectively, instructing the convergence speed of the frequency error to be faster than the fourth speed. The data reproducing method according to any one of claims 9 to 11, comprising: 13. A signal indicating that the binary data is invalid is generated until the convergence speeds of the amplitude and frequency errors converge after an offset occurs at a third speed and a fourth speed, respectively. 13. The data reproducing method according to claim 12, wherein: 14. The data reproducing method according to claim 8, further comprising a step of invalidating the detected second intersection according to noise of a read signal.