JP2002358501A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a synchronizing circuit to be stably operated without inconsistency and without increasing a circuit scale and power consumption. SOLUTION: Local synchronization parallel pulse signal processing circuit is provided with a plurality of neurons, that is bonded mutually based on the prescribed rule and arranged in parallel, for performing a prescribed operation to an input signal and outputting it, a phase synchronizing signal generating circuit for outputting a phase synchronizing signal to the prescribed near neuron and a synchronization detecting means for detecting synchronization within the permission phase difference of the output of prescribed near neuron. The phase synchronizing signal generating circuit is functioned as the neuron for the prescribed operation and the output in response to the synchronization detecting result of the synchronization detecting means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit such as a neural network for performing parallel pulse signal processing with a local synchronous operation.

[0002]

2. Description of the Related Art Conventionally, in the field of image recognition and voice recognition, a type in which a recognition processing algorithm specialized for a specific recognition target is sequentially calculated and executed as computer software, or a dedicated parallel image processor (SIM) is used.
D, MIMD machine, etc.).

A typical example of the image recognition algorithm will be described below. First, as a feature to calculate and perform a feature amount related to the similarity with the recognition target model, model data of the recognition target is expressed as a template model, and similarity to the input image (or its feature vector) is determined by template matching or the like. Calculation of degree, calculation of higher-order correlation coefficient, etc., mapping of input pattern to eigenimage function space obtained by principal component analysis of target model image, and calculation of distance between model and feature space Method (Sirovic
h, et al., 1987, Low-dimensional procedure for the
characterization of human faces, J. Opt. Soc. Am.
[A], vol. 3, pp.519-524), graphically represent multiple feature extraction results (feature vectors) and their spatial arrangement,
A method of calculating similarity by elastic graph matching (Lades et al. 1993, Distortion Invariant Object R
ecognition in the Dynamic Link Architecture, IEEE
Trans.on Computers, vol.42, pp.300-311), a method of performing a predetermined transformation on an input image to obtain a position, rotation, and scale-invariant representation and then collating with a model (Seibert, et al.
1992, Learning and recognizing 3D objects from mu
ltiple views in a neural system, in Neural Network
s for Perception, vol. 1 Human and Machine Percept
ion (H. Wechsler Ed.) Academic Press, pp.427-444)
Etc.

As a pattern recognition method using a neural network model inspired by the information processing mechanism of a living body, a method of performing hierarchical template matching (Japanese Patent Publication No. 60-712, Fuku
shima & Miyake, 1982 Neocognitron: A new algorithm
for pattern recognition tolerant of deformation a
nd shifts in position, Pattern Recognition, vol.1
5, pp.455-469), a method of obtaining a scale and position-invariant representation of the center of an object using a dynamic routing neural network (Anderson, et al. 1995, Routing Networks in
Visual Cortex, in Handbook of Brain Theory and Neu
ral Networks (M.Arbib, Ed.), MIT Press, pp.823-82
6), other multilayer perceptrons, radial basis functions (Radial
Basis Function) There is a method using a network.

On the other hand, as an attempt to more faithfully incorporate an information processing mechanism based on a biological neural network, a neural network model circuit has been proposed in which information is transmitted and represented by a pulse train corresponding to an action potential (Mur).
ray et al., 1991 Pulse-Stream VLSI Neural Networks
Mixing Analog and Digital Techniques, IEEE Trans.
on Neural Networks, vol.2, pp.193-204.
No. 62157, JP-A-7-334478, JP-A-8-153148
And Japanese Patent No. 2879767).

As a method of recognizing and detecting a specific object by a neural network composed of pulse train generating neurons, a higher order (second or higher order) by Eckhorn et al. On the assumption of a linking input and a feeding input is used. ) Model (Eckhorn, et al. 1990, Feature linking via synchr
onization among distributed assemblies: Simulation
of results from cat cortex, Neural Computation, V
ol.2, pp.293-307), that is, a method using a pulse-coupled neural network (hereinafter abbreviated as PCNN) (USP56).
64065 and Broussard, et al. 1999, Physiolo
gically Motivated Image Fusion for Object Detectio
n using a Pulse Coupled Neural Network, IEEE Tran
s. on Neural Networks, vol. 10, pp. 554-563, etc.).

As a method of reducing the wiring problem in the neural network, there is a method of encoding the address of a so-called pulse output neuron in an event-driven manner (Address Event Representation: AER) (Lazzaro, et al. 1993). , Silicon Auditory
Processors as Computer Peripherals, In Touretzky,
D. (ed), Advances in Neural Information Processing
Systems 5. San Mateo, CA: Morgan Kaufmann Publisher
s). In this case, since the ID of the neuron on the output side of the pulse train is binary-coded as an address, even if output signals from different neurons are temporally arranged on a common bus, the neurons on the input side do not. The address of the original neuron can be automatically decoded.

On the other hand, in the neural network processor according to Japanese Patent No. 2741793, the number of neurons and the circuit scale are reduced by forming a multi-layer feedforward network in a systolic array architecture.

In the parallel processing multiprocessor system and the like according to Japanese Patent No. 2500038, the presence or absence of an error is detected by majority processing of a signature generated simultaneously with processing of an instruction set in a distributed parallel computing system.

In recent years, as the operating frequency of the microprocessor has been greatly increased, the chip is divided into a plurality of blocks and each block is asynchronously operated instead of operating the entire chip in synchronization with a single clock signal. An architecture that runs on a computer has been developed (Schuster, S. et al.,
“Asynchronous Interlocked Pipelined CMOS Circuits
Operating at 3.3-4.5GHz ”, 2000 IEEE Internationala
l Solid-State Circuits Conference (ISSCC2000), WA1
7.3, vol.43, pp.292-293, 2000).

[0011]

In the above-mentioned conventional example, a global clock signal is used as a control clock signal for synchronizing each operation element, or a synchronous cluster for performing a local operation is formed. It is necessary to use a local clock signal for performing the control as a control clock signal.

[0012] Therefore, it is difficult to realize a synchronous circuit which stably operates without inconsistency due to an increase in circuit scale and power consumption.

[0013]

According to the present invention, a phase synchronization signal generating circuit sends a signal between an output signal of an operation element from a phase synchronization signal generation circuit to the operation element in accordance with an output of the operation element to be phase-synchronized. By the function of outputting the phase synchronization signal having the signal level whose phase difference is within the allowable phase difference, perform the local synchronization operation of the parallel pulse signal processing consistently and stably,
Another object is to realize constant power consumption.

Further, by switching the circuit configuration in accordance with the synchronization detection result of the synchronization detection means, the function of the phase synchronization signal generation circuit and the function of the arithmetic element for performing a predetermined operation and outputting are realized by the same element. The purpose of the present invention is to reduce the circuit scale.

According to the present invention, a plurality of arithmetic elements which are connected to each other in a signal processing circuit based on a predetermined rule and which perform a predetermined operation on an input signal and output a signal, A phase synchronization signal generating circuit for outputting a phase synchronization signal to the arithmetic element, and synchronization detection means for detecting synchronization within an allowable phase difference between outputs of the arithmetic element in a predetermined vicinity, The signal generation circuit may also function as an arithmetic element that performs the predetermined operation and outputs the result in accordance with a synchronization detection result of the synchronization detection unit.

Thus, even if the operation of each of the arithmetic elements constituting the parallel processing circuit is asynchronous, desired arithmetic processing can be performed after synchronization is established, and the circuit scale can be reduced. Become.

In a signal processing circuit according to another aspect of the present invention, the output of the phase synchronization circuit is performed in response to a time-series signal input from a predetermined neighboring arithmetic element. You may.

Thus, since event-driven synchronization is locally established such that a local synchronization cluster is appropriately formed in accordance with the operation content of a predetermined neighboring arithmetic element, power consumption is reduced and operation is reduced. Stabilization can be achieved with an asynchronous parallel processing circuit.

In a signal processing circuit according to another aspect of the present invention, the output of the phase synchronization circuit may be a pulse signal.

Thus, the arithmetic element to be synchronized performs synchronized output within an allowable phase difference at a timing according to the phase synchronization signal which is the input pulse signal.

In a signal processing circuit according to another aspect of the present invention, the arithmetic element in the predetermined vicinity has a refractory period, and the phase synchronizing signal is output after a signal is input in the phase synchronizing signal generating circuit. The time interval until the operation is performed may have a time interval longer than the refractory period of the predetermined neighboring arithmetic element.

Thus, the arithmetic element to which the phase synchronization signal has been input during the refractory period can perform an output synchronized with the other arithmetic elements when the next phase synchronization signal is input.

In the signal processing circuit according to another aspect of the present invention, the output of the phase synchronization signal output from the phase synchronization signal generation circuit to the predetermined neighboring operation element is the same as the predetermined neighboring operation element. The phase difference between the output signals from the control signals may be controlled so as to be within the allowable phase difference. Is output in a very short time after the input of the calculation element, and the phase of the output signal of the arithmetic element becomes a synchronized phase within an allowable phase difference.

Further, it is possible to shorten the time until the synchronization is established.

In a signal processing circuit according to another aspect of the present invention, the predetermined neighboring computing element has a refractory period, and the phase difference between the output signals of the prescribed neighboring computing element is the phase synchronization. When a signal is input during a period other than the refractory period of the arithmetic element, the signal may be within the allowable phase difference.

As a result, the arithmetic element in the vicinity of the predetermined position to which the phase synchronization signal has been input at a timing other than the refractory period has a phase of the output signal that is substantially the same within the allowable phase difference.

In a signal processing circuit according to another aspect of the present invention, the synchronization detecting means includes an arithmetic element for outputting an output according to an integrated value of the input signal.

Thus, it is possible to detect the establishment of the synchronization according to the integrated value of the output value of the arithmetic element to be synchronized.

In a signal processing circuit according to another aspect of the present invention, a plurality of arithmetic elements which are connected in parallel with each other based on a predetermined rule and are arranged in parallel to perform a predetermined operation on an input signal and output the same are provided. A phase synchronization signal generating circuit for outputting a phase synchronization signal to the arithmetic element in a predetermined vicinity,
Synchronization detecting means for detecting synchronization within an allowable phase difference of the output of the arithmetic element in a predetermined vicinity, and a phase synchronization signal output from the phase synchronization signal generation circuit to the arithmetic element in the predetermined vicinity. Is controlled such that a phase difference between output signals from the predetermined neighboring arithmetic elements is within the allowable phase difference.

As a result, even if the operation of each arithmetic element constituting the parallel processing circuit is asynchronous, a desired arithmetic processing can be performed after synchronization is established, and the arithmetic element to be synchronized is The output is performed in a very short time after the input of the phase synchronization signal, and the phase of the output signal of the arithmetic element becomes a synchronized phase within an allowable phase difference.

Further, the time until the synchronization is established can be shortened.

In a signal processing circuit according to another aspect of the present invention, the predetermined neighboring computing element has a refractory period, and the phase difference between the output signals of the prescribed neighboring computing element is the phase synchronization. When a signal is input during a period other than the refractory period of the arithmetic element, the signal may be within the allowable phase difference.

As a result, the arithmetic elements in the predetermined vicinity near the input of the phase synchronizing signal at a timing other than the refractory period have almost the same phase of the output signal within the allowable phase difference.

In a signal processing circuit according to another aspect of the present invention, the output of the phase locked loop is performed in response to a time-series signal input from a predetermined neighboring arithmetic element. Is also good.

As a result, the event-driven synchronization is locally established such that a local synchronization cluster is appropriately formed in accordance with the operation content of a predetermined neighboring arithmetic element, thereby reducing power consumption and reducing operation. Stabilization can be achieved with an asynchronous parallel processing circuit.

In a signal processing circuit according to another aspect of the present invention, the synchronization detecting means may be an arithmetic element for outputting an output according to an integrated value of an input signal.

As a result, the establishment of synchronization can be detected in accordance with the integrated value of the output value of the arithmetic element to be synchronized.

In a signal processing circuit according to another aspect of the present invention, the output of the phase locked loop may be a pulse signal.

Thus, the arithmetic element to be synchronized performs synchronized output within an allowable phase difference at a timing according to the phase synchronization signal which is the input pulse signal.

In a signal processing circuit according to another aspect of the present invention, the arithmetic element in the predetermined neighborhood has a refractory period, and the phase synchronization signal is output after the signal is input in the phase synchronization signal generation circuit. The time interval until the operation is performed may have a time interval longer than the refractory period of the predetermined neighboring arithmetic element.

Thus, the arithmetic element to which the phase synchronization signal has been input during the refractory period can perform an output synchronized with the other arithmetic elements when the next phase synchronization signal is input.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In this embodiment, a neural network model inspired by an information processing mechanism of a living body is used as a locally synchronized signal processing circuit.

However, in the present invention, the overall function and operation of the pulse signal processing circuit are not particularly limited, and the information may be transmitted by forming a local synchronous cluster as described later. A signal processing circuit having another configuration and function may be used as long as the signal processing circuit has another configuration and function.

Therefore, it should be noted that the pattern recognition apparatus described below is merely an example for describing the present invention to the extent that it is tired.

The overall configuration Overview FIG. 1 is a diagram showing an overall configuration of a network for pattern detection and recognition system in the present embodiment. This device mainly deals with information related to recognition (detection) of an object or a geometric feature.

FIG. 1 shows a so-called Convolutional network structure (LeCun, Y. and Bengio, Y., 1995, “Convolu
nation Networks for Images Speech, and Time Serie
s ”inHandbook of Brain Theory and Neural Networks
(M. Arbib, Ed.), MIT Press, pp. 255-258). The final output corresponds to the recognition result, that is, the category of the recognized object.

The data input layer 1 is a CMOS sensor or a photoelectric conversion element such as a CCD element in the case of the image sensor means, and is a voice input sensor in the case of detecting and recognizing voice. Alternatively, high-dimensional data obtained from an analysis result (for example, principal component analysis, vector quantization, etc.) of the predetermined data analysis means may be input.

Hereinafter, the case of inputting an image will be described. The feature detection layer (1, 0) performs multi-resolution processing by Gabor wavelet transform or the like to apply local low-order features of the image pattern (which may include color component features in addition to geometric features) to each of the entire screen. At the position (or each of the predetermined sampling points over the entire screen), the same number of feature categories are detected at the same location at a plurality of scale levels or resolutions, and the types of the feature amounts (for example, a predetermined direction as a geometric feature are detected). When a line segment is extracted, it has a receptive field structure corresponding to the geometrical structure (slope of the line segment), and is composed of neuron elements that generate a pulse train according to the degree.

The feature detection layer (1, k) forms a processing channel at a plurality of resolutions (or scale levels) as a whole (where k ≧ 0). That is, in the case where the Gabor wavelet transform is performed in the feature detection layer (1, 0), a set of feature detection cells having a Gabor filter kernel having the same scale level and different direction selectivity in the receptive field structure is used for feature detection. The same processing channel is formed in the layer (1,0), and also in the subsequent layer (1,1), the feature detection cells receiving outputs from the feature detection cells (detecting higher-order features)
Belong to the same channel as the processing channel.

In the subsequent layer (1, k) (where k> 1), similarly, the feature detection cells receiving outputs from a plurality of feature integrated cells forming the same channel in the (2, k-1) layer Are configured to belong to the channel. In each processing channel, processing at the same scale level (or resolution) proceeds, and detection and recognition from low-order features to high-order features are performed by hierarchical parallel processing.

The feature integration layer (2,0) has a predetermined receptive field structure.
(Hereinafter, the receptive field has a coupling range with the output element of the immediately preceding layer, and the receptive field structure means the distribution of the coupling load), has a neuron element that generates a pulse train, and has a feature detection layer ( The integration of a plurality of neuron element outputs in the same receptive field from (1, 0) (operation such as subsampling by local averaging) is performed. Further, each receptive field of the neuron in the feature integration layer has a common structure among neurons in the same layer. Each feature detection layer (1, 1), (1, 2),.
(1, N)) and each feature integration layer ((2,1), (2,2),...,
(2, N)) have a predetermined receptive field structure acquired by learning, and the former ((1, 1),.
) Performs detection of a plurality of different features in each feature detection module, and the latter ((2, 1),...) Integrates detection results regarding a plurality of features from the preceding feature detection layer.
However, the former feature detection layer is connected (wired) to receive the cell element output of the preceding feature integration layer belonging to the same channel.
Have been. Subsampling, which is a process performed in the feature integration layer, is performed in a local region (a local receptive field of the feature integration layer neuron) from a feature detection cell population of the same feature category.
This is for averaging the output from the.

FIG. 2 is a diagram showing a configuration of a synapse circuit and a neuron element. As shown in FIG. 2A, the structure for connecting the neuron elements 201 between the layers includes a signal transmission unit 203 (wiring or delay line) corresponding to an axon or a dendrite of a nerve cell, and a synapse circuit. This is S202. FIG.
(A) relates to the output (input from the viewpoint of the cell N) of the feature integrated (detected) cell forming the receptive field for a certain characteristic detected (integrated) cell (N) from the neuron group (n _i ). 3 shows a configuration of a connection. The signal transmission unit 203 shown by a thick line forms a common bus line, and pulse signals from a plurality of neurons are transmitted on this signal transmission line in time series. The same configuration is adopted when receiving an input from a cell (N) of an output destination. In this case, the input signal and the output signal may be divided and processed on the time axis with exactly the same configuration, or two systems for input (dendritic side) and output (axon side) may be used. The processing may be performed by providing the same configuration as that of FIG.

The synapse circuit S202 has an interlayer connection (a connection between a neuron on the feature detection layer 102 and a neuron on the feature integration layer 103, and each layer has a connection to a subsequent layer and a preceding layer. May be involved)
Some are involved in connections between neurons in the same layer. The latter is mainly used, if necessary, mainly for coupling a pacemaker neuron described later with a feature detection or feature integration neuron.

In the synapse circuit S202, the so-called excitatory coupling amplifies the pulse signal, and the inhibitory coupling conversely attenuates. When transmitting information using a pulse signal, amplification and attenuation can be realized by any of amplitude modulation, pulse width modulation, phase modulation, and frequency modulation of the pulse signal.

In this embodiment, the synapse circuit S20
2 is mainly used as a phase modulation element of the pulse, the amplification of the signal is converted as a substantial advance as a characteristic quantity of the pulse arrival time characteristic, and the attenuation is converted as a substantial delay. That is,
The synaptic connection gives the arrival position (phase) on the time axis peculiar to the feature of the output neuron as described later, and qualitatively the excitatory connection leads the phase of the arrival pulse with respect to a certain reference phase. In the case of inhibitory coupling, a delay is similarly given.

In FIG. 2A, each neuron element
n _j outputs a pulse signal (spike train) and uses a so-called integral-and-fire type neuron element as described later. As shown in FIG. 2 (C),
The synapse circuit and the neuron element may be combined to form a circuit block.

[0057] will be described neuron element then neurons constituting each layer. Each neuron element is an extended model based on the so-called integral-and-fire neuron, and fires when the result of spatiotemporal linear addition of the input signal (pulse train corresponding to the action potential) exceeds the threshold, and the pulse shape It is the same as a so-called integral-and-fire neuron in that it outputs a signal.

FIG. 2B shows an example of a basic configuration representing the operation principle of a pulse generation circuit (CMOS circuit) as a neuron element, and a known circuit (IEEE Trans. On Neural Net).
works Vol. 10, pp. 540). Here, it is configured to receive excitatory and inhibitory inputs as inputs.

Hereinafter, the operation principle of the pulse generation circuit will be described. Capacitor C ₁ and resistor R excitatory input side
The time constant of _one circuit is smaller than the time constant of the capacitor C ₂ and the resistor R ₂ , and in a steady state, the transistors T ₁ ,
T ₂ and T ₃ are shut off. Note that the resistance is actually
It is composed of transistors coupled in diode mode.

[0060] potential of the capacitor C ₁ is increased, the capacitor
Above than that of C ₂ by the threshold value of the transistors _{T 1,} transistors _{T 1} becomes active, further activates the transistor _T 2, _{T 3.} Transistors T ₂ , T
₃ constitutes a current mirror circuit, the output of the circuit of FIG. 2 (B), is output from the capacitor C ₁ side by the output circuit (not shown). When the charge storage amount of the capacitor C ₂ becomes maximum, transistors T ₁ is blocked, as a result transistors T ₂ and T ₃ are also cut off, the positive feedback is constituted as a 0.

[0061] so-called refractory period, the capacitor C ₂ is discharged, the potential of the capacitor C ₁ is large than the potential of the capacitor C _2, as long as the difference does not exceed the threshold value of the transistor T _1, the neuron does not respond . Capacitors C ₁ and C
_A periodic pulse is output by repeating the alternate charging and discharging of No. ₂ and its frequency is generally determined according to the level of the excitatory input. However, depending on the presence of the refractory period, it is possible to limit the maximum value or to output a constant frequency.

The potential of the capacitor, and hence the amount of charge stored, is
It is temporally controlled by a reference voltage control circuit (time window weight function generation circuit) 204. Reflecting this control characteristic,
This is weighted addition within a time window to be described later for the input pulse (see FIG. 7). The reference voltage control circuit 204 generates a reference voltage signal (corresponding to a weight function of FIG. 7B) based on a synchronization detection signal described later.

In general, the relationship between the sum of the input signals and the output level (pulse phase, pulse frequency, pulse width, etc.) changes depending on the sensitivity characteristics of the neuron. Can be changed by the top-down input of. In the following, for convenience of explanation, it is assumed that the circuit parameters are set such that the frequency of the pulse output corresponding to the total value of the input signal rises sharply (thus, almost binary in the frequency domain), and the output is performed by pulse phase modulation. It is assumed that the level (such as the timing at which phase modulation is applied) fluctuates.

As a pulse phase modulator, a circuit as shown in FIG. 5 to be described later may be added. As a result, the weight function within the time window is controlled by the reference voltage. As a result, the phase of the pulse output from this neuron changes, and this phase can be used as the output level of the neuron.

The time τ _w1 corresponding to the maximum value of the weighting function as shown in FIG. 7B that gives the temporal integration characteristic (reception sensitivity characteristic) of the pulse subjected to the pulse phase modulation by the synaptic connection is generally The time is set earlier than the estimated arrival time τ _{s1 of the} pulse unique to the feature given by the synaptic connection. As a result, a pulse arriving earlier within a certain range from the estimated arrival time (in the example of FIG. 7B, a pulse that arrives too early is attenuated) is a pulse signal having a high output level in the neuron receiving it. Is integrated over time. The shape of the weight function is not limited to a symmetric shape such as Gaussian, but may be an asymmetric shape. It should be noted that the center of each weighting function in FIG. 7B is not the expected pulse arrival time for the above-described purpose.

The phase of the neuron output (before synapse) is based on the beginning of the time window as described later, and the delay (phase) from the reference time is determined by the amount of charge accumulation after phase synchronization detection. Has characteristics. The details of the circuit configuration for providing such output characteristics will not be described because they are not the focus of the present invention. The post-synaptic pulse phase is obtained by adding the pre-synaptic phase to the unique phase modulation amount given by the synapse.

A known circuit configuration may be used in which, when the total value of inputs obtained by using a window function or the like exceeds a threshold value, an oscillation output is output with a predetermined timing delay.

The configuration of the neuron element is a neuron belonging to the feature detection layer 102 or the feature integration layer 103. When the firing pattern is controlled based on a phase synchronization circuit described later, phase synchronization of the output is achieved. After that, the circuit configuration may be such that the neuron outputs a pulse with a phase delay according to the input level (simple or weighted sum of the above input) received from the receptive field of the preceding layer. In this case, before the outputs are phase-synchronized, there is a transient transition state in which each neuron outputs pulses at random phases in accordance with the input level.

As described above, the neurons in the feature detection layer have a receptive field structure according to the feature category, and the input pulse signal (current value or potential) from the neuron in the preceding layer (input layer or feature integration layer) is obtained. When the total weight of the time window function (described later) is equal to or greater than a threshold value, a non-decreasing and non-linear function that asymptotically saturates to a certain level, such as a sigmoid function, according to the total value, that is, a so-called sq
A pulse is output with an output that takes a uashing function value (here, given by a phase change; a configuration that changes based on frequency, amplitude, and pulse width may be used).

[0070] Synaptic circuits such as FIG. 4, synaptic to each neuron n _'j is the coupling destination of the neuron n _i at the synapse circuit 202 (S _i) to (meaning the size of the modulation about the phase delay, etc.) This shows that the given small circuits are arranged in a matrix.

When the network has a configuration in which the connection weight has a covalent connection form (particularly, a case where the synapse connection is represented by a single weight coefficient), the delay amount at each synapse (P _{ij described} below) 3) can be uniform within the same receptive field unlike the case of FIG. In particular, the connection from the feature detection layer to the feature integration layer is performed when the feature integration layer performs sub-sampling by local averaging (however, using uniform weighting) of the output of the feature detection layer that is the preceding layer. Such a configuration can be made regardless of the detection target (that is, regardless of the problem).

In this case, each small circuit 401 shown in FIG.
Requires only a single circuit _{Sk, i} as shown in FIG. 4C _, which is a particularly economical circuit configuration. On the other hand, if the coupling from the feature integration layer (or the sensor input layer) to the feature detection layer is like this, the feature detection neuron will detect the simultaneous arrival of pulses representing multiple different feature elements (or
It is an event called “almost simultaneous arrival”.

As shown in FIG. 4B, each synapse connection small circuit 401 includes a learning circuit 402 and a phase delay circuit 403. The learning circuit 402 adjusts the delay amount by changing the characteristics of the phase delay circuit 403, and also stores the characteristic value (or its control value) on the floating gate element or on a capacitor coupled to the floating gate element. It is something to memorize. The phase delay circuit 403 is a pulse phase modulation circuit, and includes, for example, monostable multivibrators 506 and 507, resistors 501 and 504, capacitors 503 and 505 as shown in FIG.
There is a structure using the transistor 502. FIG. 5B shows a square wave P1 input to the monostable multivibrator 506 (FIG. 5B [1]), a square wave P2 output from the monostable multivibrator 506 (the same [2]), a monostable Multivibrator 507
Represents the respective timings of the square wave P3 ([3]) output from.

The details of the operation mechanism of the phase delay circuit 403 are omitted, but the pulse width of P1 is determined by the time until the voltage of the capacitor 503 due to the charging current reaches a predetermined threshold, and the width of P2 Is determined by the time constant of the resistor 504 and the capacitor 505. When the pulse width of P2 is
If the falling point shifts later, the rising point of P3 also shifts by the same amount, but the pulse width of P3 does not change. As a result, only the phase of the input pulse is changed. Is modulated and output.

A refresh circuit that uses the control voltage Ec as a reference voltage
The pulse phase (delay amount) can be controlled by changing the learning circuit 402 that controls the amount of charge stored in the capacitor 508 that applies the connection weight to the capacitor 509. In order to maintain the connection weight for a long period of time, after the learning operation, as a charge of a floating gate element (not shown) added to the outside of the circuit of FIG. The coupling load may be stored. Other configurations designed to reduce the circuit scale (for example, see Japanese Patent Application Laid-Open No. 5-37317)
A publicly known circuit configuration such as that described in Japanese Patent Application Laid-Open No. H10-327054 can be used.

FIG. 5 shows an example of a learning circuit at the synapse that achieves simultaneous arrival of pulses or a predetermined amount of phase modulation.
What has a circuit element as shown in FIG. That is, the learning circuit 402 is connected to the pulse propagation time measurement circuit 510.
(Here, the propagation time refers to a time difference between a pulse output time at a pre-synapse of a neuron of a certain layer and an arrival time of the pulse at an output destination neuron on the next layer), a time window generating circuit 511. , And a pulse phase modulation amount adjustment circuit 512 that adjusts the pulse phase modulation amount at the synapse so that the propagation time becomes a constant value.

By setting the time window based on the firing point of the output destination neuron, the extended Hebb's learning rule shown below is applied.

Processing at the feature detection layer (1,0) (Gabor wavelet
( Lower-order feature extraction by transformation, etc.) The feature detection layer (1, 0) has a pattern structure (lower-order feature) having a predetermined spatial frequency in a local area of a certain size and having a vertical directional component. Assuming that there is a neuron for detecting the characteristic, if there is a corresponding structure in the N1 receptive field on the data input layer 1, a pulse is output at a phase corresponding to the contrast. Such a function can be realized by a Gabor filter. Hereinafter, the feature detection layer (1, 0)
The feature detection filter function performed by each neuron will be described.

In the feature detection layer (1, 0), multi-scale
It is assumed that Gabor wavelet transform represented by a filter set of multi-directional components is performed, and each neuron (or each group including a plurality of neurons) in a layer has a predetermined G value.
It has an abor filter function. In the feature detection layer, a plurality of Gas with a fixed scale level (resolution) and different direction selectivities
A plurality of neuron groups consisting of neurons having a receptive field structure corresponding to the convolution operation kernel of the bor function are collectively formed to form one channel. Neurons that form the same channel have different direction selectivities, and neurons with the same size selectivity may be placed close to each other, or neurons that belong to the same feature category and belong to different processing channels. They may be arranged close to each other. This is because the arrangement configuration as shown in each drawing is easier to realize in terms of the circuit configuration for the sake of the combining process described later in the collective coding.

The details of the method of performing the Gabor wavelet conversion in a neural network are described in a document by Daugman (1988) (IEEE Trans. On Acoustics, Speech, and Signal Pro
cessing, vol. 36, pp. 1169-1179).

Each neuron of the feature detection layer (1,0) is represented by g
_It has a receptive field structure corresponding to _mn . G _mn having the same scale index m has the same size receptive field, and the corresponding kernel g _mn size has a size corresponding to the scale index in operation. Here, 30 × 3 on the input image in order from the coarsest scale
The sizes were 0, 15 × 15, and 7 × 7. Each neuron outputs a non-linear squashing function of a wavelet transform coefficient value obtained by inputting a product sum of a distribution weight coefficient and image data (here, a phase reference is used;
The pulse output may be performed based on the frequency, amplitude, and pulse width. As a result, Gabor wavelet conversion is performed as the output of the entire layer (1, 0).

Processing at the feature detection layer (medium and high order feature extraction)
Out) subsequent feature detection layer ((1,1), (1,2), each neuron ...), unlike the feature detection layer (1,0), a unique feature in the pattern to be recognized Is formed by the so-called Hebb learning rule or the like. The size of the local region where the feature detection is performed gradually becomes closer to the size of the entire recognition target in a later layer, and a medium-order or higher-order feature is geometrically detected.

For example, in the case of performing face detection and recognition, the middle-order (or higher-order) features represent features at the level of a figure element such as an eye, a nose, and a mouth that constitute the face. If different processing channels have the same hierarchical level (the complexity of detected features is the same level), the detected features differ in the same category but are detected on different scales. It is in. For example, "eye" as a secondary feature
In different processing channels, detection is performed as "eyes" having different sizes. That is, detection is attempted in a plurality of processing channels with different scale level selectivity for a given size "eye" in the image.

Note that the feature detection layer neurons are generally
A mechanism may be provided to receive the coupling of the shunting inhibition (shunting inhibition) based on the output of the preceding layer in order to stabilize the output (independent of low-order and higher-order feature extraction). .

Processing in the Feature Integration Layer The neurons in the feature integration layer ((2,0), (2,1),...) Will be described. As shown in FIG. 1, a feature detection layer (for example,
The connection from (1,0)) to the feature integration layer (eg, (2,0)) is
Both the input of the excitatory connection and the output of the phase-locked loop described later from the neuron of the same feature element (type) in the preceding feature detection layer in the receptive field of the feature-integrated neuron on the excitatory input side in FIG. The function of the neuron of the integrated layer is local averaging or sub-sampling for each feature category, as described above.

According to the former, a plurality of pulses of the same type of characteristic are input, and they are integrated and averaged in a local area (receptive field) (or a representative value such as a maximum value in the receptive field). ), The position fluctuation of the feature,
Deformation can be reliably detected. For this reason, the receptive field structure of the feature integration layer neuron is uniform regardless of the feature category (for example, each is a rectangular region of a predetermined size, and the sensitivity or the weight coefficient is uniformly distributed therein). You may comprise so that it may become.

In this embodiment , the pulse signal processing in the feature integration layer receives the synchronization detection signal from the phase synchronization circuit on the feature detection layer of the preceding layer number (1, k). Not so configured. This is because, in a feature-integrated cell, the phase (frequency, pulse width, or amplitude) determined by the input level (such as the sum of the input pulses over time) within a certain time range, rather than the arrival time pattern of the input pulse. However, since the pulse is output in the present embodiment, the timing is not so important because the pulse is output. It should be noted that this is not intended to exclude the configuration in which the feature-integrated cell receives the synchronization detection signal from the phase synchronization circuit of the feature detection layer in the preceding layer, and it goes without saying that such a configuration is also possible. .

The principle of operation of pattern detection and phase synchronization Next, pulse encoding and detection of a two-dimensional figure pattern will be described. FIG. 3 schematically shows the propagation of a pulse signal from the feature integration layer to the feature detection layer (for example, from layer (2,0) to layer (1,1) in FIG. 1). . Each neuron n _i on the feature integration layer side corresponds to a different feature amount (or feature element), and a neuron n ′ _j on the feature detection layer side is a higher order neuron obtained by combining the features in the same receptive field. Related to the detection of features (graphic elements).

The connection between each neuron is made during the pulse propagation.
Between and neuron n_iFrom neuron n ' _jSynaptic connection to
(S_{j, i}) Due to time delay etc. (specific to feature)
A delay occurs, resulting in neuron n '_jArrive at
The pulse train Pi is a pulse output from each neuron in the feature integration layer.
As long as the power is exerted, the synaptic connections determined by learning
Are in a predetermined order (and interval) depending on the delay amount of
(In FIG. 3A, P_Four, P_Three, P_Two, P₁Shown to arrive in the order
Has been).

FIG. 3 (B) shows the layer number after the phase synchronization between the feature integrated layer neurons is achieved when the time window synchronization control is performed using the synchronization detection signal from the phase synchronization circuit described later. 2, k) the feature integration cells n _{1 on,} n _2, n
₃ Shows the timing of pulse propagation from (each representing a different type of feature) to a certain feature detection cell (n'j) on layer number (1, k + 1) (which performs higher-level feature detection) .

In FIG. 13, the phase-locked loop forms the same receptive field and accompanies a feature detecting neuron that detects different types of features, forms the same receptive field as these, and forms a feature integration layer (or Input from the input layer). Further, since the output from the phase locked loop is also output to the excitatory input of the feature integrated layer neuron, a (loop-like) connection between the feature integrated layer neuron group and the phase locked loop is generated.
Interconnection exists.

Next, the operation principle of phase synchronization, which is the main feature of this embodiment, will be described in detail.

First, as shown in FIG. 13, the circuit configuration of the present embodiment receives an output signal from the feature integration layer neuron, detects the phase synchronization of the output signal, and controls the switches 1 and 2, A synchronous detection means for outputting a synchronous detection signal; and a means having mutual connection with the feature integration layer neuron and performing two functions of a function as a feature detection layer neuron and a function as a phase synchronization signal generation circuit. .

The two types of functions are a switch 1 and a switch 1.
It is switched by the operation of 2.

Next, the flow of processing in the above configuration will be described step by step.

First, the feature detection layer neuron and the phase synchronization signal generation circuit of FIG. 13 function as a phase synchronization signal generation circuit until the phase synchronization of the output of the feature integration layer neuron is established (hereinafter, phase synchronization is established). Until this is done, it is called a phase synchronization signal generation circuit).

At this time, the switch 1 is connected to the lower side, and the switch 2 is connected to the upper side.

When the feature integrated layer neuron receives and outputs the output from the preceding layer and fires, the output signal is amplified by an amplifier and then input to the phase synchronization signal generation circuit.

Upon receiving at least one of the inputs, the phase synchronization signal generation circuit outputs a phase synchronization signal, which is a pulse signal, to the feature integration layer neuron.

Here, assuming that the threshold characteristic of the phase synchronization signal generation circuit has a predetermined value, the output from the feature integration layer neuron is once passed through an amplifier so that the phase synchronization signal generation circuit can fire with one pulse. Amplify.

Subsequently, the phase synchronization signal output by the firing of the phase synchronization signal generation circuit is input to the feature integration layer neuron. Here, the phase synchronization signal finally received by the feature integration layer neuron is obtained. The level is set so that the output pulse of the phase synchronization signal generation circuit is input to the amplifier to amplify the signal level, and the internal potential of the feature integration layer neuron can reach the threshold value within the allowable phase difference.

Here, the allowable phase difference corresponds to the width of the phase synchronization detection window in FIG. 16. As will be described later, the phase synchronization detection means operates the feature integration layer neuron input in the phase synchronization detection window. By the integrated value of the output signal from
Detect phase synchronization.

Upon receiving the phase-locked pulse signal, the feature-integration-layer neuron exceeds the firing threshold level by the phase-locked pulse signal in any internal state except in a refractory period.

Here, as shown in FIG. 15B, due to the difference in the internal state of each feature integration layer neuron when the phase-locked pulse signal is input, the firing phase of the feature integration layer neuron is Although a slight difference occurs, as described above, the phase synchronization signal level is set so that the phase difference is equal to or less than the allowable phase difference. Have a phase difference within the allowable phase difference, and are in a synchronized state.

Further, the above-described operation is repeated until the feature integration layer neuron, which has been in the refractory period in the above-described operation, receives the phase synchronization signal at a timing other than the refractory period and fires, thereby finally achieving all the features. The output of the integrated layer neuron can be synchronized.

Next, the phase synchronization detecting means for detecting the above-mentioned phase synchronization state will be described.

As shown in FIG. 13, the phase synchronization detecting means receives the output of the feature integration layer neuron as an input signal.

Here, as shown in FIGS. 14A and 14B, the phase synchronization detecting means has the same configuration as that of the feature integration layer neuron explained in the section on the neuron element, and the phase synchronization detection window An input value within a phase synchronization detection window having a predetermined time determined by a generation circuit is integrated, and when the value exceeds a threshold value, a fire is generated and an output is performed.

Therefore, the time width of the phase synchronization detection window is set to an allowable phase difference when the above-mentioned feature integration layer neurons are phase-locked, and the outputs of all feature integration layer neurons that combine firing thresholds are set. By setting this value to the integral value, it becomes possible to detect the phase synchronization of the feature integration layer neuron.

That is, as shown in FIG. 16, by setting the allowable phase difference as the phase synchronization detection window, when the outputs of all the feature integration layer neurons are synchronized, the phase synchronization detection means in the neuron element circuit in the phase synchronization detection means Since the input integrated value within the synchronization detection window reaches the threshold value and fires, as a result, the synchronization firing of the feature integration layer neuron can be detected.

Next, the operation after detecting the phase synchronization will be described.

As shown in FIG. 14A, the phase synchronization detecting means includes a switch control signal generating circuit for generating a switch control signal in accordance with the output of the neuron element circuit, and a synchronous detection signal in accordance with the output. A synchronization detection signal generating circuit.

When the phase synchronization detecting means detects the phase synchronization of the feature integration layer neuron by firing the neuron element circuit as described above, it outputs a switch control signal by the switch control signal generation circuit receiving the output of the neuron element circuit. Then, the switch 1 is switched upward.

As a result, the input to the phase synchronization signal generation circuit becomes the output of the feature integration layer neuron subjected to the processing of the synapse circuits S1 to S4 in FIG. 13, and the function of the phase synchronization signal generation circuit is This means that the function has been switched to the function of the feature detection layer neuron (hereinafter, until the feature detection layer neuron completes the calculation and output based on the output signal of the feature integration layer neuron described later, the phase synchronization signal generation circuit performs the feature detection. Layer neurons).

Further, the phase synchronization detecting means outputs a switch control signal by the switch control signal generating circuit which has received the output of the neuron element circuit, in order to send the output from the feature detection layer neuron to the subsequent processing hierarchy, and 2, the connection between the feature detection layer neuron and the subsequent feature integration layer neuron is made conductive.

Here, the output signal of the feature integration layer neuron input to the feature detection layer neuron is purely the input of the phase synchronization signal to the feature integration layer neuron by the above-described switching operation. It becomes an output signal by firing according to the input from the previous layer of the neuron.

Further, the phase synchronization detection means outputs a synchronization detection signal to the feature detection layer neuron by the synchronization detection signal generation circuit receiving the output of the neuron element circuit,
A reference time for the generation timing of a time window described later is given.

In this case, by calculating in advance the time required for the output from the feature integration layer to arrive at the feature detection layer, it is possible to appropriately set the relationship between the synchronization detection signal and the time window generation timing. Becomes possible.

In this embodiment, the synchronization detection signal is a pulse-like signal, and the time when the signal is input to the feature detection layer neuron is set as the start point of the time window.

In the phase synchronization process described above, the integrated layer neurons corresponding to the overlapping receptive field portion are shown in FIG. 15A (in FIG. 15A, inputs from the preceding layer to the feature integrated layer neurons are indicated by thin lines, and The input from the layer neuron to the feature detection layer neuron is indicated by a dotted line, the phase synchronization signal is indicated by a bold line, and the synchronization detecting means, switches 1, 2, the synapse circuit, and the amplifier are omitted as shown in FIG. The phase-locked neuron receives the input of the phase-locked signal.
Alternatively, even if any one of the inputs from the phase synchronization signal generation circuit fires at least once, the output pulse is simultaneously input to the plurality of phase synchronization signal generation circuits, so that the phases of the plurality of phase synchronization signals at that time also change. Synchronize.

Accordingly, a plurality of phase synchronization signals are input to the feature integration layer neuron corresponding to the subsequent overlapping receptive field portion in a state where the respective phases are synchronized.
The process of establishing the phase synchronization of the feature integration layer neuron follows the same process as the case of the above-described single phase synchronization signal.

As described above, even when the feature integration layer neuron corresponding to the overlapping receptive field receives a plurality of phase synchronization signal inputs, it is possible to stably and consistently establish the output phase synchronization.

In particular, in the phase synchronization signal generation circuit, when the time interval from the input of the signal to the output of the phase synchronization signal is set to a time interval longer than the refractory period of the feature integration layer neuron, When the next phase synchronization signal is input, the feature integration layer neuron that did not fire because it was input during the refractory period can fire and output in phase synchronization with the other feature integration layer neurons. It is possible to shorten the time until

Next, the operation of the feature detection layer neuron after the phase synchronization of the output of the feature integration layer neuron is detected will be described.

When the synchronization detection signal is input to the feature detection layer neuron from the phase synchronization detection means, a time window is generated by the synchronization detection signal as described above.

Here, the time window is the feature detection layer neuron.
(n ′ _i ), which is common to each neuron in the feature integration layer forming the same receptive field with respect to the neuron, and gives a time range of time window integration.

The synchronization detecting means at the layer number (1, k) (k is a natural number) outputs a pulse output as a synchronization detection signal to the feature detection layer neuron (layer number (1, k)) to perform feature detection. The layer neuron provides a timing signal for generating a time window when the input is temporally added. The start time of this time window is a reference time for determining the arrival time of the pulse output from each integrated cell. That is, the synchronization detection means gives a pulse output time from the feature integration layer neuron and a reference pulse for time window integration in the feature detection cell.

Each pulse is given a predetermined amount of phase delay when passing through the synapse circuit, and further, reaches a feature detecting cell through a signal transmission line such as a common bus. The arrangement of the pulses on the time axis at this time is indicated by the pulses (P ₁ , P ₂ , P ₃ ) indicated by dotted lines on the time axis of the feature detection cells.

Each pulse (P ₁ , P _1
2 , P ₃ ) time window integration (usually one integration; however, charge accumulation by multiple time window integrations or averaging of multiple time window integrations may be performed) As a result, when it becomes larger than the threshold value, a pulse output (P _d ) is made based on the end time of the time window. Note that the learning time window shown in the figure is referred to when a learning rule described later is executed.

Subsequently, when the calculation operation described later is completed in the feature detection layer neuron as described above, the switch 1 returns to the lower side again, and the output of the feature integration layer neuron is passed through the amplifier to the feature detection layer neuron. Input to neuron.

At the same time, the output of the feature integration layer neuron is also input to the synchronization detecting means.

Then, the switch 2 returns to the upper side again, and the output of the feature detection layer neuron is input to the feature integration layer neuron.

This means that the role of the feature detection layer neuron has been switched again to the phase synchronization signal generation circuit.

In this embodiment, the switching operation of the switches 1 and 2 is set in advance so that the switch control signal is output from the switch control signal generation circuit after a predetermined time from the previous switching operation. It is realized by doing.

The operations of the switches 1 and 2 here can be performed by using other control means. However, since the operation is not related to the main point of the present invention, the description is omitted.

With respect to the processing steps described above, FIG.
FIG. 16 shows the pulse output timing of each neuron corresponding to (A).

In FIG. 16, when the feature integration layer neurons (N _{1I to} N _6I ) are fired and output by the feature detection neuron output in the preceding layer, a phase synchronization signal is output from the phase synchronization signal generation circuit. In the feature integration layer neuron to which the phase synchronization signal has been input, the phase synchronization of the output within the phase synchronization detection window is detected by the phase synchronization detection means through the above-described phase synchronization process.

When the phase synchronization of the output of the feature integration layer neuron is detected by the phase synchronization means, a synchronization detection signal is output to the feature detection layer neurons (N ′ _{2D to} N ′ _3D ).

As a result, in the feature detection layer neuron, a calculation is performed based on a time window, and an output is performed according to the calculation result.

As described above, by switching the function of the phase synchronization signal generation circuit and the function of the feature detection layer neuron by the switching operation, it is possible to achieve both stable establishment of consistent output phase synchronization and reduction of the circuit scale. Becomes possible.

Spatio- temporal integration of pulse output and network
Click properties Next calculation of spatial weighted sum when the input pulses (weighted sum) will be described.

As shown in FIG. 7B, in each neuron, the weighted sum of the input pulses is calculated by a predetermined weighting function (eg, Gaussian) for each sub-time window (time slot), and the sum of the weighted sums is calculated. It is compared with a threshold. τ _j represents the center position of the weighting function of the sub-time window j, and is represented by the start time reference (elapsed time from the start time) of the time window. The weight function is generally a function of a distance (shift on the time axis) from a predetermined center position (representing a pulse arrival time when a feature to be detected is detected) and is symmetric. Therefore, assuming that the center position τ of the weight function of each sub-time window (time slot) of a neuron is a time delay after learning between neurons, a neural network that performs a spatio-temporal weighted sum of input pulses (weighted sum) Can be regarded as a kind of time-domain domain Radial Basis Function Network (hereinafter abbreviated as RBF). The time window F _Ti of the neuron n _i using the weight function of the Gaussian function is expressed as σ for each sub-time window and b _ij for the coefficient factor.

[Outside 1] ... (1)

It should be noted that the weight function may take a negative value. For example, when a neuron of a certain feature detection layer is scheduled to finally detect a triangle, and a feature (F _false ) clearly not being a component of the figure pattern is detected, another feature is detected. as contribution is large even triangular detection output from the feature elements are not made to ultimately, in sum calculation processing of the input, the pulse corresponding to the feature _{(F fa ulse),} gives a negative contribution Such weighting functions and feature detection (integration) coupling from cells can be provided.

[0144] space sum when the input signal to the neuron n _i of the feature detection layer X _i (t) is

[Outside 2] ... (2) Here, ε _j is the initial phase of the output pulse from the neuron n _j , and when it converges to 0 by synchronous firing with the neuron n _i , ε _j may always be 0.
When the weighted function shown in FIG. 7B and the weighted function shown in FIG. 7B are executed, a temporal transition of the weighted sum value as shown in FIG. 7E is obtained. The feature detection neuron outputs a pulse when the weighted sum reaches a threshold value (Vt).

[0145] The output pulse signal from the neuron n _i, as described above, with the spatio-temporal sum squashing nonlinear function to become an output level and time delay given by learning (the so-called total input sum) of the input signal (phase) Output to neurons in the upper layer (pulse output is fixed frequency (binary), and phase modulation amount which becomes a squashing nonlinear function for spatio-temporal sum of input signal is added to phase corresponding to fixed delay amount determined by learning. Output).

Processes mainly performed in the feature detection layer (at the time of learning and recognition)
Will be described. In each feature detection layer, as described above, pulse signals related to a plurality of different features from the same receptive field are input in the processing channel set for each scale level, and a spatio-temporal weighted sum (weighted sum) is input.
Perform calculations and threshold processing. Pulses corresponding to each feature amount arrive at predetermined time intervals according to a delay amount (phase) predetermined by learning.

The learning control of the pulse arrival time pattern is not the focus of the present embodiment, and will not be described in detail. For example, the characteristic element constituting a certain figure pattern is the one that most contributes to the detection of the figure. Competitive learning is introduced so that the feature elements that arrive first and have the same pulse arrival time if they arrive as they arrive at a certain amount of time apart from each other. Alternatively, predetermined feature elements (feature elements constituting a recognition target, which are considered to be particularly important: for example, a feature having a large average curvature, a feature having a high linearity, etc.) arrive at different time intervals. It may be designed as follows.

In the present embodiment, neurons corresponding to each lower-order feature element in the same receptive field on the feature integration layer, which is the preceding layer, are synchronously fired (pulse output) at predetermined phases.
Will do. In general, there is a connection to a feature detection neuron that detects the same higher-order feature that is different in position but different in neurons in the feature integration layer (in this case, the same higher-order feature is formed although the receptive field is different) To have a bond).
At this time, it goes without saying that synchronous firing occurs even with these feature detection neurons. In each neuron on the feature detection layer, the calculation of the spatiotemporally weighted sum of the input pulses (sum of weights) is performed only in a time window of a predetermined width for the pulse train arriving at the neuron. The means for realizing the weighted addition within the time window is not limited to the neuron element circuit shown in FIG. 2, and it goes without saying that it may be realized by other methods.

This time window corresponds to the refractory period of the actual neuron.
(refractory period) It corresponds to the time zone to some extent. In other words, there is no output from the neuron regardless of any input during the refractory period (time range other than the time window), but the firing according to the input level occurs in the time window other than that time range. Is similar to the neuron. FIG.
The refractory period shown in (B) is a time period from immediately after the firing of the feature detection cells to the next time window start time. Needless to say, the length of the refractory period and the width of the time window can be arbitrarily set, and the refractory period does not have to be shorter than the time window as shown in FIG.

In the present embodiment, as the mechanism already described, for example, for each feature detection layer neuron, the input of the synchronization detection signal by the phase detection means which receives the input from the same receptive field causes the above-described start timing. It brought commonality.

In the case of such a configuration, it is not necessary to perform the synchronization control of the time window (if it is necessary) over the entire network, and there is fluctuation or fluctuation of the timing signal as described above. Is also uniformly affected by the output from the local receptive field (the fluctuation of the position of the window function on the time axis is the same between neurons forming the same receptive field). The reliability of detection does not degrade. Since a highly reliable synchronous operation is enabled by such local circuit control, the tolerance of variation regarding circuit element parameters is also increased.

Hereinafter, a feature detecting neuron for detecting a triangle as a feature will be described for simplicity. The feature integration layer at the preceding stage provides L-shaped patterns (f ₁₁ , f ₁₂ ,...) Having various orientations as shown in FIG. 7C, and continuity (connectivity) with the L-shaped pattern. Line segment combination pattern (f
₂₁ , f ₂₂ ,...), A combination of two sides forming a triangle (f ₃₁ ,...), And the like.

Also, f ₄₁ , f ₄₂ , and f _{43 in} the figure are features constituting triangles having different directions, and indicate features corresponding to f ₁₁ , f ₁₂ , and f ₁₃ . As a result of setting a specific delay amount between neurons forming interlayer connection by learning, in a triangular feature detection neuron, each sub time window (time slot) (w ₁ , w ₂ , ...)
The setting is made in advance so that the pulses corresponding to the main and different features constituting the triangle arrive.

For example, w ₁ , w ₂ ,
, W _n , as shown in FIG. 7A, a pulse corresponding to a combination of a set of features that constitutes a triangle as a whole arrives first. Here, the L-shaped pattern (f ₁₁ ,
f ₁₂ , f ₁₃ ) arrive within w ₁ , w ₂ , w ₃ respectively, and the feature element
pulse corresponding to _{(f 21, f 22, f} 23) , respectively w _1, w _2, w ₃
The amount of delay is set by learning so as to arrive within.

The pulses corresponding to the characteristic elements (f ₃₁ , f ₃₂ , f ₃₃ ) arrive in the same order. In the case of FIG. 7A, a pulse corresponding to one characteristic element arrives in one sub time window (time slot). The meaning of dividing into sub time windows is
By individually and reliably detecting pulses (detection of feature elements) corresponding to different feature elements developed and expressed on the time axis in each sub time window, an integration method when integrating those features, For example, it is to increase the possibility of change and adaptability of the processing mode, such as whether to detect all characteristic elements or to detect a certain percentage of features.

For example, the recognition (detection) target is a face,
In situations where the eye search (detection), which is a part of it, is important (when the priority of eye pattern detection is to be set high in visual search), feedback coupling from a higher-order feature detection layer By introducing
It is possible to selectively enhance the reaction selectivity (detection sensitivity of a specific feature) corresponding to the feature element pattern constituting the eye. By doing so, it is possible to give higher importance to lower-order feature elements constituting higher-order feature elements (patterns) and detect them.

[0157] Further, if it is set in advance that a pulse arrives in a sub-time window as soon as an important feature is reached, the weight function value in the sub-time window must be larger than the value in the other sub-time windows. Thereby, the feature having a higher importance can be more easily detected. This importance (detection priority between features) can be obtained by learning or can be defined in advance.

Therefore, as long as it is only necessary to detect a certain percentage of characteristic elements, the division into sub-time windows has little meaning, and may be performed in one time window.

Note that a plurality (three) different characteristic elements are
The corresponding pulses arrive and add up
(FIG. 7D). That is, one sub time window (time
Slot) with multiple feature elements (Fig. 7 (D)) or optional
Before the pulses corresponding to the number of feature elements are input
It may be a stake. In this case, in FIG.
In the time window, the vertex of the triangle f₁₁Support detection of
Other characteristic element f₂₁, F₂₃The pulse corresponding to arrives
Similarly, in the second sub-time window, the vertex angle portion f ₁₂Inspection
Other features f that support₂₂, F₃₁Pal
Has arrived.

The number of divisions into sub-time windows (time slots), the width of each sub-time window (time slot), the class of the feature, and the assignment of the pulse time interval corresponding to the feature are not limited to those described above. Needless to say, it can be changed.

Application Example Installed in Photographing Apparatus When the pattern recognition (detection) apparatus according to the configuration of the present embodiment is installed in the photographing means, focusing on a specific subject, color correction of the specific subject, and exposure control are performed. Will be described with reference to FIG. FIG. 12 is a diagram illustrating a configuration of an example in which the pattern detection (recognition) device according to the embodiment is used for an imaging device.

An image pickup apparatus 1101 shown in FIG. 12 includes an image forming optical system 1102 including a photographing lens and a drive control mechanism for zoom photographing.
D or CMOS image sensor 1103, imaging parameter measurement unit 1104, video signal processing circuit 1105, storage unit 1106, control signal generation unit 1107 that generates control signals such as control of imaging operation, control of imaging conditions, and viewfinders such as EVF And a recording medium 1110, and the above-described pattern detection device as a subject detection (recognition) device 1111.

The image pickup apparatus 1101 detects a face image of a person registered in advance (detection of the position and size of a person) from a captured image by a subject detection (recognition) apparatus 1111. When the position and size information of the person is input from the subject detection (recognition) device 1111 to the control signal generation unit 1107, the control signal generation unit 1107
Focus control for that person based on the output from 04,
A control signal for optimally controlling exposure condition control, white balance control, and the like is generated.

As a result of using the above-described pattern detection (recognition) device for an image pickup device, the subject can be reliably detected.
(Recognition) function with low power consumption and high speed (real time)
Thus, it is possible to perform detection of a person or the like and optimal control of photographing based on the detection (AF, AE, etc.).

(Second Embodiment) This embodiment is different from the first embodiment only in the items of the operation principle of pattern detection and phase synchronization.

Therefore, in the present embodiment, the above items will be described, and the other functions and operations are the same as those in the first embodiment, and the description will be omitted.

First, as shown in FIG. 6, the phase synchronization circuit of this embodiment receives an output signal from the feature integration layer neuron, detects the phase synchronization of the output signal, and controls the switches 1 and 2. And a synchronization detecting means for outputting a synchronization detection signal, and a phase synchronization signal generating circuit interconnected with the feature integration layer neuron.

The processing flow in the above configuration will be described step by step.

First, when the feature integration layer neuron receives an output from the preceding stage and fires and outputs, the output signal is input to the phase synchronization signal generation circuit in the phase synchronization circuit via the amplifier.

The phase synchronization signal generating circuit is composed of a neuron element circuit as shown in FIG.
Upon receiving at least one of the inputs, a phase synchronization signal is output to the feature integration layer neuron (at this time,
The switch 2 in FIG. 6 is conducting.)

Here, assuming that the threshold characteristic of the phase synchronization signal generation circuit has a predetermined value, the output from the feature integration layer neuron is once passed to an amplifier so that the phase synchronization signal generation circuit can fire with one pulse. Amplify.

Subsequently, the phase synchronization signal output by the firing of the phase synchronization signal generation circuit is input to the feature integration layer neuron. Here, the phase synchronization signal finally received by the feature integration layer neuron is obtained. The level is set so that the output pulse of the phase synchronization signal generation circuit is input to the amplifier to amplify the signal level, and the internal potential of the feature integration layer neuron can reach the threshold value within the allowable phase difference.

Here, the allowable phase difference corresponds to the width of the phase synchronization detection window in FIG. 16. As will be described later, the phase synchronization detection means operates the feature integration layer neuron input in the phase synchronization detection window. By the integrated value of the output signal from
Detect phase synchronization.

Upon receiving the phase synchronization signal, the feature integration layer neuron exceeds the firing threshold level by the phase synchronization pulse signal in any internal state, except in a refractory period.

Here, as shown in FIG. 15B, due to the difference in the internal state of each feature integration layer neuron at the time when the phase synchronization pulse signal is input, the firing phase of the feature integration layer neuron becomes Although a slight difference occurs, as described above, the phase synchronization signal level is set so that the phase difference is equal to or less than the allowable phase difference. Have a phase difference within the allowable phase difference, and are in a synchronized state.

Further, the above-described operation is repeated until the feature integration layer neuron, which has been in the refractory period in the above-described operation, receives the phase synchronization signal at a timing other than the refractory period and fires, and finally all the features are obtained. The output of the integrated layer neuron can be synchronized.

Next, a description will be given of a phase synchronization detecting means for detecting the above-mentioned phase synchronization state.

As shown in FIG. 6, the phase synchronization detecting means receives the output of the feature integration layer neuron as an input signal.

Here, as shown in FIG. 14 (A, C),
The phase synchronization detecting means has a configuration similar to that of the feature integration layer neuron described in the section of the aforementioned neuron element, and outputs an input value in the phase synchronization detection window having a predetermined time determined by the phase synchronization detection window generating circuit. Integrates, fires when the value exceeds the threshold, and outputs.

Therefore, the time width of the phase synchronization detection window is set to an allowable phase difference when the above-mentioned feature integration layer neurons are phase-synchronized, and the outputs of all feature integration layer neurons that combine firing thresholds are set. By setting this value to the integral value, it becomes possible to detect the phase synchronization of the feature integration layer neuron.

That is, as shown in FIG. 16, by setting the allowable phase difference as the phase synchronization detection window, when the outputs of all the feature integration layer neurons are synchronized, the phase synchronization detection means in the neuron element circuit in the phase synchronization detection means Since the input integrated value within the synchronization detection window reaches the threshold value and fires, as a result, the synchronization firing of the feature integration layer neuron can be detected.

Next, the operation after the phase synchronization is detected will be described.

As shown in FIG. 14A, the phase synchronization detecting means includes a switch control signal generating circuit for generating a switch control signal according to the output of the neuron element circuit, and a synchronous detection signal according to the output. A synchronization detection signal generating circuit.

When the phase synchronization detecting means detects the phase synchronization of the feature integrated layer neuron by firing of the neuron element circuit as described above, the switch control signal generation circuit which receives the output of the neuron element circuit outputs a switch control signal. Then, the switch 2 is switched to the cutoff state (conduction state until phase synchronization is detected), and the output of the phase synchronization signal from the phase synchronization signal generation circuit to the feature integration layer neuron is stopped.

At the same time, by switching the switch 1 to the conducting state (the blocking state until the phase synchronization is detected), the output of the feature integration layer neuron is subjected to the processing of the synapse circuits S1 to S4 in FIG. Input to the feature detection layer neuron.

Here, the output signal of the feature integration layer neuron input to the feature detection layer neuron is purely the input of the phase synchronization signal to the feature integration layer neuron by the above-described switching operation. It becomes an output signal by firing according to the input from the previous layer of the neuron.

Further, the phase synchronization detection means outputs a synchronization detection signal to the feature detection layer neuron by the synchronization detection signal generation circuit receiving the output of the neuron element circuit,
A reference time for the generation timing of a time window described later is given.

In this case, by calculating in advance the time required for the output from the feature integration layer to arrive at the feature detection layer, the relationship between the synchronization detection signal and the time window generation timing can be appropriately set. Becomes possible.

In this embodiment, the synchronization detection signal is a pulse-like signal, and the time when the signal is input to the feature detection layer neuron is set as the start point of the time window.

In the above-described phase synchronization processing, the integrated layer neuron corresponding to the overlapping receptive field receives a plurality of different phase synchronization signals, but the integrated layer neuron corresponding to the overlapping receptive field receives the input from the preceding layer. input,
Alternatively, even if any one of the inputs from the phase locked loop causes firing, the output pulse is simultaneously input to a plurality of phase locked loops, so that the phases of the plurality of phase locked loops are synchronized at that time.

Therefore, a plurality of phase synchronization signals are input to the feature integration layer neuron corresponding to the subsequent overlapping receptive field portion in a state where the respective phases are synchronized.
The process of establishing the phase synchronization of the feature integration layer neuron follows the same process as the case of the above-described single phase synchronization signal.

As described above, even when the feature integration layer neuron corresponding to the overlapping receptive field receives a plurality of phase synchronization signal inputs, it is possible to stably and consistently establish the output phase synchronization.

In particular, in the phase synchronizing signal generating circuit, when the time interval from the input of the signal to the output of the phase synchronizing signal is set to a time interval longer than the refractory period of the feature integration layer neuron, When the next phase synchronization signal is input, the feature integration layer neuron that did not fire because it was input during the refractory period can fire and output in phase synchronization with the other feature integration layer neurons. It is possible to shorten the time until

Next, the operation of the feature detection layer neuron after the phase synchronization of the output of the feature integration layer neuron is detected will be described.

When a synchronization detection signal is input to the feature detection layer neuron from the phase synchronization detection means, a time window is generated by the synchronization detection signal as described above.

Here, the time window is the feature detection layer neuron.
(n'i), which is common to each neuron in the feature integration layer that forms the same receptive field for the neuron, and gives a time range of time window integration.

The synchronization detecting means at the layer number (1, k) (k is a natural number) outputs a pulse output as a synchronization detection signal to the feature detection layer neuron (layer number (1, k)) to perform feature detection. The layer neuron provides a timing signal for generating a time window when the input is temporally added. The start time of this time window is a reference time for determining the arrival time of the pulse output from each integrated cell. That is, the synchronization detection means gives a pulse output time from the feature integration layer neuron and a reference pulse for time window integration in the feature detection cell.

Each pulse is given a predetermined amount of phase delay when passing through the synapse circuit, and further, reaches a feature detecting cell through a signal transmission line such as a common bus. The arrangement of the pulses on the time axis at this time is indicated by the pulses (P ₁ , P ₂ , P ₃ ) indicated by dotted lines on the time axis of the feature detection cells.

Each pulse (P ₁ , P
₂ , P ₃ ) time window integration (usually one integration; however, charge accumulation by multiple time window integrations or averaging of multiple time window integrations may be performed) As a result, when it becomes larger than the threshold value, a pulse output (P _d ) is made based on the end time of the time window. Note that the learning time window shown in the figure is referred to when a learning rule described later is executed.

Subsequently, when the calculation operation described later is completed in the feature detection layer neurons as described above, the switch 2 returns to the conducting state again, and the output of the phase synchronization signal generation circuit is passed through the amplifier to integrate the features. Input to layer neurons.

The switch 1 returns to the cutoff state again,
The input from the feature integration layer neuron to the feature detection layer neuron stops.

In the present embodiment, the switching operation of the switches 1 and 2 is set in advance so that the switch control signal is output from the switch control signal generation circuit after a predetermined time from the previous switching operation. It is realized by doing.

The operation of the switches 1 and 2 here can be performed by using other control means. However, since the operation is not related to the main point of the present invention, the description is omitted.

As described above, by setting the signal level of the phase synchronization signal output from the phase synchronization circuit so that the neurons of the feature integration layer are fired within the allowable phase difference, the feature integration layer can be shortened in a shorter time. It becomes possible to establish phase synchronization of neurons.

(Third Embodiment) FIG. 8 shows a configuration example of a phase locked loop circuit and other neurons (a neuron group of a feature integration layer and a detection layer) connected to the phase locked loop circuit in the present embodiment.
The input from the preceding layer to the feature integration layer neuron is shown by a thin line, the input from the feature integration layer neuron to the feature detection layer neuron is shown by a dotted line, the mutual connection between the feature integration layer and the phase locked loop is shown by a thick line, and the switch control signal Is indicated by a thin line.
The synapse circuit and the synchronization detection signal are omitted).

The phase synchronization circuit has a feature detection layer neuron for detecting the same feature category. One neuron exists for each group obtained by dividing the number by a predetermined number, and an independent phase synchronization signal is generated. Is different from the second embodiment.

In this way, the repetitive receptive field structure of the feature integration layer between adjacent feature detection layer neurons is eliminated (the feature integration layer neuron receives only a phase synchronization signal from one phase synchronization circuit). , The number of phase synchronization circuits and the number of phase synchronization detection means can be reduced.

In the present embodiment, the synchronization detection signal of the phase synchronization circuit is generated independently of the other phase synchronization circuits when the synchronization detection means detects the synchronous firing of the feature integration layer neuron.

FIG. 9 shows the pulse output timing of each neuron corresponding to FIG. 8 showing the processing steps described above.

In FIG. 9, the feature integration layer neurons (N
_{1I to} N _6I ) are fired by the output of the feature detection neuron, which is the preceding layer, and when they are output, a phase synchronization signal is output from the phase synchronization signal generation circuit. In the feature integration layer neuron to which the phase synchronization signal has been input, the phase synchronization of the output within the phase synchronization detection window is detected by the phase synchronization detection means through the above-described phase synchronization process.

When the phase synchronization of the output of the feature integration layer neuron is detected by the phase synchronization means, a synchronization detection signal is output to the feature detection layer neurons (N ′ _{2D to} N ′ _3D ).

As a result, the calculation based on the time window is performed in the feature detection layer neuron, and an output is performed according to the calculation result.

Here, the output of the phase synchronization signal generation circuit is:
When the time integration value of the input pulse within the phase synchronization detection time window (shown in FIG. 9) exceeds a predetermined threshold value, the operation is performed independently of the other phase synchronization circuits.

As described above, the phase locked loop circuit generates one independent phase locked signal for each group obtained by dividing the feature detection layer neuron for detecting the same feature category into a predetermined number. With such a configuration, it is possible to reduce the circuit scale and power consumption.

(Fourth Embodiment) FIGS. 10 (A), (B) and 11 show examples of the configuration relating to the coupling centering on the phase synchronization circuit and the phase synchronization detecting means in this embodiment.
The input from the feature integration layer neuron to the feature detection layer neuron is indicated by a dotted line, the phase synchronization signal is indicated by a thin line, the interconnection between the feature integration layer and the phase synchronization circuit is indicated by a thick line, and the interconnection between the feature integration layer and the WTA circuit is indicated by a thick line. The thin lines indicate the mutual coupling between the phase locked loop circuit and the WTA circuit, and the switch control signals are indicated by the thin lines. Also, the input from the preceding layer to the feature integration layer neuron, the synapse circuit, and the synchronization detection signal are omitted. ).

As a representative position of the feature detection layer neuron group obtained by dividing the phase locked loop in the same manner as in the third embodiment, for example, a neuron located at the center of gravity or its nearest neighbor
A pulse signal is received only from the feature integration layer neuron input to (N3I), and a phase synchronization signal is generated under predetermined conditions.

In FIG. 10A, N ′ is located at the position of the center of gravity of the neuron group of the feature detection layer connected to the phase locked loop.
_2D , the feature integrated layer neurons N _1I , N to which N ' _2D connects
_2I, N _{3 I,} N _4I is a mutual coupling and phase synchronization circuit (indicated by binding a thick arrow). With this configuration, the number of wires required for mutual coupling is reduced as compared with the third embodiment. Further, even if the above-described wiring is reduced, the operation problem (because a plurality of phase-synchronous signals are asynchronously input, the phase-locked circuit generates an independent phase-locked signal and eliminates the overlapping receptive field structure). There is no occurrence of a time window generation timing shift between the phase locked loop and the feature detection layer.

Similarly, in the configuration shown in FIG.
It is N 'that interconnects with the synchronous circuit. _2DReceive input
Near the center of gravity of the neuron group
One of the neurons (N_3I) Only. Such a configuration is
This leads to a further reduction of wiring for coupling. Also rank
The phase synchronizing circuit integrates the features to receive the input in FIG.
Out of the layer neurons
It can also be configured to receive only input. For example,
In the configuration shown in FIG. 11, the feature integration layer neuron group and the phase
The so-called Wi that detects the maximum output between the synchronous circuit
Set nner-Take-All circuit (WTA circuit)
And the phase locked loop receives the output from the WTA circuit.
I did it. The feature integration layer neuron group and the feature detection layer
The connection with the iron group is the same as in FIGS. 10 (A) and 10 (B).
In this way, a local area within a predetermined range on input (image) data
Feature integrated layer neuron that detects the most prominent features in the region
By performing local timing control based on the output from the
And stable parallel pulse signal processing with smaller circuit scale
Operation is realized.

[0219]

As described above, according to the present invention, in the signal processing circuit, there is an effect that the synchronous operation can be stably realized without contradiction without increasing the circuit scale and the power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing the overall configuration of a network according to the present invention.

FIG. 2 is a diagram showing a configuration of a synapse section and a neuron element section and a circuit configuration of a neuron element.

FIG. 3 is a diagram showing how multiple pulses propagate from a feature integration layer (or an input layer) to a feature detection layer neuron.

FIG. 4 is a diagram showing a configuration diagram of a synapse circuit.

FIG. 5 is a diagram showing a configuration of a synapse coupling small circuit and a configuration of a pulse phase delay circuit used in the first embodiment.

FIG. 6 is a schematic diagram illustrating an example of a coupling structure of a phase locked loop according to a second embodiment.

FIG. 7 shows a configuration of a time window when processing a plurality of pulses corresponding to different feature elements input to the feature detection neuron,
It is a figure which shows the example of a weight function distribution, and the example of a characteristic element.

FIG. 8 is a schematic diagram of a coupling structure centering on a phase locked loop circuit according to a third embodiment.

FIG. 9 is a diagram showing pulse firing timing of each neuron.

FIG. 10 is a schematic diagram of a coupling structure centering on a phase locked loop circuit according to a fourth embodiment.

FIG. 11 is a schematic diagram of a coupling structure centering on a phase locked loop circuit according to a fourth embodiment.

FIG. 12 is a diagram illustrating a configuration example of a photographing device equipped with a pattern recognition device.

FIG. 13 is a schematic diagram of an example of a coupling structure in a phase synchronization step according to the first embodiment.

FIG. 14 is a diagram illustrating a block configuration of a phase synchronization circuit.

FIG. 15 is a diagram showing an example of a coupling structure centering on input and output of a phase synchronization signal and a firing process by the phase synchronization signal.

FIG. 16 is a diagram showing pulse firing timing of each neuron.

Continued on the front page (72) Inventor Katsuhiko Mori 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term (reference) in Canon Inc. 5B057 AA01 BA02 CH04 CH08 DA11 DC40

Claims (13)

[Claims] 1. A plurality of arithmetic elements which are connected in parallel with each other based on a predetermined rule, perform a predetermined operation on an input signal and output a signal, and A phase synchronization signal generation circuit that outputs a synchronization signal; and synchronization detection means that detects synchronization within an allowable phase difference between outputs of the arithmetic element in a predetermined vicinity. A signal processing circuit that also functions as an arithmetic element that performs the predetermined operation and outputs the result according to a synchronization detection result of the means. 2. The method according to claim 1, wherein the phase synchronization signal generating circuit is configured to:
2. The signal processing circuit according to claim 1, wherein the signal processing circuit outputs a phase synchronization signal. 3. The signal processing circuit according to claim 1, wherein an output of the phase synchronization signal generation circuit is a pulse signal. 4. The method according to claim 1, wherein the arithmetic element in the vicinity of the predetermined has a refractory period, and the time interval from the input of the signal to the output of the phase synchronization signal in the phase synchronization signal generating circuit is the predetermined time interval. 4. The signal processing circuit according to claim 3, wherein the signal processing circuit has a time interval equal to or longer than a refractory period of a nearby operation element. 5. An output of a phase synchronization signal output from the phase synchronization signal generating circuit to the predetermined neighboring arithmetic element, wherein a phase difference between output signals from the predetermined neighboring arithmetic element is equal to the allowable value. 5. The signal processing circuit according to claim 1, wherein the signal processing is controlled so as to be within a phase difference. 6. A phase difference between output signals of said predetermined neighboring arithmetic elements when said predetermined neighboring arithmetic elements have a refractory period, and said phase difference between said output signals of said predetermined neighboring arithmetic elements is other than the refractory period of said arithmetic elements. 6. The signal processing circuit according to claim 5, wherein the difference is within the allowable phase difference. 7. The signal processing circuit according to claim 1, wherein said synchronization detecting means includes an arithmetic element for outputting an output according to an integral value of an input signal. 8. A plurality of arithmetic elements which are connected to each other in accordance with a predetermined rule and arranged in parallel, perform a predetermined operation on an input signal and output the same, A phase synchronization signal generation circuit that outputs a synchronization signal; and a synchronization detection unit that detects synchronization within an allowable phase difference between outputs of the arithmetic element in a predetermined vicinity, and the predetermined proximity from the phase synchronization signal generation circuit. Wherein the output of the phase synchronization signal output to the arithmetic element is controlled such that the phase difference between the output signals from the predetermined adjacent arithmetic elements is within the allowable phase difference. Signal processing circuit. 9. The phase difference between the output signals of the predetermined neighboring arithmetic elements having a refractory period, and the phase synchronization signal being input in a period other than the refractory period of the arithmetic elements. 9. The signal processing circuit according to claim 8, wherein the difference is within the allowable phase difference. 10. The phase synchronization signal generation circuit according to claim 8, wherein the phase synchronization signal generation circuit outputs a phase synchronization signal in accordance with a time series signal input from the predetermined neighboring arithmetic element. Signal processing circuit. 11. The signal processing circuit according to claim 8, wherein the synchronization detecting means is an arithmetic element that outputs an output according to an integrated value of an input signal. 12. An output of the phase synchronization signal generation circuit,
The signal processing circuit according to claim 8, wherein the signal processing circuit is a pulse signal. 13. The method according to claim 1, wherein the arithmetic element in the vicinity of the predetermined period has a refractory period, and the time interval from the input of the signal to the output of the phase synchronization signal in the phase synchronization signal generation circuit is the predetermined time interval. 13. The signal processing circuit according to claim 12, wherein the signal processing circuit has a time interval equal to or longer than a refractory period of a neighboring arithmetic element.