JP2002354071A - Portable telephone and its circuit for processing sound source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the power consumption of a portable telephone and its circuit for processing sound source lowered. SOLUTION: Operational frequencies of a sound source processing circuit 30 for enabling multiple sounds to be simultaneously reproduced are varied according to the number of sound under reproduction. Aside from the case such that the specified number of sound to be reproduced is in maximum, this allows often the operation at frequencies lower than the maximum frequency and the required number of sound is still simultaneously reproduced, so that the increase of the consumption power is comparatively avoided even if the maximum number of sound of capable being simultaneously reproduced is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a portable telephone device and a sound source processing circuit incorporated therein, and more particularly, to a portable telephone device capable of simultaneously reproducing a plurality of sounds. Such a sound source processing circuit is also used in an electronic sound synthesis output device such as an electronic musical instrument and an acoustic synthesizer, and is particularly suitable for being incorporated in a battery-driven portable device. It should be noted that the mobile phone device in this specification includes a PHS (Personal Handyphone System) in addition to an analog or digital mobile phone.
m) and a handset serving as a slave unit when wireless communication is performed with a fixed telephone set as a base unit.

[0002]

2. Description of the Related Art In many mobile phones, a ring tone function, that is, a function of selecting or changing a melody of a ring tone is provided as a standard feature, and its performance has been improved. The number of sounds that can be played is also increasing. For example, recently, the maximum number of sounds that can be simultaneously reproduced and synthesized from 3 chords to 16 chords has increased, and the number of sounds is expected to increase in the future. With such performance improvement, the sound source processing circuit for that purpose is integrated into a one-chip IC, and a clock corresponding to the highest operating frequency is supplied.
The maximum number of sounds can be produced at any time.

[0003]

By the way, in such a sound source processing circuit, as the maximum number of simultaneously reproducible sounds increases, the maximum operating frequency also increases, and the circuit always operates at that frequency. Also increase almost in proportion. However, in devices that operate on battery power, such as mobile phones, reducing power consumption is a paramount proposition.

[0004] Therefore, it is important to devise so that the power consumption does not increase even if the maximum number of sounds that can be simultaneously reproduced increases, or the increase does not need to increase much. The present invention has been made to solve such a problem, and an object of the present invention is to realize a portable telephone device and a sound source processing circuit with low power consumption.

[0005]

Means for Solving the Problems First to fourth solving means invented to solve such problems are as follows.
The configuration and operation and effect will be described below.

[First Solution] A portable telephone device according to a first solution is a portable telephone device provided with a sound source processing circuit capable of simultaneously reproducing a plurality of sounds as described in claim 1 of the present application. The operating frequency of the sound source processing circuit is varied according to the number of sounds being reproduced.

[0007] The sound source processing circuit of the first solving means is as follows.
As described in claim 2 at the time of filing the application, storage means for holding one or a plurality of sound source data, and selecting the same or different one from the sound source data based on the input audio data to simultaneously perform a plurality of sounds. A sound source processing circuit comprising a reproducing means and a frequency varying means for varying an operating frequency of the computing means in accordance with the number of sounds being reproduced. Alternatively, as described in claim 3 at the beginning of the application, in addition to the above, dividing means for inputting the audio data and dividing the sound for each sound is provided upstream of the arithmetic means, and the operating frequency thereof is also the frequency variable means. Is to be made variable.

In the portable telephone device and the sound source processing circuit of the first solution, at least the operating frequency of the main part of the sound source processing circuit can be changed according to the number of sounds being reproduced. Aside from the maximum number of sounds specified to be required, they often operate at frequencies below the maximum operating frequency, and the required number of sounds will still be properly synchronized It will be played. As a result, even if the maximum number of sounds that can be reproduced simultaneously increases, the power consumption does not need to increase for that. Therefore, according to the present invention, a portable telephone device and a sound source processing circuit with low power consumption can be realized.

[Second Solving Means] The sound source processing circuit of the second solving means is the sound source processing circuit of the first solving means as described in claim 4 at the time of filing the application. Means for setting a frequency division value in the feedback unit;
A phase locked loop incorporating a frequency dividing circuit is provided, and the frequency dividing value of the first frequency dividing circuit is updated when the frequency is changed.

In the sound source processing circuit of the second solving means, a process of changing a frequency such as a variable clock for determining an operating frequency can be easily performed by updating a frequency division value.
In addition, based on the characteristics of the phase locked loop, the frequency of the variable clock or the like is higher than the predetermined frequency of the original basic clock or the like corresponding to the frequency division value. Therefore, it is possible to use a base clock or the like that supports the lowest operating frequency. On the other hand, if the conventional means for simply dividing the frequency of the basic clock to generate the variable clock is employed, the basic clock must be compatible with the highest operating frequency. This allows
Up to the operating frequency of the clock generation circuit and the oscillation circuit that generate the basic clock etc. before the change, the number of sounds that can be reproduced simultaneously is released from the increase and the frequency remains low, so that the power consumption of that circuit can be reduced. Becomes Therefore,
According to the present invention, a sound source processing circuit with lower power consumption can be realized.

[Third Solution Means] The sound source processing circuit of the third solution means is the sound source processing circuit of the first and second solution means as described in claim 6 at the beginning of the application. In addition to the storage unit and the arithmetic unit or the dividing unit, the frequency variable unit is also mounted on one semiconductor integrated circuit device.

In the sound source processing circuit according to the third aspect of the present invention, since a specific frequency varying means is incorporated in the semiconductor integrated circuit device, even if the maximum number of simultaneously reproducible sounds increases. This can be dealt with by internal modification of the semiconductor integrated circuit device, and compatibility is maintained with respect to external circuits and surrounding circuits. This makes it easy to extend the maximum number of sounds that can be reproduced simultaneously by improving the sound source processing circuit independently. Therefore, according to the present invention, a sound source processing circuit that consumes less power and can be easily expanded can be realized.

[Fourth Solution Means] The sound source processing circuit of the fourth solution means is the sound source processing circuit of the second and third solution means. Wherein the frequency variable means further comprises another second frequency dividing circuit capable of setting a frequency dividing value even at a position out of the phase locked loop, wherein the second frequency dividing circuit is used to vary the frequency. The division value of the circuit is also updated.

In the sound source processing circuit of the fourth solving means, when the frequency of the variable clock or the like is varied, the frequency can be easily updated by updating the divided values of the first and second frequency dividing circuits. The frequency of the variable clock or the like is obtained by dividing the frequency of the basic clock or the like by an integral multiple of the frequency of the first frequency divider by the frequency of the second frequency divider. As a result, a variable clock having a frequency not only an integer multiple but also a rational multiple is generated from the basic clock or the like, so that power consumption can be finely reduced. Therefore, according to the present invention, a sound source processing circuit with even lower power consumption can be realized.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In addition to the portable telephone device of the present invention achieved by such a solution, the electronic sound synthesizing output device incorporating the above sound source processing circuit is equipped with a disposable or rechargeable battery. It is preferable that at least the sound source processing circuit operates by being supplied with power from a battery. It is also good to make it possible to switch between such driving with a battery and driving with commercial power.

A portable telephone device and a sound source processing circuit according to the present invention achieved by the above-described means and embodiments are described below.
Specific embodiments for implementing this will be described with reference to the following first to fourth embodiments. The first embodiment shown in FIGS. 1 and 2 employs the above-described first to third solving means (first claim 1).
, 4 and 6), and the second embodiment shown in FIG.
The embodiment embodies the above-described fourth solution (initially claim 5), and the third embodiment shown in FIG. 4 and the fourth embodiment shown in FIG. -This is an application example.

[0017]

First Embodiment A first embodiment of a portable telephone device and a sound source processing circuit according to the present invention will be described with reference to the drawings. FIG. 1 shows the entire configuration,
(A) is a right side view, (b) is a front view, and (c) is an entire block diagram of an electronic circuit. FIG. 2 is a detailed block diagram of a part of the electronic circuit. FIG. 2A shows a sound source processing circuit, and FIG. 2B shows a PLL circuit.

This mobile phone 10 (mobile phone device)
It comprises a telephone body 14 capable of wireless communication and a battery pack 17 which can be mounted on the back thereafter (FIG. 1 (a)).
reference). The telephone main body 14 (see FIG. 1B) has an antenna 11 implanted on the upper end surface, and a speaker 12 on the front side.
(Sound output means), a liquid crystal display 13 (display means), a keyboard 15 (operation means), a microphone 16 (speech input means), and the like are provided so that it is easy to make a telephone call or dial. The battery pack 17 has a built-in rechargeable NiCd battery, lithium ion battery, or the like, and supplies power to an electronic circuit 20 in the telephone body 14.

The electronic circuit 20 (see FIG. 1C)
A wireless communication circuit 21 including a modulation / demodulation means for performing transmission and reception with a base station or the like wirelessly via an antenna 11
Is provided, and a keyboard interface (KBD-I /
F) 25 is provided, and a microphone 16
A voice input circuit 26 having A / D conversion means and the like is provided for picking up and inputting the data. In addition, the electronic circuit 20 appropriately controls and drives these circuits and the like in order to support calls between speakers, and also performs various arithmetic and sequence processes such as necessary communication procedures and call processing. CPU to execute
24 is also included. An oscillation circuit 22 for generating a system clock and the like supplied to the CPU 24 and the like is also provided.

Further, the electronic circuit 20 has a read / write access by the CPU 24 in order to hold its own telephone number and some telephone numbers to be automatically dialed, and to temporarily store data accompanying various calculations and controls. Internal memory 2 consisting of flash memory, RAM, etc.
3 is also built in. Audio data such as a ringing melody is also stored and held in the internal memory 23. The audio data is held in the internal memory 23 in a predetermined data format, for example, in a format similar to or similar to MP3 of the MIDI standard or the MPEG standard, and is read out by the CPU 24 in order to generate the audio data stream A. Has become.

The electronic circuit 20 is also provided with a sound source processing circuit which, when a digital audio data stream A is successively delivered from the CPU 24, performs an operation of a reproducing process and the like to generate an analog sound output signal B in accordance with the digital audio data stream A. The sound output signal B is transmitted to the speaker 12, and a reproduced sound such as a ring tone is emitted.
The sound source processing circuit is collectively mounted on a one-chip LSI 30, and the sound source processing LSI 30 receives the audio data stream A and the basic clock f and outputs a sound output signal B. This sound source processing LSI
The basic clock f supplied to 30 is also generated by the oscillation circuit 22, and has a constant frequency.

In the sound source processing LSI 30 (see FIG. 2A), as an input means and a dividing means, an F for inputting and buffering the audio data stream A sequentially.
An FIFO 31; a sequencer 32 for sequentially reading out the audio data stream A from the FIFO 31 while measuring the timing based on the tempo data and the like included in the header part of the audio data, and dividing the data for each sound; And a RAM 33 arranged and stored in an array area or the like so as to be easily distinguished and updated. For example, note data of a triad is divided into three sound data of a high tone, a middle tone, and a low tone, and is written separately in three vacant channels in the array area.

The sound source processing LSI 30 has a non-volatile sound source ROM as storage and holding means for holding sound source data.
34 is provided, in which sound source data obtained by digitizing and compressing a basic waveform such as a musical instrument sound is stored. The sound source data is basic waveform data for determining the timbre and the like of each sound, and thus may be one or more. The accompanying information, other management data, fixed parameters, and the like are also stored and held in the sound source ROM 34.

Further, the sound source processing LSI 30 is also provided with a DSP 35 (digital signal processor) as arithmetic means, which selects and reads out sound source data from a sound source ROM 34 based on sound data developed in a RAM 33. A dynamic attribute such as intensity and length is also given to the timbre to reproduce a desired sound signal. The operation of the reproduction process is repeated at least for the number of effective channels during one cycle time.
That is, the same or different sound source data is read out in parallel from the sound source ROM 34 by the same number of times as the number of sound data expanded in the RAM 33 and not yet deleted, that is, the number n of sounds being simultaneously reproduced. The number of sound sources at the time is equal to, but the reproduction process is repeatedly performed by that number.
Then, a digital signal generated by adding the calculated values of these sounds is converted into an analog sound output signal B by the D / A conversion circuit 36 also serving as an amplifier.

The sound source processing LSI 30 is also provided with a PLL circuit 40 (phase locked loop) as frequency varying means. The PLL circuit 40 includes the sequencer 32 and D
In order to vary the operating frequency of the SP 35, a variable frequency variable clock nf is generated from the fixed frequency base clock f, and the oscillation signal is supplied to the sequencer 32 and the DSP 35 as a clock. As will be described later in detail, the frequency of the variable clock nf is set to be n times higher than the basic clock f. As the multiple n, the above-mentioned simultaneous reproduction sound number n is adopted by the sequencer 32, and each time the simultaneous reproduction sound number n changes or whenever necessary, the sequencer 32
Is sent to the PLL circuit 40, and the multiple n is updated.

The circuit structure of the PLL circuit 40 will be described in detail (see FIG. 2B). The phase comparison circuit 41 inputs the basic clock f and the feedback of the variable clock nf, and smoothes the output. Loop filter 42
And a VCO 43 (voltage controlled oscillation circuit) using the output voltage as a control signal, and a variable clock n output from the VCO 43
f includes a counter 44 interposed and connected to a line fed back to the phase comparison circuit 41. The counter 44 is a p-adic counter that counts the variable clock nf and sends a carry to the phase comparison circuit 41. When the number n of simultaneously reproduced sounds is sent from the sequencer 32, the value n
, The value of p is changed. This allows
The counter 44 divides the variable clock nf by the frequency division value p (first frequency division circuit), and the PLL circuit 40 incorporating the frequency division number p in the feedback unit converts the frequency division value p into the number n of simultaneously reproduced sounds. , The variable clock nf
And the operating frequencies of the sequencer 32 and the DSP 35 can be varied in accordance with the number n of simultaneously reproduced sounds.

The mode of use and operation of the portable telephone device and sound source processing circuit of the first embodiment will be described.
The operation method and device operation when making a call using the mobile phone 10 and setting a ringtone melody, etc. are general,
The detailed description will be omitted, and it is assumed that audio data has already been stored in the internal memory 23 by general key operation or download. An audio data stream A which is delivered to the sound source processing LSI 30 and further becomes an audio output signal B will be described in detail.

Before the audio data stream A is inputted to the sound source processing LSI 30, the number n of simultaneously reproduced sounds is "0".
However, since the value is inappropriate as the frequency dividing value, it is forcibly corrected to the minimum value "1", sent out from the sequencer 32 to the PLL circuit 40, and set in the counter 44.
The variable clock nf having the same frequency as the basic clock f is supplied to the sequencer 32 and the DSP 35, and those circuits operate at that frequency. Thus, the sound source processing LSI 3
0 indicates that the audio data stream A can be received at any time and the reproduction process can be started, while the operating frequency is minimized and the power consumption is minimized.

In this state, when the audio data stream A is sequentially sent to the FIFO 31, the audio data stream A is divided for each sound by the sequencer 32 and developed in the RAM 33 while maintaining the order. At this stage, the number n of simultaneously reproduced sounds becomes a value equal to or more than "1" and is set as a frequency dividing value in the counter 44, so that the frequency of the variable clock nf becomes n times corresponding to the value.
For example, when the note data included in the audio data stream A specifies a triad, the frequency of the variable clock nf is increased to three times the basic clock f, and the sound data is expanded to three channels of the RAM 33. Is done. When the 16 chord is designated, the frequency of the variable clock nf is increased to 16 times the basic clock f, and sound data of 16 channels is developed in the RAM 33. In each channel area, note data and the like are written by the sequencer 32 and the DSP 35
The data and the like of the elapsed time updated by, and the flags and the like set and reset by the two are also developed.

Further, based on this, the DSP 35
For each sound data of each channel, appropriate sound source data is read from the sound source ROM 34, and the sound of the timbre is reproduced at an appropriate intensity according to the tempo, elapsed time, and the like. Then, when the reproduction process is completed for one of the valid channels, the calculated values are added to each other and sent to the D / A conversion circuit 36. Thus, an acoustic output signal B in which a plurality of sounds are reproduced at the same time is generated.

Further, at this time, as described above, the frequency of the variable clock nf and the operating frequencies of the sequencer 32 and the DSP 35 change in accordance with the number n of simultaneously reproduced sounds. Since the processing capacity / calculation capacity also increases / decreases in accordance with the quantity / calculation quantity, the reproduction processing is performed at every predetermined cycle time without spoiling the uselessly and without waste. In a control circuit or an arithmetic circuit, the power consumption is generally determined in proportion to the clock frequency in a general clock synchronous digital circuit.
The power consumption of 35 is increased only when necessary according to the simultaneous reproduction sound number n, and is decreased otherwise, so that it can be minimized.

[0032]

Second Embodiment A sound source processing circuit of the present invention whose block diagram is shown in FIG. 3 is different from that of the first embodiment described above.
The point is that the counter 45 is additionally introduced as a second frequency dividing circuit, and the counter 45 is inserted and connected where the line of the variable clock nf branches out of the loop. The sequencer 32 sends a numerical value n to a counter 44 and sets it by sending a numerical value m to a counter 45 in addition to the setting.

The counter 45 is a m-ary counter that inputs and counts the variable clock nf and sends a carry as the variable clock nmf to the sequencer 32 and the DSP 35. When a numerical value m is sent from the sequencer 32, the counter 45 counts up. The base m is modified by the value m. Thus, the PLL circuit 40 outputs the basic clock f
Generates a variable clock nmf whose frequency is (n / m) times, thereby varying the operating frequencies of the sequencer 32 and the DSP 35.

In this case, the operating frequency of the sound source processing LSI 30 can be easily and finely varied by appropriately setting the numerical values n and m according to the number of sounds being reproduced at the same time. Specifically, the ratio can be increased not only to an integer multiple of the basic clock f but also to a large number of rational numbers based on various combinations of the numerical values n and m. Further, by selecting appropriate ones from a large number of combinations of the numerical values n and m to limit the use range, the controllable range of the frequency required for the VCO 43 can be narrowed. Thus, the PLL circuit 40 can be easily operated stably. In this example and in the first embodiment, the basic clock f supplied to the tone generator LSI 30 may be the same, and the basic clock f may be the same even if the range in which the values n and m can be taken is changed.

[0035]

Third Embodiment The sound source processing circuit of the present invention whose data structure is schematically shown in FIG. 4 is different from that of the first and second embodiments in that the audio data stream A includes a title and a maker. One or more sets of numerical values n and m calculated and detected in advance are stored in the empty area A3 of the header part A1 for storing names and the like at the start of the reproduction process or during reproduction. The values n and m are stored in the counter 4 shortly before the number of sounds suddenly changes.
Sequencer 3 to be used for updating the division value of 4, 45
2 is modified.

In this case, it is possible to obtain the number of sounds being reproduced before performing the reproduction processing.
By controlling the oscillation state of the LL circuit 40 a little earlier at the time of a sudden change, the start of the change of the frequency of the variable clocks nf and nmf can be preceded, and the end of the change can be made in time with the change of the processing amount / calculation amount. Therefore, the cutoff frequency of the loop filter 42 is
Operation can be further stabilized. Note that the numerical values n,
m may be scattered and stored in an area A2 in which tempo data and note data are continuous, not limited to the header part A1.

[0037]

4. Fourth Embodiment FIG. 5 shows an external view and a circuit block diagram of a device which is a handy electric tone incorporating a sound source processing circuit of the present invention. The electronic musical instrument is supplied with operating power of an electronic circuit from a disposable battery 51, and is provided with a playing key 52 and a tone color selecting switch 53 partially exposed. . The speaker 55 is also incorporated so as to emit sound. The input circuit 54 for inputting the operation state of the key 52 and the switch 53 to generate an audio data stream A of one line or a plurality of lines, and the audio data stream A and the basic clock f are input to the built-in electronic circuit. Sound source processing L for generating a sound output signal B and outputting it to the speaker 55
SI30. Note that this sound source processing LSI
Although the FIFO 31 is omitted from 30, it is omitted in consideration of the operation speed of the key 52 and the buffering function of the input circuit 54, and there is no inconvenience even if the FIFO 31 is provided.

Also in this case, as described in the first to third embodiments, the operating frequency of the sound source processing LSI 30 and the power consumption thereof are determined by the number of simultaneous presses of the key 52, that is, the sound source RO.
Since the variable is adjusted according to the number of sounds being reproduced based on the sound source data of M34, the continuous use time of the dry battery 51 is extended similarly to the battery pack 17.

[0039]

[Others] In each of the above embodiments, a chord is taken as an example of a plurality of sounds reproduced at the same time. However, the plurality of sounds may be not only chords but also a plurality or a large number of sound sources. That is, a plurality of sounds differing only in scale from the same sound source data may be reproduced simultaneously, a plurality of sounds may be reproduced simultaneously by selecting different sound source data, or a combination thereof. It is sufficient that a plurality of sounds can be reproduced, and it is not necessary to always reproduce a plurality of sounds. Therefore, a single sound may be reproduced depending on designation or operation.

[0040]

As is apparent from the above description, the portable telephone device and the sound source processing circuit according to the first solution of the present invention have low power consumption by appropriately changing the operating frequency. There is an advantageous effect that the portable telephone device and the sound source processing circuit of the present invention can be realized.

Further, in the sound source processing circuit according to the second solving means of the present invention, the frequency of the base clock or the like, which is the base of the variable clock, may be low, so that the power consumption is further reduced. There is an advantageous effect that the sound source processing circuit can be realized.

Further, in the sound source processing circuit according to the third solution of the present invention, the maximum number of sounds that can be simultaneously reproduced can be increased by independent improvement, so that power consumption is reduced and expansion is possible. This has an advantageous effect that an easy sound source processing circuit can be realized.

Further, in the sound source processing circuit according to the fourth solution of the present invention, since the frequency can be finely changed, a sound source processing circuit with even lower power consumption can be realized. This has the advantageous effect of:

[Brief description of the drawings]

FIG. 1A is a right side view of a mobile phone device, FIG. 1B is a front view of the mobile phone device, and FIG. 1C is an electronic circuit of a mobile phone device and a sound source processing circuit according to a first embodiment of the present invention. 3 is an overall block diagram of FIG.

FIG. 2 is a detailed block diagram of a part of the electronic circuit, in which (a) relates to a sound source processing circuit and (b) relates to a PLL circuit.

FIG. 3 is a block diagram of a sound source processing circuit according to a second embodiment of the sound source processing circuit of the present invention.

FIG. 4 is a schematic configuration diagram of an audio data stream in a third embodiment of the sound source processing circuit of the present invention.

5A and 5B show an application example of a fourth embodiment of the sound source processing circuit of the present invention to an electronic musical instrument, and FIG.
(B) is a block diagram of an electronic circuit.

[Explanation of symbols]

Reference Signs List 10 mobile phone (mobile phone device capable of sound source processing / electronic sound reproduction / electronic sound synthesis) 11 antenna (wireless communication means) 12 speaker (communication means, reproduced sound / synthesized sound output means, sound output means) 13 display (display means) 14 Telephone body 15 Keyboard (operation member, operation means) 16 Microphone (communication means) 17 Battery pack (rechargeable battery, detachable battery) 20 Electronic circuit 21 Wireless communication circuit (communication means) 22 Oscillator circuit (basic) Clock generation unit) 23 Internal memory (audio data stream storage and holding unit) 24 CPU (main processor, stream transfer unit, control unit) 25 KBD-I / F (keyboard interface, operation unit) 26 Voice input circuit (communication unit) 30 Sound source processing LSI (sound source processing circuit) 31 FIFO (first in first out) Memory, buffer memory) 32 Sequencer (microprocessor, control means, dividing means) 33 RAM (for temporary storage of audio data divided into each channel) 34 Sound source ROM (storage holding means for plural sound sources) 35 DSP (digital signal processor) , Calculation means) 36 D / A conversion circuit 40 PLL circuit (phase lock loop, clock frequency variable means) 41 phase comparison circuit 42 loop filter (low-pass filter) 43 VCO (voltage controlled oscillation circuit) 44 counter (first frequency dividing circuit) 45) Counter (second frequency divider) 50 Handy electric tone (electronic musical instrument, acoustic synthesizer) 51 Dry battery (disposable battery) 52 Key (key of keyboard, note information input means) 53 Switch (tone selection button, sound source information input means) ) 54 input circuit (audio Data stream input means) 55 speakers (playback sound / synthesis sound output means, sound output means)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04M 1/73 H04B 7/26 X H04Q 7/38 G10H 7/00 521Z

Claims (6)

[Claims] 1. A portable telephone device having a sound source processing circuit capable of simultaneously reproducing a plurality of sounds, wherein a means for varying an operating frequency of the sound source processing circuit according to the number of sounds being reproduced is provided. Mobile phone device. 2. A storage means for holding one or a plurality of sound source data, and an arithmetic means for selecting the same or different one from the sound source data based on input audio data and reproducing a plurality of sounds simultaneously. A sound source processing circuit comprising: a sound source processing circuit comprising: a frequency varying means for varying an operating frequency of the arithmetic means in accordance with the number of sounds being reproduced. 3. A dividing means for inputting the audio data and dividing the sound for each sound is provided upstream of the calculating means, and its operating frequency is also variable by the frequency varying means. 2. The sound source processing circuit according to item 2. 4. The frequency varying means includes a phase locked loop in which a frequency dividing circuit is incorporated in a feedback section, and the frequency is varied by updating the frequency dividing value. A sound source processing circuit according to claim 2. 5. The method according to claim 5, wherein said frequency varying means further comprises another frequency dividing circuit at a position out of said phase locked loop, and varies the frequency by updating the frequency dividing value. 5. The sound source processing circuit according to claim 4, wherein: 6. A semiconductor integrated circuit device according to claim 2, wherein said memory holding means, said calculating means or said dividing means, and said frequency varying means are mounted on one semiconductor integrated circuit device. Item 6. A sound source processing circuit according to any one of Items 5.