JP2002353741A - Mixer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mixer circuit that can maintain an excellent image rejection characteristic against dispersion of the constants of circuit elements and maintain performance for other signal characteristics equal to or better than that of a conventional mixer circuit. SOLUTION: To the input side of a local signal Slo and the output side of an IF signal Sif , 90-degree phase shifters 10, 50 consisting of 2-stage configuration polyphase filters are provided. A signal final output stage is provided with an emitter follower type output circuit 51 to compensate a signal power loss by the high impedance of the 90-degree phase shifter. A frequency conversion section has a configuration of a Gilbert mixer where an amplifier section 40 is used in common. Signal distribution resistors R1-R4 are provided into the transmission line of reception signals Srf 1, Srf 2 between the amplifier section 40 and mixer sections 20, 30, and the degradation in the image rejection characteristic due to the common use of the amplifier section 40 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an RF (Radio Freq)
uency: radio frequency) radio communication system,
For example, the present invention relates to a mixer circuit that can be suitably used for a reception circuit in a wireless communication system conforming to the Bluetooth standard.

[0002]

2. Description of the Related Art In a receiver in a radio communication system, in particular, a so-called superheterodyne receiver, a reception signal (desired reception signal) _{SD of a} desired frequency band is converted to a local oscillation signal (local (LO) signal) S _LO. Mixed with IF
(Intermediate Frequency) Processing for frequency conversion into a signal _SIF is performed. A circuit that obtains a frequency-converted output signal by mixing two or more input signals in this manner is called a mixer circuit. In recent years, with the development of IC (integrated circuit) technology, the overall configuration of a receiving circuit including a mixer circuit has been developed in the direction of higher integration and integration into one chip.

[0003] In the mixer circuit, when the frequency of the local signal S _LO is f _LO, an intermediate frequency f _IF by high frequency (f _LO
Regardless of whether a signal of either + f _IF ) or a low frequency (f _LO -f _IF ) is input, the signal is converted to an intermediate frequency f _IF in response to the input signal. Therefore, as shown in FIG. 14, for example, when the signal of the upper frequency f _D (= f _LO + f _IF ) with respect to the local oscillation frequency f _LO is received as the desired reception signal S _D , Frequency f _IM (= f _LO −f _IF )
When the other signal _SIM is input, the mixer circuit responds not only to the desired reception signal S _D but also to the other signal S _IM and outputs the IF signal.
Conversion to signal _SIF . That is, the signal component to be converted into an IF signal S _IF is to only desired reception signal S _D of the frequency f _D, other signals S _IM frequency f _IM is, acts as an interference wave, causing reception failure . Since the frequency f _{IM of} this interfering wave is exactly a mirror image of the desired reception frequency f _D centered on the local oscillation frequency f _LO ,
This is called an “image signal”. The frequency f _IM image signal S _IM is referred to as "image frequency", received by the image signal S _IM disorder called "image interference".

Therefore, in order to reduce image disturbance,
Contrivance for removing an image signal S _IM conventionally have been made. In the conventional receiver, as shown in FIG.
A method of externally attaching a PF (bandpass filter) circuit 110 and removing the image signal _SIM before input to the mixer circuit 103 is generally adopted. BPF circuit 11
Generally, SAW (Surface Acoustic Waves:
Surface acoustic wave) filters are often used.

[0005] In the circuit of FIG.
Circuit elements other than 10 are provided in one IC chip 100. That is, the low noise amplifier (LNA: low noise high frequency amplifier) circuit 1 is provided in the IC chip 100.
01, a local oscillator 102, a mixer circuit 103, an intermediate frequency amplifier (IF-AMP) 104, and a demodulator 105.

[0006] In this circuit, the balanced input RF band of the input signal (RF signal) S _RF is then amplified by the LNA circuit 101 is output to the outside BPF circuit 110. External BPF circuit 110 removes an image signal S _IM included in the RF signal S _RF, and outputs a signal including frequency f _D to desired to the mixer 103. Mixer circuit 103
Mixes the desired reception signal S _D output from the external BPF circuit 110 with the local signal S _{LO of} the local oscillation frequency f _LO output from the local oscillator 102 and outputs the intermediate frequency f _IF
And outputs the IF signal _SIF whose frequency has been converted. In this circuit, before the input to the mixer circuit 103, the external BPF circuit 1
Since pre-image signal S _IM are removed by 10, good IF signal S _IF only desired reception signal S _D
Can be converted to After that, the IF signal _SIF is amplified by the intermediate frequency amplifier 104 and input to the demodulator 105. Demodulator 105, balanced output signal S _OUT obtained by demodulating the IF signal S _IF.

However, the circuit configuration shown in FIG. 15 requires an external filter (external BPF circuit 110) to remove the image signal _SIM, which hinders miniaturization of the entire receiver. There is. In addition, since the external filter consumes a large amount of current as compared with the circuit in the IC chip, there is also a problem that energy saving is hindered. Therefore, in recent years, a mixer circuit called an "image rejection mixer" which does not require an external filter has been developed. The image rejection mixer is configured to be able to remove an image signal by itself.

FIG. 16 shows an example of a conventional receiving circuit using an image rejection mixer. In FIG. 16, components having the same functions as the circuit elements in FIG. 15 are denoted by the same reference numerals. The circuit shown in this figure includes an LNA circuit 101, a local oscillator 102, an image rejection mixer 201, a built-in active BPF
202 and demodulator 105 are integrated into one IC chip 200
It is provided inside. The image rejection mixer 201 includes a 90 ° phase shifter 211, mixer circuits 212 and 213, and a combiner 214.

In this circuit, a balanced input RF signal S
_{After the RF} is amplified in the LNA circuit 101, it is output to the image rejection mixer 201. The image rejection mixer 201 mixes the desired reception signal S _D included in the RF signal S _RF with the local signal S _{LO of} the local oscillation frequency f _LO output from the local oscillator 102, and performs frequency conversion to the intermediate frequency f _IF. And outputs the IF signal _SIF . At this time, if the image rejection mixer 201 is properly configured, the image signal S _IM included in the RF signal S _RF is removed, to convert only the desired received signal S _D to the IF signal S _IF it can. Thereafter, IF signal S _IF, after being input frequency selection in the internal active BPF202 is performed, are input to the demodulator 105. Demodulator 105, balanced output signal S _OUT obtained by demodulating the IF signal S _IF.

Next, the function of the image rejection mixer 201 will be described in more detail with reference to FIG. In the circuit of FIG. 17, it is optional whether the desired wave (desired received signal S _D ) is _placed in the upper sideband or the lower sideband with respect to the local signal _SLO .

This image rejection mixer 201
, The 90 ° phase shifter 211 has a local signal S _LO
Is entered. The signal input to the 90 ° phase shifter 211 is performed in a balanced manner. That is, a pair of balance signals having a phase difference of 180 ° is input as the local signal _SLO . 9
The 0 ° phase shifter 211 converts the input local signal S _LO to 9
The signal is divided into two and output to two types of balance signals that are shifted by 0 °. In the figure, two types of balance signals for these local signals S _LO are respectively referred to as “Lo-0 °, Lo-180”.
° "," Lo-90 ° , Lo-270 ° " and referred. Distributed one S _LO 1 (balanced signal Lo-0 ° of the local signal S _LO, L
o-180 °) is input to the mixer circuit 213. On the other hand, S
_LO 2 (balance signals Lo-90 ° and Lo-270 °) is input to the mixer circuit 212. The mixer circuits 212 and 213 include:
The RF signal S including the upper and lower sidebands of the local signal S _LO
RF is distributed and input in phase. At this time, the input of the RF signal S _RF 1 to the mixer circuit 213 is carried out equilibrium. That is, a pair of balance signals having a phase difference of 180 ° is input to mixer circuit 213 as RF signal S _RF1 . The other mixer circuit 212 also has the mixer circuit 21
The RF signal S _RF2 having the same phase as that of the RF signal 3 is input in a balanced manner.

The mixer circuit 213 mixes the input local signal S _LO1 (balanced signals Lo-0 °, Lo-180 °) and the RF signal S _RF1, and converts a pair of frequency-converted balance signals IF- 1. 0 ° and IF-180 ° are output as the first IF signal S _IF1 . On the other hand, the mixer circuit 212 similarly mixes the local signal S _LO 2 (balanced signals Lo-90 ° and Lo-270 °) and the RF signal S _RF2, and performs a frequency-converted pair of balance signals IF-90 °. , IF-270 ° as the second IF signal S _IF2 . The second IF signal S _IF2 is _{equal to} the first IF signal S
Is output in a state of being 90 ° phase shift on _IF 1. At this time, the phase relationship between the desired wave and the image wave in each of the IF signals S _IF1 and S _IF2 is output in a reversed state. When the first IF signal S _IF1 and the second IF signal S _{IF2 having} such a phase relationship are input to the 90 ° phase shifter 214A of the synthesizer 214 and synthesized, a desired wave (for example, an upper waveband) is obtained. ) Passes with phase coincidence, but the image signal (for example, lower sideband) cancels out because the phase relationship is reversed, and is removed.

[0013]

However, FIG.
When the function of the image rejection mixer 201 shown in (1) is configured by the conventional circuit technology, the image signal rejection characteristic called image rejection characteristic is deteriorated due to the variation of the circuit element constant occurring in the IC manufacturing process. There is a problem of doing it. As an example, the image rejection mixer 201 is generally used for R
In the case of a circuit called a C-RC configuration (FIG. 18), when the resistance value of the resistance element R and the capacitance value of the capacitor C fluctuate by 20% in the same direction with respect to the design value, Typ .> 40dB image rejection is 20d
It drops to around B.

Here, the circuit of FIG. 18 will be briefly described. In FIG. 18, the same reference numerals are given to portions corresponding to the respective circuit elements shown in FIG. This circuit has 9
Portions corresponding to the 0 ° phase shifters 211 and 214A are each formed of an RC filter using a resistor R and a capacitor C. That is, as shown in FIG.
4, R115, R116 and capacitors C110, C11
A 90 ° phase shifter 211 is composed of the first and C112. The resistors R100, R104, R107 and the capacitors C103, C104, C105 form a 90 ° phase shifter 214A.

The circuit shown in FIG.
2 and 213 are each constituted by a so-called Gilbert mixer. That is, as shown in the figure, the resistors R99, R123, R124 and the transistors Q105, Q106, Q107, Q108, Q10
9, Q110 form a mixer circuit 212. In the mixer circuit 212, an amplifier section is configured by a resistor R99 and transistors Q109 and Q110, and a resistor R1
23, R124 and transistors Q105, Q106, Q
A mixer section is constituted by 107 and Q108. The amplifier section of the mixer circuit 212 includes a constant current source I101,
I102 is connected. Further, the resistors R102 and R1
21, R122 and transistors Q99, Q100, Q1
The mixer circuit 213 is composed of 01, Q102, Q103, and Q104. In the mixer circuit 213, an amplifier is configured by the resistor R102 and the transistors Q103 and Q104, and a mixer is configured by the resistors R121 and R122 and the transistors Q99, Q100, Q101, and Q102. The constant current sources I99 and I100 are connected to the amplifier section in the mixer circuit 213.

In the circuit shown in FIG.
By the function of the 0 ° phase shifter 211, the local signal S _LO is divided into two, and two local signals S _LO 1 and S _LO 2 shifted by 90 ° are output. Further, the local signal S _LO1 and the RF signal S _RF1 are mixed by the function of the mixer circuit 213 composed of a Gilbert mixer, and the first IF signal S _IF1 is output. Similarly, the local signal S _LO2 and the RF signal S _RF2 are mixed by the mixer circuit 212 including a Gilbert mixer, and the second IF
The signal _SIF2 is output. Then, the first IF signal S _IF1 and the second IF signal S _IF2 are combined by the function of the 90 ° phase shifter 214A having the RC filter configuration while the image signal is removed, and the desired IF signal S _IF Is output.

Incidentally, in order to remove an image signal favorably by the image rejection mixer 201 shown in FIG. 17, the I.P.
For each of the image signals included in the F signals S _IF1 and S _IF2 , the amplitude and phase must satisfy predetermined conditions. That is, the image signal can be satisfactorily removed if the amplitudes are equal and the phases are reversed. However, in the circuit having the RC-RC configuration shown in FIG. 18, in particular, the amplitude relationship tends to collapse from an ideal state with respect to variations in circuit element constants, and image rejection characteristics deteriorate. There's a problem.

The 90 ° phase shifters 211 and 214A are
A method using an RC filter and a poly-phase (Poly-Phase) filter is also conceivable. In other words, a method in which one of the 90 ° phase shifters 211 and 214A is constituted by a polyphase filter is also conceivable, but also in this case, the image rejection characteristic is deteriorated due to the variation in the constant of the circuit element. Problems arise.

The present invention has been made in view of such a problem, and an object of the present invention is to reduce variation in constants of circuit elements.
It is an object of the present invention to provide a mixer circuit that can maintain good image rejection characteristics and maintain the same or higher performance as the other signal characteristics.

[0020]

A mixer circuit according to the present invention has a two-stage polyphase filter and converts input local oscillation signals into first and second signals having different phases from each other.
And a first phase shifter for distributing and outputting the received signals to two local transmission signals, and distributing the input received signals into two, and mixing the distributed received signals with the first and second local transmitted signals. A frequency converter for generating and outputting first and second intermediate frequency signals having different phases from each other, and a polyphase filter having a two-stage configuration, and combining the first and second intermediate frequency signals, A second phase shifter for removing unnecessary signal components included in the first and second intermediate frequency signals, and an emitter follower type output circuit for amplifying and outputting the intermediate frequency signal synthesized by the second phase shifter It is provided with.

In the mixer circuit according to the present invention, the function of the first phase shifter distributes the local oscillation signal to the first and second local oscillation signals having different phases from each other and outputs the divided signals. In addition, the function of the frequency conversion unit divides the input reception signal into two, and mixes each of the divided reception signals with the first and second local transmission signals, and outputs the second reception signal having different phases from each other. It is output as the first and second intermediate frequency signals. Then, the function of the second phase shifter combines the first and second intermediate frequency signals and removes unnecessary signal components included in the first and second intermediate frequency signals. The synthesized intermediate frequency signal is amplified and output by the function of the emitter follower type output circuit. In the mixer circuit according to the present invention, the first
The phase shifter and the second phase shifter are constituted by a two-stage polyphase filter, so that even if the constants of the circuit elements vary in the IC manufacturing process, for example, the image rejection characteristics can be improved. Reduction is prevented.
Further, since the emitter follower type output circuit is provided in the final output stage of the signal, the signal power loss due to the high impedance of the second phase shifter is compensated.

In the mixer circuit according to the present invention, for example, the frequency conversion section mixes one of the distributed reception signals with the first local oscillation signal to generate a first intermediate frequency signal. A second mixer unit for mixing the other of the received signals and the second local oscillation signal to generate a second intermediate frequency signal; and a first mixer unit and a second mixer unit.
Are shared by the first mixer unit and the second mixer unit.
And a common amplifier unit forming a Gilbert mixer.

As described above, by constituting the frequency conversion unit with a Gilbert mixer having a common amplifier unit, it is possible to mainly improve distortion characteristics.

When the frequency converter is constituted by the above-mentioned Gilbert mixer, the transmission line of the received signal between the common amplifier and the first mixer, and between the common amplifier and the second mixer is used. It is preferable to provide a resistance element for signal distribution.

By providing the resistive element for distributing the signal in this manner, a reduction in image rejection characteristics is prevented.

Further, it is preferable that a plurality of coils connected in series to each of the plurality of resistance elements are provided on the transmission line of the received signal.

By providing the coil in this manner, a decrease in gain due to the provision of the resistive element for signal distribution is prevented.

Further, in the mixer circuit according to the present invention,
It is preferable that the constants of the circuit elements of the respective polyphase filters in the first phase shifter and the second phase shifter are appropriately optimized in order to obtain desired signal characteristics.
Specifically, it is preferable that the constants of the circuit elements of the polyphase filter in the first phase shifter have the same value in both the first and second stages. Further, it is preferable that the constants of the circuit elements of the polyphase filter in the second phase shifter have different values in the first and second stages.

Since the constants of the circuit elements of each polyphase filter of each phase shifter are optimized as described above, loss of signal power is mainly prevented.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, an example of a receiving circuit to which a mixer circuit according to an embodiment of the present invention is applied will be described with reference to FIG. The receiving circuit shown in FIG. 1 is applied to, for example, a wireless communication system based on the Bluetooth standard. This receiving circuit, in order from the input side of the RF signal _SRF ,
An LNA circuit 2, a mixer circuit (image rejection mixer) 1, a built-in active BPF 4, and a demodulator 5 are provided. This receiving circuit also has a local oscillator 3. Each of these circuit elements is provided in one IC chip 6. Image rejection mixer 1
Is a 90 ° phase shifter 10 and mixer circuits 21A and 21B.
And a synthesizer 60. The combiner 60 includes a 90 ° phase shifter 50 and an output circuit 51 as shown in FIG. The mixer circuits 21A and 21B include an amplifier (A
MP) 40 are shared. Mixer circuits 21A and 21B
Have mixer sections 20 and 30, respectively.
The mixer circuits 21A and 21B constitute the frequency conversion unit 21 (FIG. 2).

In this embodiment, the 90 ° phase shifter 10
Corresponds to a specific example of the “first phase shifter” in the present invention, and the 90 ° phase shifter 50 corresponds to a specific example of the “second phase shifter” in the present invention.

The LNA circuit 2 has a function for amplifying and outputting the RF signal S _RF. The image rejection mixer 1 receives the desired reception signal S included in the RF signal S _RF
D and the local oscillation frequency f _LO output from the local oscillator 3
(LO) signal S _LO of the intermediate frequency f
_It has a function of outputting an IF signal _SIF whose frequency has been converted to IF. Image rejection mixer 1 also
It has a function of removing the image signal _SIM .

Next, the function of each part of the image rejection mixer 1 will be described with reference to FIG. In addition,
In the circuit of FIG. 2, it is optional whether the desired wave (desired received signal S _D ) is _placed in the upper sideband or the lower sideband with respect to the local signal _SLO .

The 90 ° phase shifter 10 has a function of splitting the balanced input local signal S _LO into two types of balanced signals shifted by 90 ° into two types and outputting the same. In FIG. 2, the two types of balance signals for the local signal S _LO are referred to as “Lo-0 °, Lo-180 °” and “Lo-90,” respectively.
°, Lo-270 ° ”.

The frequency conversion unit 21 distributes the received signal (RF signal S _RF ) into two, and separates the divided RF signals S _RF 1 and S _RF 2 into first and second local signals. It has a function of mixing with the signals S _LO 1 and S _LO 2 to generate and output first and second IF signals S _IF 1 and S _IF 2 having different phases.

The configuration of each part of the frequency conversion unit 21 will be described.
Specifically, the amplifier section 40 receives the input RF signal S_RFTo
Amplified and amplified RF signal S_RFIn-phase RF
Signal S_RF1, S_RFIt has a function of distributing to two. Miki
The sub-circuit 21 </ b> B (the mixer unit 30) includes the 90 ° phase shifter 10.
Local signal S distributed by_LO1 (balun
Signal (Lo-0 °, Lo-180 °) and input via the amplifier 40
RF signal S_RF1 and the frequency-converted one
The pair of balanced signals IF-0 ° and IF-180 ° are converted to the first IF signal.
S_IFIt has the function of outputting as 1. Meanwhile, the mixer
The circuit 21A (the mixer unit 20 thereof) is connected to the 90 ° phase shifter 10.
Therefore, the other local signal S distributed _LO2 (balance
Signals Lo-90 °, Lo-270 °) and input via the amplifier 40.
RF signal S_RF2 and a frequency-converted pair
The balance signals IF-90 ° and IF-270 ° of the second IF signal S
_IF2 is provided.

The 90 ° phase shifter 50 outputs the first IF signal S _IF
1 and with the second combines the IF signal S _IF 2, and has a function of outputting an IF signal S _IF frequency component desired.
The 90 ° phase shifter 50 also has a function of removing the image signal _SIM included in the first IF signal S _IF1 and the second IF signal S _IF2 . The output circuit 51 has a function for amplifying and outputting the IF signal S _IF output from the 90 ° phase shifter 50.

Next, a specific circuit configuration example of the image rejection mixer 1, which is a characteristic part of the present embodiment, will be described with reference to FIG. In FIG. 3, FIG.
Parts corresponding to the circuit elements shown in FIG. 2 are denoted by the same reference numerals. This circuit example is a signal of ISM (Industrial Scientific and Medical) band of 2.4 to 2.5 GHz, a circuit for downmixing a 3MHz intermediate frequency f _IF with image rejection. In this circuit example, the desired wave is in the upper sideband with respect to the local signal _SLO , and the image signal _SIM is in the lower sideband.

In this circuit example, the mixer circuits 21A and 21B
However, each has a configuration of a so-called Gilbert mixer. The Gilbert mixer is a mixer that is roughly divided into a mixer section and an amplifier section. In the conventional circuit shown in FIG. 18, two Gilbert mixers (mixer circuits 212 and 213) each having an independent amplifier section are cascaded, and two Gilbert mixers are respectively shifted by 90 °.
The two local signals S _LO1 and S _LO2 are input. On the other hand, in this circuit example, the mixer section and the amplifier section of the Gilbert mixer are considered separately, and the amplifier section is shared by the two mixer circuits 21A and 21B. That is, the mixer circuit 21A includes the amplifier 40 and the mixer 2
0 and a Gilbert mixer, and a mixer circuit 21B
Also, the amplifier 40 and the mixer 30 constitute a Gilbert mixer using the amplifier 40 as a common circuit element.

Incidentally, if the Gilbert mixer is configured by sharing the amplifier section 40, the image rejection characteristic may be deteriorated. Therefore, in this circuit example, in order to prevent a decrease in image rejection characteristic is provided a resistor for distributing the signal line after the distribution of the RF signal S _RF. That is, the amplifier 40 and the mixer 2
0 is connected via distribution resistors R1 and R2, and the amplifier unit 40 and the mixer unit 30 are connected via distribution resistors R3 and R4.

Now, the configuration of each section of the circuit example will be described. First, the amplifier section 40 includes transistors Q1 and Q
2 and a resistance Re. The RF signals _SRF are input to the base terminals of the transistors Q1 and Q2, respectively. The constant current sources I2 and I1 are connected to the emitter terminals of the transistors Q1 and Q2, respectively. The emitter terminals of the transistors Q1 and Q2 are connected via a resistor Re. The collector terminals of the transistors Q1 and Q2 are branched into two and connected to the mixer units 20 and 30.

The mixer section 20 includes transistors Q3, Q
4, Q5, Q6 and resistors R1, R2, R13, R14. The base terminals of the transistors Q3 and Q6 are
Connected to each other. The base terminals of the transistors Q4 and Q5 are also connected to each other. Transistors Q3, Q
6, one of the balanced signals (Lo-90 °) constituting the local signal S _LO 2 distributed by the 90 ° phase shifter 10 is commonly input to the base terminals of the transistors Q4 and Q5.
The other balanced signal (Lo-270 °) constituting the local signal S _LO2 is commonly input to the base terminal of. The emitter terminals of the transistors Q3 and Q4 are connected to each other. The emitter terminals of the transistors Q5 and Q6 are also connected to each other. Transistors Q3, Q4
, One of the balance signals constituting the RF signal S _RF2 distributed in the amplifier section 40 is commonly input via a distribution resistor R1 to the transistor Q5.
The Q6 emitter terminals of, one of the balanced signals constituting the RF signal S _RF 2 is adapted to be common input via a resistor R2 for distribution. The collector terminals of the transistors Q3 and Q6 are connected to the 90 ° phase shifter 50.

The mixer section 30 includes transistors Q7, Q
8, Q9, Q10 and resistors R3, R4, R15, R16. The base terminals of the transistors Q7 and Q10 are connected to each other. The base terminals of the transistors Q8 and Q9 are also connected to each other. Transistor Q
One of the balanced signals (Lo-180 °) constituting the local signal S _LO 1 distributed by the 90 ° phase shifter 10 is commonly input to the base terminals of the transistors Q and Q10.
Other balance signals (Lo-0 °) constituting the local signal S _LO 1 are commonly input to the base terminals of 8, Q9. The emitter terminals of the transistors Q7 and Q8 are connected to each other. The emitter terminals of the transistors Q9 and Q10 are also connected to each other. Transistor Q
One of the balance signals constituting the RF signal S _RF1 distributed in the amplifier section 40 is commonly input to the emitter terminals of the transistors Q9 and Q10 via the distribution resistor R3. , one of the balanced signals constituting the RF signal S _RF 1 is adapted to be common input via a resistor R4 for distribution. Transistor Q
The collector terminals of 7, Q8 are connected to a 90 ° phase shifter 50.

As shown in detail in FIG. 4, the 90 ° phase shifter 10 has two stages of polyphase filters 10A and 10A.
B. As shown in detail in FIG. 5, the 90 ° phase shifter 50 also includes two-stage polyphase filters 50A and 50B. 9
The reason why the 0 ° phase shifters 10 and 50 each have a two-stage configuration is as follows.
With a configuration with only one stage, sufficient image rejection characteristics cannot be obtained. With a configuration with three or more stages, signal loss increases excessively, and other characteristics other than the image rejection characteristics are reduced. This is because it is difficult to secure the same level.

Before describing the structure of each polyphase filter in the 90 ° phase shifters 10 and 50, first,
A configuration of a general one-stage polyphase filter will be described with reference to FIG. The polyphase filter is 4
Four input terminals 211-214 and four output terminals 215
218, four resistors Ra-Rd, and four capacitors Ca-Cd, one input terminal being cyclically coupled to two output terminals via one resistor and one capacitor. Configuration. That is, the first input terminal 211 is coupled to the first output terminal 215 via the first resistor Ra, and is coupled to the second output terminal 216 via the first capacitor Ca. Similarly, the second to fourth input terminals 212 to 14 are connected to the output terminals 215 to 218 via the second to fourth resistors Rb to Rd and the second to fourth capacitors Cb to Cd, respectively. It is cyclically connected to two of them.

As shown in FIG. 4, the first-stage polyphase filter 10A constituting the 90 ° phase shifter 10 has two input terminals 11 and 12, four output terminals, and four resistors R5 and R6. , R7, R8 and four capacitors C1, C
2, C3 and C4. In the figure, illustration of the four output terminals is omitted. This polyphase filter 10A has just the first and second input terminals 211 and 212 as compared with the polyphase filter of FIG.
The third and fourth input terminals 2
13, 214 are coupled to one input terminal 12. The rest is the same as the configuration of FIG.

On the other hand, the second-stage polyphase filter 10
B has four input terminals and four output terminals 13 to 1 as shown in FIG.
6, four resistors R9, R10, R11, R12 and four capacitors C5, C6, C7, C8.
In the figure, illustration of four input terminals is omitted.
Four output terminals of the first-stage polyphase filter 10A and four input terminals of the second-stage polyphase filter 10B are connected to each other. When signals having opposite phases (balance signals) are input to the two-stage polyphase filters 10A and 10B, the four output terminals 13 to 16 have the same amplitude and a phase shift of 90 °. Two signals are output.

As shown in FIG. 5, the first-stage polyphase filter 50A constituting the 90 ° phase shifter 50 has four input terminals 51 to 54, four output terminals, and four resistors R17 and R18. , R19, R20 and four capacitors C9, C10, C11, C12. In addition,
In the figure, illustration of four output terminals is omitted. This polyphase filter 50A has a shape in which the input side and the output side are just reversed as compared with the polyphase filter of FIG.

On the other hand, the second-stage polyphase filter 50
B has four input terminals, two output terminals 55 and 56, and four resistors R21, R22 and R as shown in FIG.
23, R24 and four capacitors C13, C14, C1
5, C16. In the figure, illustration of four input terminals is omitted. This polyphase filter 50B is different from the polyphase filter of FIG.
The input side and the output side are reversed, and the output terminals in the reversed state are combined into two. 1
Four output terminals of the second-stage polyphase filter 50A and four input terminals of the second-stage polyphase filter 50B are connected to each other. In such a two-stage polyphase filter 50A, 50B, 90 °
When four signals having different phases are input, they are combined into one balanced signal. That is, signals having the same amplitude and a phase shift of 180 ° are output from the two output terminals 55 and 56.

It is desirable that the constants of the polyphase filters constituting the 90 ° phase shifters 10 and 50 are optimized by a method described later so as to prevent loss of signal power.

The output circuit 51 includes transistors Q11 and Q11.
It is composed of an emitter-follower type amplifying circuit comprising 12 elements. The reason why the output circuit 51 is an emitter-follower type amplifier circuit is to compensate for signal power loss due to the high impedance of the 90 ° phase shifter 50. Output circuit 51
, The base terminals of the transistors Q11 and Q12 are connected to the output terminals 55 and 56 of the 90 ° phase shifter 50, respectively. The emitter terminals of the transistors Q11 and Q12 are connected to constant current sources I6 and I5, respectively. In the output circuit 51, the transistors Q11, Q
Twelve emitter terminals output the amplified IF signal _SIF .

(Modification of Circuit Configuration) Next, a modification (FIGS. 7 to 9) of the circuit configuration shown in FIG. 3 will be described.

The circuit of the first modified example shown in FIG.
Only the configuration of the amplifier section 40 is different from the circuit example shown in FIG. In the circuit example shown in FIG.
Has a configuration of a differential amplifier with a common emitter, but the amplifier section 40A in the circuit of FIG. 7 has a configuration of a differential amplifier with a common base. In the circuit of this modified example, the RF signal _SRF is input to each of the emitter terminals of the transistors Q1 and Q2 in the amplifier section 40A.

The circuit of the second modification shown in FIG.
In the circuit example shown in FIG. 5, gain compensation coils L1 and L are provided between the amplifier section 40 and the distribution resistors R1 to R4.
2, L3 and L4 are inserted in series. Other configurations are the same as those in FIG.

The circuit of the third modification shown in FIG.
In the circuit of the first modification shown in FIG. 8, the coils L1 and L for gain compensation are similar to those of the second modification shown in FIG.
2, L3 and L4 are connected to the amplifier 40A and the distribution resistor R1.
To R4. Other configurations are shown in FIG.
Is the same as

It should be noted that whether the configuration of the amplifier section 40 is a differential amplifier with a common emitter or a differential amplifier with a common base may be selected according to the difference in the target specification of the circuit.

Next, the operation and operation of the image rejection mixer 1 will be described.

First, the overall operation of the receiving circuit (FIG. 1) to which the image rejection mixer 1 is applied will be described. In the receiving circuit shown in FIG.
After F signal S _RF is amplified in LNA circuit 2 is output to the image rejection mixer 1. The image rejection mixer 1 mixes the desired reception signal S _D included in the RF signal S _RF with the local signal S _{LO of} the local oscillation frequency f _LO output from the local oscillator 3 and converts the frequency to an intermediate frequency f _IF. And outputs the IF signal _SIF . At this time, the image rejection mixer 1 outputs the RF signal S _RF
Is removed from the image signal _SIM included in. This allows
Only the desired reception signal _SD can be satisfactorily converted to the IF signal _SIF . Thereafter, IF signal S _IF, after being input frequency selection in the internal active BPF4 is performed, are input to the demodulator 5. Demodulator 5 balanced output signal S _OUT obtained by demodulating the IF signal S _IF.

Next, the operation and operation of the image rejection mixer 1 alone will be described with reference to FIG. 2 and mainly taking the circuit configuration of FIG. 3 as an example. The circuit example of Figure 7, as compared with the circuit example shown in FIG. 3, only the input of the RF signal S _RF (amplifier unit 40A) has a differential amplifier grounded base circuit The entire operation and operation are basically the same as those of the circuit example of FIG. 3 described below.

In the example of the circuit shown in FIG. 3, the amplifier section 40 includes an RF signal S _RF including upper and lower sidebands of the local signal S _LO.
Is entered. The signal input to the amplifier unit 40 is performed in a balanced manner. That is, a pair of balance signals having a phase difference of 180 ° is input as the RF signal _SRF . Amplifier section 40
The RF signal S _RF input to the transistors Q1 and Q2
And after being amplified by the function of the differential amplifier constituted by resistors Re, are 2 split into two balanced signals having the same phase (RF signal _{S RF 1, S RF 2)} .

One of the distributed RF signals S _RF1 is input to the mixer 30 in a balanced manner, and the other RF signal S _{RF2 is}
Are input to the mixer 20 in a balanced manner. At this time, in the mixer unit 20, the RF signal S _RF2 is supplied to the distribution resistors R1 and R1.
The signal is input to the emitter terminals of the transistors Q3 to Q6 via R2. In the mixer section 30, the RF signal S _RF 1
Are connected to transistors Q7 through Q3 through resistors R3 and R4 for distribution.
It is input to the emitter terminal of Q10. Resistor R1 for distribution
When ~ R4 does not exist, the phase operation of the circuit is not stable,
The desired image rejection characteristics cannot be obtained. This is because the mixer unit 20 and the mixer unit 30 share the amplifier unit 40. Specifically, in the case of using a normal Gilbert mixer, a circuit constant of 20%
Although the image rejection characteristic of 40 dB or more is ensured even if the variation occurs, when two Gilbert mixers are configured by sharing the amplifier unit 40, the image rejection is required unless the distribution resistors R1 to R4 are used. Rejection characteristics are reduced to around 30 dB. In the circuit example of FIG.
RF signals S _RF 1 and S _RF via distribution resistors R1 to R4.
By inputting _RF 2, the amplifier 40
Is prevented from lowering of the image rejection characteristic caused by the common use.

However, these distribution resistors R1 to R4
Is a factor that lowers the gain of the circuit. For this reason,
It is necessary to select appropriate values for these resistance values according to the characteristics of the entire circuit so as not to lower the gain.
As a means for coping with the phenomenon of the gain decrease, as shown in the circuit example of FIG.
0 (amplifier section 40A) and gain reduction compensation coils L1 to L4 may be inserted in series between distribution resistors R1 to R4. By these coils L1 to L4, the impedance of the circuit in the signal distribution portion increases, the resistance value for distribution can be reduced, and an increase in the gain of the amplifier section 40 can be expected. However, the coil L1
Since ~ L4 generally occupies a large area as a configuration in an IC, care must be taken in applying this point.

The local signal S _LO from the local oscillator 3 (FIG. 1) is input to the 90 ° phase shifter 10 in a balanced manner. 9
In 0 ° phase shifter 10, polyphase filter 10A of the two-stage configuration, 10B by the function of (4), two balanced signal Lo-0 ° where the local signal S _LO input is a 90 ° phase shift, Lo- The output is divided into 180 °, Lo-90 °, and Lo-270 °. One of the distributed local signal S _LO S _LO 1 (balanced signal Lo-0 °, Lo-180 °) is inputted to the base terminal of the transistor Q7~Q10 mixer unit 30. On the other hand, S _LO 2 (balance signal Lo-90 °, Lo-270
°) is input to the base terminals of the transistors Q3 to Q6 of the mixer section 20.

In the mixer section 30, transistors Q7 to Q7
Local signal S _LO 1 (balanced signal Lo)
-0 °, Lo-180 °) and the RF signal S _RF1, and outputs a pair of frequency-converted balance signals IF-0 °, IF-180 ° as the first IF signal S _IF1. . On the other hand, the mixer unit 2
0 Similarly, the local signal S _LO 2 which is input to the transistor Q3 to Q6 (balanced signal Lo-90 °, Lo-270 °) and R
The second IF signal S _IF2 is mixed with the F signal S _RF2 , and the frequency-converted pair of balanced signals IF-90 ° and IF-270 ° are output as the second IF signal S _IF2 .

The second IF signal S_IF2 is the first IF signal
S_IFAbout 90 ° with 90 ° phase shift from 1
Output to the phaser 50. At this time, each IF signal S_IF
1, S_IF2 、 hope wave IF_DAnd image wave IF_IMAnd rank
The phase relationship is output in a reversed state. That is, the desired wave
IF_DAbout the input terminals 51 to 90 of the 90 ° phase shifter 50
In FIG. 54, as shown in FIG.
A phase-related signal is input. On the other hand, image wave IF_IMTo
For the input terminals 51 to 54 of the 90 ° phase shifter 50,
As shown in FIG.
Number is entered. FIG. 5 shows the 90 ° phase shifter 50.
Desired wave IF at input stage and output stage_D, IF_D1 phase
And image wave IF_IM, IF_IMAn example of the relationship with phase 1 is shown.
You. The phase is basically determined by the desired wave IF_D,
IF_D1 and image wave IF_IM, IF_{I M}1 and each independently
The phase between each signal at the same time is not necessarily shown.
It is not always the case.

The first IF signal S _IF1 and the second IF signal S _{IF2 having} such a phase relationship are converted by the 90 ° phase shifter 50
, And a desired wave (upper waveband in the present circuit example) is passed in phase by the function of the two-stage polyphase filters 50A and 50B (FIG. 5). On the other hand, the image signal (lower sideband in the present circuit example) is canceled and canceled out because the phase relationship is reversed. Thereby, the desired IF signal S is output from the 90 ° phase shifter 50.
_IF is output. The IF signal _SIF is further amplified by the function of the transistors Q11 and Q12 of the output circuit 51 so as to be adapted to the load of the next-stage circuit, and output to the next-stage circuit. At this time, even if the image signal slightly remains at the stage of being input to the output circuit 51, the signal remains a signal sufficiently smaller than the signal in the desired waveband even after being amplified by the transistors Q11 and Q12. Is output.

Next, the difference between the performance of the image rejection mixer 1 of the present embodiment and the performance of the conventional image rejection mixer will be considered.

In the case where the constants of the circuit elements do not vary from the design values, the present embodiment using the conventional mixer using the RC filter in the 90 ° phase shifter (FIG. 17) and the two-stage polyphase filter There is no significant difference in the image rejection characteristics between the two mixers. On the other hand, when there is a variation in the manufacturing of the circuit element constants, the conventional mixer using the RC filter
Variations in the constants of the resistance and the capacitor cause a significant reduction in image rejection characteristics. On the other hand, like the mixer of the present embodiment, the local signal _SLO input side 9
When the 0-degree phase shifter 10 and the 90-degree phase shifter 50 on the output side of the IF signal S _IF are integrated with a two-stage polyphase filter, the image rejection characteristic is deteriorated due to a variation in the constant. Can be suppressed.

The following are the main reasons why the image rejection mixer 1 can suppress the deterioration of the image rejection characteristic with respect to the variation of the constant. First, the variation of constants inside the IC is not independent of individual elements, but exhibits the same direction of variation in all elements. Next, in a phase shifter using a polyphase filter, its output power (output amplitude)
Are the phase 0 ° and 180 ° balance signals and the phase 90
And 270 ° of the balance signal must match in all frequency bands (see FIG. 10). Further, when the polyphase filter is configured with two or more stages, 90 °
The phase characteristic changes in a form close to symmetry on the frequency dimension from the point where the phase shift frequency has a band and the phase difference is 90 ° (see FIG. 11). Since these are satisfied, in the image rejection mixer 1, even if there is a variation in the constant, the 90 ° output stage
In the phase shifter 50, for each of the image signals included in the IF signals S _IF1 and S _IF2 , the amplitude and the phase substantially satisfy a predetermined condition for removing the image signal,
The image signal can be removed well.

FIG. 10 shows two signals output from the 90 ° phase shifter 10 (polyphase filters 10A and 10B) on the input side.
The output amplitude characteristics of two balance signals (phase 0 °, 180 ° signals and phase 90 °, 270 ° signals) are shown. In FIG. 10, the horizontal axis represents the frequency (GH
z), and the vertical axis indicates power gain (dB). FIG.
As can be seen from FIG.
In B, the output amplitudes of the two balance signals are almost completely coincident in the entire frequency range.

FIG. 11 shows a polyphase filter 10A,
Two balanced signals (phase 0 °,
The output phase difference characteristics of the 180 ° signal and the 90 ° and 270 ° phase signals are shown. In FIG. 11, the horizontal axis represents frequency (GHz) and the vertical axis represents phase (deg).
Is shown. As can be seen from FIG. 11, the polyphase filters 10A and 10B have a phase characteristic of 90 °.
From the point P1 at which the phase difference becomes a shape close to symmetry in the frequency dimension.

The image rejection mixer 1
Then, the amplifier unit 40 is composed of two mixer circuits 21A and 21B.
Are combined to form a Gilbert mixer, thereby improving distortion characteristics.

Further, in the present image rejection mixer 1, the loss of signal power is prevented by optimizing the constants of the polyphase filters constituting the 90 ° phase shifters 10 and 50. Further, since the emitter follower type output circuit 51 is arranged at the final output stage of the signal, the signal power loss due to the high impedance of the 90 ° phase shifter 50 is compensated.

Here, a method of optimizing the constant of each polyphase filter will be described. 90 ° phase shifters 10, 5
It is preferable that the polyphase filter constituting 0 is optimized so as to show the optimum amount of energy transmission with respect to the output impedance of the preceding circuit and the input impedance of the next circuit. As a result, the 90 ° phase shifter 10, 50, in the first stage and second-stage polyphase filter, the cutoff frequency (fc = 1 / (2πRC) ) is fixed to an intermediate frequency S _IF, and the resistance R The combination of the constants of the capacitor C is optimized.

More specifically, the larger the impedance of the 90 ° phase shifter 50 on the output side, the better the gain of the entire circuit due to the characteristics of the next-stage emitter follower type output circuit 51. However, the NF (Noise Figure) Will worsen at the same time. For this reason, for the 90 ° phase shifter 50 on the output side, an upper limit is set for the value of the resistance, which is a component of the polyphase filter, and the upper limit of the capacitance value of the capacitor is set based on the limit of the capacitance value that can be manufactured inside the IC. decide. As a result, an upper limit and a lower limit are set for the possible values of the resistance value and the capacitance value. Within this setting range, the first-stage and second-stage polyphase filters are combined to form a 90 ° phase shifter 5.
Optimize input impedance and output impedance of 0. At this time, the resistance value and the capacitance value of the polyphase filter are optimized so that the output signal level in the next-stage emitter follower type output circuit 51 is maximized.

The above-described optimization methodology for the 90 ° phase shifter 50 on the output side is similarly applicable to the 90 ° phase shifter 10 on the input side. In the circuit example of FIG.
First-stage and second-stage polyphase filters 10A and 10B
In both cases, when the constants of the elements were configured to have the same value, the impedance could be increased as much as possible.

Considering the above optimization method, 90 °
Polyphase filter 10A, 1 constituting phase shifter 10
It is desirable that the circuit constant of each element of 0B is configured to have the same value in both the first and second stages. On the other hand, polyphase filters 50A and 50B constituting the 90 ° phase shifter 50
It is desirable that the circuit constant of each element is different between the first stage and the second stage. Specifically, as shown in an example of the values in FIG. 5, each resistance value in the second-stage polyphase filter 50B is set to be larger than each resistance value in the first stage. desirable. As a rule of thumb, each resistance value in the first stage is Ra, and each resistance value in the second stage is R
b, Ra ≦ Rb, Ra = kRb, 1 ≦ k
It is considered that the value falls within a range of about ≦ 2.5. Regarding the capacitance value, “fc = 1 /
(2πRC) ”, so if the resistance value is determined, the capacitance value is also determined.

The configuration in which the RC filter and the polyphase filter are combined, that is, the 90 ° phase shifter 10
Is composed of an RC filter (or a polyphase filter), and the 90 ° phase shifter 50 is composed of a polyphase filter (or an RC filter).
Such excellent image rejection characteristics cannot be obtained. Further, when the 90 ° phase shifters 10 and 50 are constituted by three or more stages of polyphases, the signal loss in the phase shifters is excessively increased, and various characteristics other than the image rejection characteristics are reduced to the same level as the conventional one. It is difficult to secure.

<Simulation Data> Next, specific performance data of the image rejection mixer 1 will be simulated and shown. The following data is simulation data when the image rejection mixer 1 has the circuit configuration of FIG. Note that the in-band characteristic at the time of the desired constant indicates a characteristic when the constant of each circuit element is a constant value as designed. CG represents a conversion gain, and NF represents a noise figure. IIP3 represents an input intercept point.
The image rejection when the constant fluctuates means that the resistance value and the capacitance value of each polyphase filter in the 90 ° phase filters 10 and 50 fluctuate 20% in the same direction (plus or minus) with respect to the design value. Represents the value of the image rejection characteristic at the time.

RF signal input: 2.4 G to 2.5 GHz LO signal input: 2.3997 G to 2.4997 GHz IF signal output: 3 MHz <In-band characteristic at desired constant> CG: 6.02 dB NF ... 18.13dB IIP3 ...- 2.03dBm Image rejection ... 51dB Image rejection at constant fluctuation ...> 40dB

FIG. 12 shows the result of simulating the image rejection characteristics. 12, the horizontal axis represents the frequency (GHz), and the vertical axis represents the value (dB) of the image rejection characteristic. In the figure,
Points indicated by "●", "black square", and "x" are sample points used to obtain these characteristics. In FIG. 12, the characteristic value when the constant fluctuates by + (plus) 20% is shown by a broken line (black square). In addition, the characteristic value when the constant fluctuates by − (minus) 20% is shown by a dashed line (x mark). The characteristic values at the time of the desired constant are indicated by solid lines (indicated by ●).

As can be seen from the results of the above simulation data, the present image rejection mixer 1 can obtain good image rejection characteristics with respect to variations in circuit element constants, and can obtain other signal characteristics (gains). , NF and IIP3) also obtained good values.

As described above, according to the present image rejection mixer 1, the 90 ° phase shifter 10 composed of a two-stage polyphase filter is provided on the input side of the local signal _{SLO and} the output side of the IF signal _SIF. , 50 are provided, it is possible to prevent the image rejection characteristics from being lowered even if, for example, variations in circuit element constants occur in the IC manufacturing process. At this time, in each phase shifter, the constants of the circuit elements of each polyphase filter are
Since optimization is appropriately performed to obtain desired signal characteristics, desired image rejection characteristics can be maintained while preventing loss of signal power and the like. Also,
An emitter follower type output circuit 51 is provided at the final output stage of the signal.
Is provided, it is possible to compensate for the signal power loss due to the high impedance of the 90 ° phase shifter 50.

The frequency converter 21 is connected to the amplifier 40
Is used as a Gilbert mixer, so that distortion characteristics can be mainly improved. Further, the reception signals S _RF1,1 between the amplifier unit 40 and the mixer units 20,30
On transmission line S _RF 2, resistors for signal distribution R1~R4
Is provided, it is possible to prevent a reduction in image rejection characteristics due to the common use of the amplifier unit 40. Furthermore, preferably, the received signals S _RF 1,
On transmission line S _RF 2, resistors for signal distribution R1~R4
Are connected in series with the coils L1 to L4 (FIGS. 8 and 9).
Are connected to provide a reduction in gain due to the resistors R1 to R4.

As described above, according to the present image rejection mixer 1, it is possible to maintain good image rejection characteristics with respect to variations in circuit element constants, and the other signal characteristics are equivalent to those of the prior art. Or better performance can be maintained. Specifically, even if the resistance value and the capacitance value of each polyphase filter fluctuate by 20% in the same direction with respect to the design value, the performance of the gain, NF, and IIP3 is maintained at the conventional level, and , An image rejection characteristic exceeding 40 dB can be maintained. Also, when a receiver integrated into an IC is configured by using the image rejection mixer 1, an external filter can be removed from the configuration of the receiver, and the circuit can be reduced in size and energy can be saved. Can be. In addition, since good image rejection characteristics can be maintained with respect to variations in circuit element constants, the yield of ICs can be improved.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the mixer circuit of the present invention is not limited to the receiving circuit having the configuration shown in FIG. 1, but can be widely applied to receiving circuit circuits in various wireless communication systems using the RF band.

[0088]

As described above, claims 1 to 6
According to the mixer circuit described in any one of the above, the mixer circuit has a two-stage polyphase filter, and distributes the input local oscillation signals to the first and second local oscillation signals having different phases from each other. A first phase shifter to be output, and an input received signal divided into two, and the divided received signals are mixed with first and second local oscillation signals, and the first and second local oscillation signals are different in phase from each other. A frequency conversion unit that generates and outputs a second intermediate frequency signal; and a polyphase filter having a two-stage configuration, synthesizes the first and second intermediate frequency signals, and combines the first and second intermediate frequency signals. A second phase shifter that removes unnecessary signal components included in the signal; and an emitter follower-type output circuit that amplifies and outputs an intermediate frequency signal synthesized by the second phase shifter. Circuit element The relative variation constant, it is possible to maintain good image rejection characteristics, and can also be maintained at a level equivalent to the conventional art or more performance for other signal characteristics.

In particular, according to the mixer circuit of the second aspect, in the mixer circuit of the first aspect, the frequency conversion section mixes one of the distributed reception signals and the first local oscillation signal, A first mixer unit that generates one intermediate frequency signal, a second mixer unit that mixes the other of the distributed received signals and a second local oscillation signal, and generates a second intermediate frequency signal; Since the first mixer unit and the second mixer unit are shared and shared by the first mixer unit and the second mixer unit, and a common amplifier unit forming a Gilbert mixer, the configuration is mainly performed. The distortion characteristics can be improved.

According to the mixer circuit of the third aspect, the mixer circuit of the second aspect further includes a portion between the common amplifier portion and the first mixer portion and a portion between the common amplifier portion and the second mixer portion.
Since a plurality of resistive elements are provided on the transmission line of the received signal between the mixer unit and the mixer unit, it is possible to prevent a reduction in image rejection characteristics due to the common use of the amplifier unit.

Further, according to the mixer circuit of the fourth aspect, in the mixer circuit of the third aspect, a plurality of coils connected in series to each of the plurality of resistance elements are provided on the transmission line of the received signal. Since this is provided, it is possible to prevent a decrease in gain due to providing a plurality of resistance elements on the transmission line of the received signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a receiving circuit to which an image rejection mixer according to an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram showing an outline of an image rejection mixer according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of an image rejection mixer according to one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a 90 ° phase shifter on the input side in the image rejection mixer shown in FIG. 3;

5 is a circuit diagram showing a configuration of a 90 ° phase shifter on the output side in the image rejection mixer shown in FIG. 3;

FIG. 6 is a circuit diagram showing a configuration of a general polyphase filter.

FIG. 7 is a circuit diagram showing a first modification of the circuit configuration shown in FIG. 3;

FIG. 8 is a circuit diagram showing a second modification of the circuit configuration shown in FIG. 3;

FIG. 9 is a circuit diagram showing a third modification of the circuit configuration shown in FIG. 3;

FIG. 10 is a characteristic diagram showing an output amplitude characteristic of a balanced signal output from a two-stage polyphase filter in the image rejection mixer according to one embodiment of the present invention.

FIG. 11 is a characteristic diagram showing an output phase difference characteristic of a balance signal output from a two-stage polyphase filter in the image rejection mixer according to one embodiment of the present invention.

FIG. 12 is a characteristic diagram showing a result of simulating image rejection characteristics in the image rejection mixer according to one embodiment of the present invention.

FIG. 13 is an explanatory diagram illustrating a phase relationship between a desired wave and an image wave input to a 90 ° phase shifter in an output stage.

FIG. 14 is an explanatory diagram illustrating image disturbance generated in the mixer circuit.

FIG. 15 is a block diagram illustrating a configuration example of a conventional receiving circuit.

FIG. 16 is a block diagram illustrating a configuration example of a conventional receiving circuit using an image rejection mixer.

FIG. 17 is a block diagram illustrating a configuration example of a conventional image rejection mixer.

FIG. 18 is a circuit diagram showing a configuration example of a conventional image rejection mixer using an RC phase shifter.

[Explanation of symbols]

S _D desired reception signal S _IF IF (intermediate frequency) signal S _IM image signal S _LO Local oscillation signal (local (LO) signal) S _RF RF signal 1 Image rejection mixer 3 Local oscillator 10, 50 90 ° phase shifter 10A, 10B, 50A, 50B Polyphase filter 20, 30 Mixer section 21 Frequency conversion section 40 Amplifier section 51 Output circuit 60 Synthesizer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hidetoshi Tsubota 3-2-1, Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa Inside RF Chips Technology Co., Ltd.

Claims (6)

[Claims] A first phase shifter having a two-stage polyphase filter for distributing an input local oscillation signal to first and second local oscillation signals having different phases from each other and outputting the same; The input received signal is divided into two, and each of the divided received signals is mixed with the first and second local oscillation signals to generate first and second intermediate frequency signals having different phases from each other. And a polyphase filter having a two-stage configuration for synthesizing the first and second intermediate frequency signals and unnecessary unnecessary signals included in the first and second intermediate frequency signals. A mixer circuit comprising: a second phase shifter for removing a signal component; and an emitter follower type output circuit for amplifying and outputting an intermediate frequency signal synthesized by the second phase shifter. 2. The frequency conversion section, wherein: a first mixer section that mixes one of the distributed reception signals and the first local oscillation signal to generate the first intermediate frequency signal; A second mixer unit that mixes the other of the divided received signals and the second local oscillation signal to generate the second intermediate frequency signal; a first mixer unit and a second mixer unit 2. The mixer circuit according to claim 1, further comprising: a common amplifier unit that constitutes a Gilbert mixer and each of the first mixer unit and the second mixer unit. 3. The image processing apparatus according to claim 1, wherein said common amplifier unit and said first mixer unit and said common amplifier unit and said second mixer unit are connected between said common amplifier unit and said second mixer unit so as to prevent deterioration of image rejection characteristics. 3. The mixer circuit according to claim 2, wherein a plurality of resistance elements are provided on a transmission line of the reception signal. 4. The mixer according to claim 3, further comprising a plurality of coils connected in series to each of the plurality of resistance elements, on the transmission line of the received signal. circuit. 5. The circuit according to claim 1, wherein constants of circuit elements of said polyphase filter in said first phase shifter are the same in both the first and second stages. The mixer circuit according to claim 1. 6. The method according to claim 1, wherein constants of circuit elements of the polyphase filter in the second phase shifter are different from each other in a first stage and a second stage. The mixer circuit according to claim 1.