JP2002353553A - Semiconductor light-emitting device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device, whose contact resistance is low, whose adhesion is superior and which can contribute toward reduction of the operating voltage, and to provide a method of manufacturing the semiconductor light-emitting device. SOLUTION: In the semiconductor light-emitting device, a p-type compound semiconductor layer 14 and an electrode 15 are provided on a substrate 1. The electrode 15 is provided with an Au layer 9, which is brought into contact with the layer 14, an impurity absorption layer 10, an impurity barrier layer 11 and a surface layer 12, in this order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having an electrode on a compound semiconductor layer and a method of manufacturing the same, and more particularly, to a semiconductor light emitting device having an electrode having an electrode structure excellent in low contact resistance and adhesion. The present invention relates to the manufacturing method.

[0002]

2. Description of the Related Art At present, semiconductor light emitting devices such as laser diodes and light emitting diodes which are widely used as light sources for information processing and communication are generally made of GaAs, GaP or the like.
After epitaxially growing a compound semiconductor layer on a substrate such as a II-VI compound semiconductor such as III-V or ZnSe, or sapphire, an electrode is formed on the compound semiconductor layer or, if necessary, on the substrate. Then, the substrate is cleaved into a bar shape in a chip forming process, coated on an end face, and further cut into element sizes, and then processed into a product through a bonding process and a packaging process.

The above-mentioned electrodes serve as an interface when a semiconductor light emitting device is incorporated in a carrier or wiring is performed on electrodes on the surface of the semiconductor light emitting device. It is important that the connection is ohmic. On the other hand, the electrode is also required to have good adhesion in bonding such as wiring on the surface, and for that purpose, it is important to suppress the diffusion of constituent elements of the compound semiconductor to the electrode surface as much as possible. For the purpose of satisfying such requirements, the electrode usually has a multilayer structure including an ohmic contact layer for making ohmic contact with the compound semiconductor layer and a surface layer. Then, in order to improve ohmic contact and adhesion between the multilayer and the compound semiconductor, it is common to form a multilayer on the compound semiconductor layer and then perform a heat treatment called an alloy.

As a material of a surface layer provided on the ohmic contact layer, Au having high conductivity and being hardly corroded is widely used. For example, p-type G
In an electrode formed on a compound semiconductor layer such as aAs or AlGaAs, Cr / Au, Cr / Pt / Au, Ti /
Pt / Au, AuZnNi or the like is used as an electrode material. On the other hand, the material of the ohmic contact layer is also empirically known, and AuG is used as an ohmic contact layer on a compound semiconductor such as n-type GaAs or GaInP.
An electrode structure such as eNi or AuGeNi / Au is used.

By the way, when an electrode containing Au is formed on a p-type compound semiconductor, if the content of Au increases,
It has been experimentally revealed that the electrode surface in contact with the semiconductor layer has a particularly large effect of sucking the group III element out of the p-type compound semiconductor layer. When the content of the group III element on the outermost surface of the electrode surface layer exceeds 5%, the formation of an alloy or an oxide of Au and the group III element becomes remarkable, and the bonding strength is remarkably reduced. (JP-A-11-274469).

In order to suppress the decrease in the bonding strength, for example, Japanese Unexamined Patent Application Publication No. 11-274469 discloses a method in which an impurity absorbing layer having a specific composition such as Ti is provided in an electrode layer. There is disclosed a method capable of maintaining the bonding strength by trapping the content at the outermost surface of the electrode surface layer to 5% or less.

On the other hand, attempts have been made to lower the contact resistance of the electrodes, and Ti has relatively good bonding properties.
As an electrode having an electrode structure of / Pt / Au, an electrode having a layer using a material (Pt) having a large work function has been developed. For example, Japanese Patent No. 3093774, Okada, e
t al; JJAP, Vol.30, No.4A, April, 1991, pp L558-56
FIG. 0 shows a technique in which Pt / Ti / Pt / Au is sequentially formed on a p-GaAs layer to obtain a low contact resistance. Sugiyama, et al; JJAP, Vol. 33, Janua
ry, 1994, pp. 786-789, p-AlGaAs / G
Pt / Ti / Pt / Au layers are sequentially formed on the aAs layer,
Techniques for realizing low contact resistance are disclosed.

[0008]

However, with the recent development of semiconductor lasers used for information processing, communication and the like and diversification of needs, the electrodes used for semiconductor lasers and the like are also adapted to the applications. And miniaturization is progressing more and more. Under these circumstances, the electrodes having the above-mentioned conventional electrode structure are not always sufficient to reduce the operating voltage. Therefore, there is an urgent need to develop an electrode capable of reducing the operating voltage as compared with the conventional electrodes. Thus, the present invention has been made to solve the above-described problems, and provides a semiconductor light emitting device having an electrode structure which has low contact resistance and excellent adhesion, and can contribute to reduction of operating voltage, and a method of manufacturing the same. The purpose is to:

[0009]

Means for Solving the Problems As a result of intensive studies to solve the above problems, the present inventors have made an electrode having an electrode structure using Au instead of Pt as the ohmic contact layer of the p-type compound semiconductor layer. As a result, the semiconductor light emitting device of the present invention having an electrode having lower contact resistance and better adhesion than conventional electrodes and a method of manufacturing the same have been completed. That is, the present inventors have formed an electrode having an electrode structure of Au / Ti / Pt / Au using Au having a large work function as a metal of an electrode in contact with a compound semiconductor, thereby achieving low contact resistance and low compound resistance. A semiconductor light emitting device capable of dramatically improving the adhesive strength to a semiconductor layer has been completed.

The present invention is a semiconductor light emitting device having a compound semiconductor layer and an electrode on a substrate, wherein the electrode comprises an Au layer, an impurity absorbing layer, an impurity barrier layer, and a surface in contact with the p-type compound semiconductor layer. A semiconductor light emitting device having layers in this order is provided.

As a preferred embodiment of the semiconductor light emitting device of the present invention, an embodiment in which the thickness of the Au layer is 1 μm or less; an embodiment in which the impurity absorption layer is a layer containing Ti; and an embodiment in which the impurity barrier layer contains Pt. A mode in which the surface layer is a layer containing Au; and a mode in which a plated conductive layer is further provided on the electrode.

According to the semiconductor light emitting device of the present invention, the p-type G
Since pure Au is used as a contact metal having a large work function on an aAs-based compound semiconductor, low ohmic contact resistance and adhesion at a semiconductor / electrode (metal) interface can be improved.

Further, the present invention provides a semiconductor light emitting device including a step of forming a substrate, a step of forming a compound semiconductor layer, and a step of forming an electrode having an Au layer, an impurity absorbing layer, an impurity barrier layer and a surface layer in this order. Wherein the electrode is formed by laminating an Au layer, an impurity absorbing layer, an impurity barrier layer, and a surface layer by a film forming method, and then performing alloying at 600 ° C. or less to form the electrode. A method for manufacturing a semiconductor light emitting device is provided.

As a preferred embodiment of the production method of the present invention,
An embodiment in which the film forming method is a physical film forming method; an embodiment in which the physical film forming method is electron beam evaporation, resistance heating evaporation or sputtering; and forming the surface layer in the step of forming the electrode. An embodiment including a step of forming a plating conductive layer on the surface layer after and before performing the alloying; an embodiment in which the surface layer of the electrode is formed by a chemical film forming method; the chemical film forming method However, there can be mentioned an embodiment in which an electrolytic plating method, an electroless plating method, or a metal spraying method is used.

According to the method of manufacturing a semiconductor light emitting device of the present invention, since alloying is performed within a predetermined temperature and time,
It is possible to provide a semiconductor light emitting device that has low contact resistance and excellent adhesion at the semiconductor / electrode interface.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor light emitting device according to the present invention and a method for manufacturing the same will be described in detail. In the semiconductor light emitting device of the present invention, a compound semiconductor layer is formed on a substrate, and an Au layer, an impurity absorption layer, an impurity barrier layer, and a surface layer that are in contact with a p-type compound semiconductor layer are further formed on the compound semiconductor layer in this order. It is characterized by having an electrode. The structure of the semiconductor light emitting device of the present invention having such features will be specifically described with reference to FIG. In addition, although the drawings attached to this specification include parts whose dimensions are intentionally changed in order to facilitate understanding of the structure, actual dimensions are as described in this specification. Also,
FIG. 1 shows a semiconductor light emitting device having a so-called self-aligned stripe structure, but the present invention is not limited to this structure, and may have a buried ridge stripe structure.

In FIG. 1, the structure of the semiconductor light-emitting device of the present invention is schematically shown in which an n-type cladding layer 2, an active layer 3, and a p-type first cladding layer 4 are laminated on a substrate 1, and on top of that. A surface protection film 5, a current blocking layer 6 opened in a stripe shape through the surface protection film 5, and a p-type second cladding layer 7, which is laminated on the opening of the current blocking layer 6.
A cap layer 8 is laminated on the p-type second cladding layer 7 to form a p-type compound semiconductor layer 14. And
On the compound semiconductor layer 14, an electrode 15 having an Au layer 9, an impurity absorption layer 10, an impurity barrier layer 11, a surface layer 12, and a plated conductive layer 13 in this order is formed.

In FIG. 1, the substrate 1 constituting the semiconductor light emitting device of the present invention is not particularly limited in its conductivity and material as long as a crystal having a double hetero structure can be grown thereon. Not done. Preferred is a conductive substrate. More specifically, GaAs, GaP, GaN, AlAs, Al suitable for growing a crystal film on a substrate.
III-V such as P, AlN, InAs, InP, InN
Group, ZnSe, ZnTe, ZnS, CdSe, CdT
A II-VI group compound semiconductor substrate such as e, CdS, a sapphire substrate, Si or the like can be used. In particular, it is preferable to use a crystal substrate having a zinc blende structure. In this case, the substrate crystal growth surface is preferably a low-order plane or a plane crystallographically equivalent thereto, and most preferably a (100) plane. Note that in this specification, the (100) plane does not necessarily have to be exactly the (100) plane, but includes a case having an off-angle of about 30 ° at the maximum. The upper limit of the off-angle is preferably 30 ° or less, more preferably 16 ° or less. The lower limit is preferably 0.5 ° or more, more preferably 2 ° or more, still more preferably 6 ° or more, and most preferably 10 ° or more.

On the substrate 1, a thickness of 0.2 to 2 μm is usually used so that defects of the substrate are not introduced into the epitaxial growth layer.
It is preferable to form a buffer layer of the order.

On the substrate 1, a p-type compound semiconductor layer 14 including the active layer 3 is formed. The p-type compound semiconductor layer 14
Layers having a lower refractive index than the active layer are included above and below the active layer 3, of which the substrate-side layer functions as an n-type cladding layer and the other epitaxial-side layer functions as a p-type cladding layer.
The magnitude relationship between the refractive indices can be adjusted by appropriately selecting the material composition of each layer according to a method known to those skilled in the art. For example, Al _x Ga _{1 -x} As, (Al
_{x Ga 1-x) 0.5 In} 0.5 P, the cladding layer comprising the composition of Al such as Al _x Ga _1-x N, it is possible to adjust the refractive index by changing the Al composition.

The n-type cladding layer 2 is more refracted than the active layer 3.
It is formed of a material having a low rate. Further, the n-type cladding layer 2
Must be larger than the refractive index of the p-type cladding layer.
Is preferred. For example, p-type GaInP, AlGaIn
P, AlInP, AlGaAs, AlGaAsP, Al
GaInAs, GaInAsP, GaN, AlGaN,
AlGaInN, BeMgZnSe, MgZnSSe,
General III-V group, II-VI group such as CdZnSeTe
Semiconductors can be used. Capacitor of n-type cladding layer 2
Rear concentration, lower limit is 1 × 10¹⁸cm^-3More preferably,
3 × 10¹⁸cm ^-3More preferably, 5 × 10¹⁸cm
^-3The above is most preferred. The upper limit is 2 × 10 ²⁰cm^-3The following
Preferably 5 × 10¹⁹cm^-3The following is more preferable, and 3 ×
10¹⁸cm^-3The following are most preferred.

The n-type cladding layer 2 is a single layer.
In some cases, preferably 0.5 to 4 μm, more preferably
Has a thickness of about 1 to 3 μm. Also, n-type cladding
The layer 2 may be composed of a plurality of layers.
Is GaInP, AlGaInP or AlI on the active layer side.
an nP cladding layer and an n-type
Layer made of AlGaAs or AlGaAsP
Can be exemplified. This and
The thickness of the layer on the active layer side is preferably thin,
The lower limit of the thickness is preferably 0.01 μm or more, and 0.0
5 μm or more is more preferable. 0.5 μm as upper limit
Or less, more preferably 0.3 μm or less. Ma
The carrier concentration of the layer on the substrate side is 2 × 1 as the lower limit.
0¹⁷cm^-3More preferably, 5 × 10¹⁷cm^-3That's all
Is more preferable. 3 × 10 as upper limit ¹⁸cm^-3The following is preferred
2 × 10¹⁸cm^-3The following is more preferred.

The structure of the active layer 3 constituting the semiconductor light emitting device of the present invention is not particularly limited, and in the example of FIG.
It has a double quantum well (DQW) structure. Specifically, the double quantum well (DQW) structure has a light confinement layer (non-doped) 31, a quantum well layer (non-doped) 32, a barrier layer (non-doped) 33, and a quantum well layer (non-doped) 34.
And a confinement layer (non-doped) 35 are sequentially laminated. In addition to this double quantum well (DQW) structure,
For example, a single quantum well structure (SQW) including a quantum well layer and a light confinement layer sandwiching the quantum well layer from above and below,
A multi-quantum well structure having three or more quantum well layers, a barrier layer sandwiched between them, and an optical confinement layer stacked above the uppermost quantum well layer and below the lowermost quantum well layer may be used. . By making the active layer 3 have a quantum well structure, the wavelength can be shortened (from 630 nm to 6 nm) as compared with a single bulk active layer.
60 nm) and a lower threshold can be achieved.

The material of the active layer 3 is GaAs, Al
GaAs, GaInP, AlGaInP, GaInA
s, AlGaInAs, GaInAsP, GaN, Ga
InN can be exemplified. In the case of a material containing Ga and In as constituent elements, a natural superlattice is easily formed. Therefore, the effect of suppressing the natural superlattice is enhanced by using an off-substrate.

On the active layer 3, a p-type clad layer is formed. Although the number of p-type cladding layers in the semiconductor light emitting device of the present invention is not particularly limited, it is preferable to form two or more p-type cladding layers from the viewpoint of improving the efficiency of confining light in the active layer 3. Hereinafter, the p-type first cladding layer 4 and the p-type second cladding layer 7 will be described in order from the one closer to the active layer 3.

The p-type first cladding layer 4 is formed of a material having a lower refractive index than the active layer 3. For example, p-type Al
GaInP, AlInP, AlGaAs, AlGaAs
P, AlGaInAs, GaInAsP, AlGaIn
N, BeMgZnSe, MgZnSSe, BeMgZn
General III-V group such as SSe, CdZnSeTe, II
-VI semiconductors can be used. When the p-type cladding layer is made of a group III-V compound semiconductor containing Al, GaAs or GaAs is formed on substantially the entire surface on which the p-type cladding layer can be grown.
Al such as sP, GaInAs, GaInP, and GaInN
It is preferable to cover with a group III-V compound semiconductor containing no, since surface oxidation can be prevented.

The carrier concentration of the p-type first cladding layer 4 is:
The lower limit is preferably 2 × 10 ¹⁷ cm ⁻³ or more, and 5 × 10 ¹⁷ c
m ^-3 or more is more preferable, and 7 × 10 ¹⁷ cm ^-3 or more is most preferable. The upper limit is preferably 5 × 10 ¹⁸ cm ⁻³ or less, and 3
× 10 ¹⁸ cm ^-3, more preferably less, 2 × 10 ¹⁸ cm ^-3
The following are most preferred. 0.01 μm as the lower limit of thickness
Or more, more preferably 0.05 μm or more,
Most preferably, it is 0.07 μm or more. The upper limit is 0.
It is preferably at most 5 μm, more preferably at most 0.3 μm, most preferably at most 0.2 μm.

The p-type first cladding layer 4 is formed on the active layer 3. In a preferred embodiment of the present invention, the refractive index of the p-type first cladding layer 4 is smaller than the refractive index of the n-type cladding layer 2. By adopting such an embodiment, the light distribution (near-field image) can be controlled so that light effectively seeps from the active layer to the light guide layer side. Further, since the optical waveguide loss from the active region (the portion where the active layer is present) to the impurity diffusion region can be reduced, it is possible to achieve improvement in laser characteristics and reliability in high-power operation.

Further, a cap layer (not shown) can be further formed on the p-type first cladding layer 4. By forming such a cap layer, at least when the p-type second cladding layer 7 is regrown at least in the opening, it is possible to easily prevent the generation of a high-resistance layer that increases the passage resistance at the regrowth interface. become able to. Further, the cap layer may function as an etching stop layer. For the cap layer, a material that is hardly oxidized or easy to clean even when oxidized can be used. Specifically, the content of an easily oxidizable element such as Al is low (about 0.3 or less).
III-V compound semiconductor layers.

The surface protective film 5 used for groove formation and selective growth is preferably a dielectric material.
SiNx film, SiO ₂ film, SiON film, Al ₂ O ₃ film, Z
It is selected from the group consisting of an nO film, a SiC film, and amorphous Si. The surface protective film 5 is formed by MOCVD as a mask.
It is used when a groove is formed by selective regrowth using a method such as the above.

The current blocking layer 6 is formed on the p-type first cladding layer 4 and has an opening. Basically, a current is injected into the active layer 3 from the opening. Current block layer 6
Is preferably a semiconductor from the viewpoint of heat dissipation, cleavage, and contact resistance. The current blocking layer 6
Is lower than the refractive index of the p-type second cladding layer 7 (actual refractive index guide structure) in order to reduce the operating current as compared with the conventional loss guide structure. p-type second cladding layer 7
In consideration of lowering the refractive index and lattice matching with the GaAs substrate, it is preferable to use AlGaAs or AlGaAsP as a semiconductor, or AlGaInP or AlInP as a material for the current blocking layer 6.

The current blocking layer 6 is formed from two or more layers having different refractive indices, carrier concentrations or conductivity types in order to control the light distribution (particularly the light distribution in the lateral direction) and to improve the current blocking function. May be. Further, the conductivity type of the current blocking layer 6 may be any of n-type or high resistance (undoped or doped with an impurity (O, Cr, Fe, or the like that forms a deep order)), or a combination of the two. It may be formed from a plurality of layers having different conductivity types or compositions. For example, a current blocking layer formed in the order of a p-type or high-resistance semiconductor layer and an n-type semiconductor layer from the side close to the active layer 3 can be preferably used. Further, if the thickness is too small, it may cause a problem in blocking the current. Therefore, the thickness is preferably 0.1 μm or more, and more preferably 0.5 μm or more. In consideration of the size of the element, it is preferable to select from the range of about 0.1 to 3 μm.

As the upper layer of the current blocking layer 6, the p-type second cladding layer 7 is formed so as to reach the inside of the opening and at least part of the current blocking layer 6 on both sides of the opening. The p-type second cladding layer 7 is formed so as to cover the entire upper surface of the opening and extend partially on the current block layer 6 on both sides of the opening. Since the p-type second cladding layer 7 is formed so as to extend to a part of the current blocking layer 6 on both sides of the opening by using the current blocking layer 6 as it is, the element characteristics are sufficiently stabilized. be able to.

The carrier concentration of the p-type second cladding layer 7 is
The lower limit is preferably 5 × 10 ¹⁷ cm ⁻³ or more, and 7 × 10 ¹⁷ c
m ^-3 or more is more preferable, and 1 × 10 ¹⁸ cm ^-3 or more is most preferable. The upper limit is preferably 1 × 10 ¹⁹ cm ⁻³ or less, and 5
× 10 ¹⁸ cm ^-3 or less is more preferable, and 3 × 10 ¹⁸ cm ^-3
The following are most preferred.

The lower limit of the thickness of the p-type second cladding layer 7 is set at 0. 0, taking into consideration that if the thickness is too small, light confinement will be insufficient, and if the thickness is too large, the passage resistance will increase.
5 μm or more is preferable, and 1.0 μm or more is more preferable. The upper limit is preferably 3.0 μm or less, more preferably 2.0 μm or less.

The current blocking layer 6 and the p-type second cladding layer 7
It is preferable to form the cap layer 8 having a low resistance (high carrier concentration) in order to reduce the contact resistance with the electrode material before the formation of the electrode 15 after the formation.
In particular, it is preferable to form the electrode after forming the cap layer 8 on the entire uppermost layer surface on which the electrode 15 is to be formed.

At this time, the material of the cap layer 8 is usually selected from materials having a smaller band gap than that of the cladding layer, and preferably has a low resistance and an appropriate carrier density in order to obtain ohmic contact with the metal electrode. . The lower limit of the carrier density is preferably 1 × 10 ¹⁸ cm ⁻³ or more, and 3 × 10
¹⁸ cm ^-3 or more, and most preferably 5 × 10 ¹⁸ cm ^-3 or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 3 × 10 ¹⁹ cm ⁻³ or less, and 2 × 10 ¹⁹ cm ^−3.
cm ^-3 or less is most preferred. The thickness of the cap layer is 0.
It is preferably from 01 to 1000 µm, more preferably from 0.1 to 20 µm, most preferably from 0.5 to 7 µm.

In manufacturing the p-type compound semiconductor layer 14 in the semiconductor light emitting device of the present invention, a conventionally used method can be appropriately selected and used. The method of growing the crystal is not particularly limited. For the crystal growth of the double hetero structure and the selective growth of the current block layer, the metal organic chemical vapor deposition (MOCVD), the molecular beam epitaxy (MBE), A known growth method such as a hydride or halide vapor phase growth method (VPE method) or a liquid phase growth method (LPE method) can be appropriately selected and used.

Although the specific growth conditions and the like of each layer vary depending on the composition of the layer, the growth method, the shape of the device, and the like, when growing a III-V compound semiconductor layer using the MOCVD method, a double heterostructure is used. Means that the growth temperature is about 650 to 750 ° C.
III ratio of about 20 to 60 (in the case of AlGaAs) or about 300 to 600 (InGaAsP, AlGaInP
), The block layer has a growth temperature of 600 to 700 ° C., and V
III ratio about 40-60 (in case of AlGaAs) or 3
It is preferable to perform the process at about 50 to 550 (in the case of InGaAsP and AlGaInP).

Electrode 1 constituting semiconductor light emitting device of the present invention
5 has an Au layer 9 in contact with the p-type compound semiconductor layer 14, an impurity absorbing layer 10, an impurity barrier layer 11, and a surface layer 12 in this order. In FIG. 1, the Au layer 9 can make ohmic contact with the cap layer 8 of the p-type compound semiconductor layer 14, and functions as an ohmic contact layer. The Au layer 9 in the present invention is formed only of Au. Au is a material having a large work function that can reduce a barrier height (ΦBP) generated when a semiconductor and an electrode are joined.
The effect of sucking out group elements is particularly large. Therefore, Au
The layer 9 forms an intermediate composition on the surface of the Au layer 9 with the group III element sucked up from the p-type compound semiconductor layer 14 in an alloying step to be described later, and forms a physical junction and an electrical junction between the semiconductor and the electrode. Obtainable. Due to such advantages of Au, the present invention uses only pure Au metal instead of Au alloy (for example, AuZnNi alloy) as the ohmic contact layer. By using only Au, it is possible to obtain many intermediate compositions that can contribute to lowering the contact resistance, and it is possible to dramatically reduce the contact resistance.

The Au layer 9 has an effect of absorbing Ga contained in the lower cap layer 8. Therefore, the Au layer 9
Is thick, Ga in the cap layer 8 is sucked out, and the thickness of the cap layer 8 (cap layer) is undesirably reduced. Then, in the present invention, Au
The thickness of the layer 9 is preferably 1 μm or less.
9 μm or less is more preferable, and 0.8 μm or less is further preferable.

In the electrode 15, the impurity absorbing layer 10 is laminated on the Au layer 9. The impurity absorbing layer 10 has a function of trapping the group III element absorbed by the Au layer 9 and controlling the content of the group III element in the surface layer 12. Such an impurity absorbing layer 10 contains Ti. Preferably. When Ti is contained in the impurity absorption layer 10, as shown in the profile analysis result of the impurity concentration in the depth direction by the secondary ion mass spectrometry (SIMS), the Ti traps the impurities efficiently. The Ti-containing impurity-absorbing layer 10 is composed of I-V
A group II element (Ga, Al, In, etc.) can be efficiently absorbed, and in particular, a group III element that has been absorbed into the Au layer 9 and diffused into the surface of the Au layer 9 can be efficiently absorbed.

If the impurity absorption layer 10 is too thick, unnecessary distortion is likely to occur, which is not preferable. Therefore, the thickness of the impurity absorbing layer 10 is preferably 1 μm or less, more preferably 0.9 μm or less, and still more preferably 0.8 μm or less.

In the electrode 15, the impurity barrier layer 11 is further laminated on the impurity absorption layer 10. As a material for the impurity barrier layer, a material which does not itself diffuse into the surface layer and becomes an impurity (a material without electromigration)
It is necessary to have a melting point higher than a heat treatment temperature in an alloying step described later. Examples of such a material include Pt, Mo, and Ta. Pt, which has stability, has small distortion, and does not affect the properties of the surface layer 12, is preferable.

If the impurity barrier layer 11 is too thick, unnecessary distortion is likely to occur, which is not preferable. Therefore, the thickness of the impurity barrier layer 11 is preferably 1 μm or less, more preferably 0.9 μm or less, and still more preferably 0.8 μm or less.

In the electrode 15, the surface layer 12 is further laminated on the impurity barrier layer 11. Thereafter, the surface layer 12 is bonded to a carrier. For this reason, it is necessary that the material be capable of performing good bonding, and a material containing Au is preferable as such a material. The thickness of the surface layer 12 is preferably 10 nm or more,
It is more preferably 20 nm to 100 μm,
It is more preferable that the thickness be from nm to 20 μm.

The Au layer 9 of the electrode 15, the impurity absorbing layer 10,
The impurity barrier layer 11 and the surface layer 12 are formed by various film-forming methods, and an evaporation method such as electron beam evaporation or resistance heating evaporation, which relatively easily forms a film on the p-type compound semiconductor layer 14, Alternatively, it can be formed by a physical film formation method such as a dry process such as sputtering.
In addition to the physical film forming method, a wet process such as an electrolytic plating method or an electroless plating method, or a known chemical film forming method such as a metal spraying method may be used. For example, as a wet process, each layer of the electrode 15 can be formed using an Au plating solution comprising 1 wt% of potassium sulfite, 1 wt% of citric acid, 1 wt% of sodium sulfite, and sodium gold sulfite (Au 50 g / l).

In the electrode 15, a plated conductive layer 13 can be further formed on the surface layer 12. Plating conductive layer 13
By laminating on the surface layer 12 and increasing the thickness of the surface layer 12, the bonding property at the time of bonding such as die bonding or wire bonding can be improved. In addition, it is possible to improve heat dissipation due to junction down, adjustment of the height of the light emitting point, and the like.

The material of the plated conductive layer 13 is not particularly limited as long as it is a conductive metal.
g, Au-Ag, Ni, Cu, Sn + Sb, Sn-N
The plated conductive layer 13 may be formed of a conductive metal such as i, Pd, Ru, and Rh. The thickness of the plating conductive layer 13 is preferably 100 μm or less, more preferably 20 μm or less, and even more preferably 18 μm or less.

The method for forming the plated conductive layer 13 is not particularly limited. For example, the plated conductive layer 13 is formed by plating while applying a current from the frame-shaped electrode provided on the electrode 15 or the periphery of the electrode 15. (JP-A-11-284285). In addition, similarly to the method of forming the electrode 15, the electrode 15 can be formed by a known forming method, but is preferably formed by a chemical film forming method such as an electrolytic plating method, an electroless plating method, or a metal spraying method. In the case of forming by an electroplating method or an electroless plating method, the plating solution is not particularly limited, and a Ni plating solution, Cu
Various plating solutions such as a plating solution and an Ag plating solution can be used.

In the semiconductor light emitting device of the present invention, after the substrate 1 is thinned to a desired thickness, a conductive layer (not shown) can be formed on the N side of the substrate as needed. The material of the conductive layer is preferably a material that can make ohmic contact with the n-type compound semiconductor. As such a material, AuGeN
An i alloy or the like is used. Specifically, the substrate 1 is AuGe
Ni / Au is formed, and Ti / Pt / Au is further formed. The method for forming such a conductive layer is as follows.
There is no particular limitation, and the film can be formed using any of the above various film formation methods.

In the formation of the electrode, a heat treatment process called an alloy is further performed for the purpose of realizing better ohmic contact resistance and strengthening the bonding between the semiconductor and the electrode material. Generally, if the alloy temperature is too low, ohmic contact cannot be made and a long processing time is required. on the other hand,
If the alloy temperature is too high or the alloy time is too long, the constituent materials of the semiconductor and the ohmic contact layer diffuse to the surface of the surface layer, deteriorating the surface state of the surface layer, and at the same time, having poor electrical characteristics. It causes bonding failure. Therefore, in order to obtain desired adhesiveness and bonding strength by using an alloy, an appropriate alloy temperature and alloy time according to the semiconductor material and the electrode material are indispensable. The present inventors, after trial and error, Au
In the case of a semiconductor light emitting device having an electrode structure of / Ti / Pt / Au, it has been found that by performing alloying within a predetermined temperature range, adhesion and bonding strength can be improved.

That is, the alloy temperature in the production method of the present invention is preferably set to 600 ° C. or less,
More preferably 600 ° C, 300 to 600 ° C
Is more preferable. The alloy holding time in the production method of the present invention is preferably 24 hours or less, more preferably 12 hours or less, and 6 hours or less.
More preferably, it is 0 minutes or less.

The semiconductor light emitting device formed as described above is further cleaved in a direction perpendicular to the resonator of the semiconductor laser to form a rod-shaped laser array. The cleavage end face of this laser bar is coated with a composite film of SiNx, Si, Al ₂ O ₃ or the like. The coating method is not particularly limited, and a known forming method such as a sputtering method, an electron beam evaporation method, or a resistance heating evaporation method may be used.

After the coating is completed, the device is further cleaved to obtain an LD chip. An LD chip becomes a product through a bonding process. Generally, an LD chip has A
Die bonding is performed on a carrier coated with a uSn solder film or a PbSn solder film. For example, an AuSn solder film (Au70) having a thickness of 1 to 90 μm is formed on the LD chip surface.
%, Sn 30%), the die bonding is performed at a temperature slightly higher than the eutectic temperature of Au and Sn. At this time, the pressing pressure is about several kg / cm ² , and the pressing time is several seconds. In the semiconductor light emitting device of the present invention, the pressing pressure is 1 to 10 kg / cm ² , and the bonding temperature is A
It is preferable to carry out the process at about 380 ° C. slightly higher than the eutectic temperature of u and Sn, and for a pressing time of 2 to 15 seconds.

The material of the solder used for the die bonding is not particularly limited, and PbSn, A
A known material such as uSi or AuGe may be used. Further, the material of the carrier is not particularly limited.
_{-CBN, BeO, SiC, Al 2} O 3, W, Mo, C
Known materials such as u, Si, and GaAs can be used.

The surface electrode of the LD chip die-bonded to the carrier is subjected to wire bonding. Generally, the material of the wire is not particularly limited.
Known materials such as 1, Al alloy, and Cu are used, and the wire diameter is several tens of μm. The conditions for wire bonding are generally such that an arbitrary ultrasonic wave is applied and the pressing load is about several tens g. In the semiconductor light emitting device of the present invention, an Au wire having a wire diameter of 10 to 90 μm can be wire-bonded to the surface of the p-side conductive layer. Wire bonding is performed with a pressing pressure of 10 to 300 g and 10 to 300 g.
It is preferable to apply 800 mW ultrasonic vibration for 0.01 to 0.9 seconds.

The assembling of the semiconductor light emitting device may be performed at a junction up or at a junction down. In particular, junction down is a structure in which the epitaxial side with the conductive layer is attached to the carrier by die bonding or the like. Compared with junction up, the heat generation part near the light emitting point can be attached relatively close to the carrier, so heat dissipation The effect can be improved.

The LD chip formed as described above is usually assembled together with a heat sink and a light output monitoring photodiode in a CAN package or the like in a nitrogen atmosphere. Recently, for the purpose of miniaturization and cost reduction, an LD chip may be assembled as an integrated optical pick integrated with an optical component.

[0060]

Now, the present invention will be described in further detail with reference to the following specific examples of the present invention. Materials, reagents, ratios, operations, and the like shown in the following examples can be appropriately changed without departing from the spirit of the present invention. Therefore, the scope of the present invention is not limited to the following specific examples.

Example 1 In this example, a semiconductor light emitting device was manufactured by forming each layer in the order shown in FIG. 2 (a) to 2 (c), there are portions where the dimensions are intentionally changed in order to facilitate understanding of the structure, but the actual dimensions are as described in the following text.

On a n-type GaAs (n = 1 × 10 ¹⁸ cm ⁻³ ) substrate 101 having a thickness of 350 μm and a (100) surface, a 1.0 μm-thick n-type GaAs is formed by MOCVD.
s buffer layer (non-doped (not shown), thickness 1.5
μm n-type AlGaAs (Si-doped: n = 1 × 10 ¹⁸⁾
cm ⁻³ ) n-type cladding layer 102, thickness 70 nm
AlGaAs (non-doped) active layer 103 having a thickness of 0.
4 μm p-type AlGaAs (Zn doped: p = 6 × 10
¹⁷ cm ^-3 ) p-type first cladding layer 104, thickness 1
50 nm SiNx surface protective film 105, thickness 0.5 μm
N-type GaAs (Si-doped: n = 2 × 10 ¹⁸ cm ⁻³ )
N-type current blocking layer 106 made of p-type AlGaAs (Zn doped: p = 1.5 × 10 ¹⁸ c) having a thickness of 1 μm
m ⁻³ ), a p-type second cladding layer 107 having a thickness of 0.3
μm p-type GaAs (Zn doped: p = 1.5 × 10 ¹⁹⁾
(cm ⁻³ ) to form a compound semiconductor layer having a double hetero structure (FIG. 2).
(A)).

In order to form a p-type electrode on the compound semiconductor layer, an Au layer 109 having a thickness shown in Table 1 was laminated on the upper surface of the p-type GaAs cap layer 108 by using photolithography and an electron beam evaporator. (FIG. 2 (b)). Next, a Ti layer 110 and a Pt layer 111 are formed on the Au layer 109.
Then, an Au layer 112 was sequentially formed (FIG. 2 (c)). Thereafter, alloying was further performed in a nitrogen atmosphere at an alloy temperature and time shown in Table 1.

[0064]

[Table 1]

(Example 2) Table 2 shows the difference in contact resistance based on the difference in the metal in contact with the p-type GaAs compound semiconductor. The upper column of Table 2 is a semiconductor light emitting device having the electrode structure of the present invention, and the middle column is Pt instead of Au.
The lower column compares the electrodes formed directly from Ti directly without providing an Au layer or a Ti layer. At this time, the thickness of the Au layer and the Ti layer is 10 nm, and the impurity absorption layer (T
An electrode was formed with the thickness of i) being 50 nm, the thickness of the impurity barrier layer (Pt) being 60 nm, and the thickness of the surface layer (Au) being 500 nm.

[0066]

[Table 2]

As can be seen from Table 2, when Au was used as the contact metal on the p-type GaAs compound semiconductor, the electrode structure was not as good as when Pt was used or when the electrode structure was formed directly from Ti directly without providing an Au layer or a Pt layer. It can be seen that the contact resistance could be reduced.

Table 3 shows Au of the contact metal on the p-type GaAs compound semiconductor in the semiconductor light emitting device of the present invention.
It shows the relationship between the layer thickness and the contact resistance.

[0069]

[Table 3]

According to Table 3, the thickness of the Au layer of the contact metal is 50
When the contact resistance is less than
Since the contact resistance is smaller than the contact resistance of the electrode having no u layer (the thickness of the Au layer = 0), it can be seen that the contact resistance is reduced.

Table 4 shows the relationship between the alloy temperature and the contact resistance in the semiconductor light emitting device of the present invention.

[0072]

[Table 4]

As shown in Table 4, the alloy temperature was set to 600 ° C.
When performed at a higher temperature, the contact resistance is 5.75.
It can be seen that a low contact resistance can be realized in about 5 minutes at a temperature of 600 ° C. or less, while it is × 10 ⁻⁷ Ωcm ² .

Example 3 The state of the interface reaction between the electrode and the compound semiconductor layer in the semiconductor light emitting device of the present invention was analyzed by Auger electron spectroscopy (AES). At an alloy temperature of 600 ° C. or less, the element (Ga, As, Al, etc.) of the compound semiconductor layer and the Au element in the ohmic contact layer form a compound, and this compound contributes to lower contact resistance. Was revealed.
Such compounds include, for example, AuGa, AuA
s, AuAl, AuAlAs, AuAlGa, AuAs
Ga and the like.

EXAMPLE 4 FIGS. 3A and 3B show a case where Au is used as a metal of a metal layer in contact with a compound semiconductor layer of the present invention and a case where Pt used in a conventional method is used for comparison. 2 shows the adhesion strength between the electrode and the compound semiconductor layer in FIG. The measuring method is that the contact area of the needle on the electrode surface is about 1
A 963 × 10 ⁻¹² m ² palladium needle was applied once, and the area where the electrode was peeled was evaluated by the ratio to the electrode area in the initial state before the needle was applied. A as ohmic contact layer
When u was used, the adhesion was improved by about 1.1 times or more as compared with the case where conventional Pt was used, and it was confirmed that this was sufficiently practical.

FIG. 4 shows the dependence of the morphology of the outermost surface on the Au film thickness after the electrodes of the semiconductor light emitting device of the present invention are alloyed at 600 ° C. or lower. Au film thickness is 1
It was found that the morphology of the outermost surface of the electrode was good when it was in the range of 000 nm or less. FIG.
9 shows the dependence of the morphology of the outermost surface of the electrode on the alloy temperature when the thickness of the Au layer of the electrode in the semiconductor light emitting device of the present invention is in the range of 1000 nm or less. When the alloy temperature was in the range of 600 ° C. or less, it was found that the morphology of the outermost surface of the electrode was good.

[0077]

The semiconductor light emitting device according to the present invention can realize an ohmic electrode on a GaAs compound semiconductor, has a lower contact resistance than a conventional semiconductor light emitting device having an electrode structure, and has a low resistance to a compound semiconductor. Electrode (metal)
Can improve the adhesiveness at the interface. Also,
The semiconductor light emitting device of the present invention can dramatically improve characteristics such as Vop, laser life, yield, and the like, and can contribute to cost reduction in an industrial production process.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory view for explaining a structure of a semiconductor light emitting device of the present invention.

FIG. 2 is a process diagram illustrating an example of a manufacturing process of the semiconductor light emitting device of the present invention.

FIG. 3 is a comparative explanatory diagram of the adhesion strength of the electrodes of the semiconductor issuing device of the present invention.

FIG. 4 is an explanatory diagram showing the dependence of the morphology of the electrode surface of the semiconductor light emitting device of the present invention on the Au film thickness.

FIG. 5 is an explanatory diagram showing the dependence of the morphology of the electrode surface of the semiconductor light emitting device of the present invention on the alloy temperature.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 n-type cladding layer 3 active layer 4 p-type first cladding layer 5 surface protection film 6 current blocking layer 7 p-type second cladding layer 8 cap layer 9 Au layer 10 impurity absorption layer 11 impurity barrier layer 12 surface layer 13 Plating conductive layer 14 p-type compound semiconductor layer 15 electrode 31 optical confinement layer 32 quantum well layer 33 barrier layer 34 quantum well layer 35 optical confinement layer 101 n-type GaAs substrate 102 n-type AlGaAs cladding layer 103 AlGaAs active layer 104 p-type AlGaAs layer 1 clad layer 105 SiNx surface protective film 106 n-type GaAs current blocking layer 107 p-type AlGaAs second clad layer 108 p-type GaAs cap layer 109 Au layer 110 Ti layer 111 Pt layer 112 Au layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 AA04 AA05 AA06 AA10 BB09 BB11 CC01 DD34 DD35 DD37 DD43 DD52 DD53 DD78 DD83 EE06 EE14 EE16 EE17 FF03 FF17 GG04 HH08 HH15 5F073 AA07 CB07 DA05 CB02 DA05 CB02

Claims (12)

[Claims] 1. A semiconductor light emitting device having a compound semiconductor layer and an electrode on a substrate, wherein the electrode includes an Au layer, an impurity absorption layer, an impurity barrier layer, and a surface layer that are in contact with a p-type compound semiconductor layer. A semiconductor light emitting device characterized by having in this order. 2. The semiconductor light emitting device according to claim 1, wherein the thickness of the Au layer is 1 μm or less. 3. The semiconductor light emitting device according to claim 1, wherein the impurity absorption layer is a layer containing Ti. 4. The semiconductor light emitting device according to claim 1, wherein said impurity barrier layer is a layer containing Pt. 5. The semiconductor light emitting device according to claim 1, wherein said surface layer is a layer containing Au. 6. The semiconductor light emitting device according to claim 1, wherein said electrode further has a plated conductive layer on said surface layer. 7. A semiconductor light emitting device comprising: a step of forming a substrate; a step of forming a compound semiconductor layer; and a step of forming an electrode by laminating an Au layer, an impurity absorption layer, an impurity barrier layer, and a surface layer in this order. In the manufacturing method, in the step of forming the electrode, after stacking an Au layer, an impurity absorption layer, an impurity barrier layer, and a surface layer by a film forming method,
A method for manufacturing a semiconductor light emitting device, wherein an electrode is formed by performing alloying at 0 ° C. or lower. 8. The method according to claim 7, wherein the film forming method is performed by a physical film forming method. 9. The method according to claim 1, wherein the physical film forming method is electron beam evaporation,
The method according to claim 8, wherein the method is performed by resistance heating evaporation or sputtering. 10. The method according to claim 1, wherein the step of forming the electrode includes a step of forming a plating conductive layer on the surface layer after forming the surface layer and before performing the alloying. Item 10. The method for manufacturing a semiconductor light emitting device according to any one of Items 7 to 9. 11. The method according to claim 10, wherein the plating conductive layer of the electrode is formed by a chemical film forming method. 12. The method according to claim 11, wherein the chemical film forming method is performed by an electrolytic plating method, an electroless plating method, or a metal spraying method.