JP2002353412A - Semiconductor memory device and method for storing information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a resistance value of a capacitor after a breakdown without breaking a conduction in a semiconductor memory device utilizing a dielectric breakdown of the capacitor. SOLUTION: The semiconductor memory device comprises a variable voltage source 1, the capacitor 2 connected to the voltage source 1, an overcurrent suppressing circuit 5, having a parallel connecting circuit of a first resistor 3 and a second resistor 4 having a larger resistance value than that of the first resistor 3, and a controller 8 connected to the suppressing circuit 5. A high voltage is applied to the source 1, so that the capacitor 2 dielectric breaks down, and a large current flows to the resistor 3. Since the resistor 3 is disconnected by the current, damages due to the large current will not occur at the other part of the circuit. Even if the resistor 3 is disconnected, the entire circuit is not disconnected due to the presence of the resistor 4 which has a large resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a device having a capacitor and storing information by applying a high voltage to cause a dielectric breakdown of the capacitor.

[0002]

2. Description of the Related Art As a semiconductor memory device, there is known a semiconductor memory device having a capacitor therein and storing information depending on whether or not a high voltage is applied to the capacitor to break an insulating layer in the capacitor. .

FIG. 12 shows an equivalent circuit of a conventional semiconductor memory device. In a conventional semiconductor memory device, a variable voltage source 101 is connected to a capacitor 102, and the capacitor 102 is connected to a control unit 118 including a first transistor 103 and a second transistor 104.

[0004] Information is stored as follows. The second transistor 104 is turned on while the first transistor 103 is kept off. Second transistor 104
Is grounded, so that the second transistor 104
By performing N, the potential of the cathode of the capacitor 102 becomes 0V. By setting the variable voltage source 101 to a high voltage higher than the withstand voltage of the capacitor 102,
Causes dielectric breakdown and enters a state of storing information. For example, a state where the dielectric breakdown of the capacitor 102 is defined as information “1” is stored, and a state where the dielectric breakdown is not performed is defined as storing information “0”. At this time, the current supplied from the variable voltage source 101 is
Through transistor 104 to ground.

[0005] Reproduction of information is performed as follows. First, the voltage of the variable voltage source 101 is set to a low voltage. Next, the second transistor 104 is turned off, and the first transistor 10 is turned off.
Turn 3 ON. When the information “1” is stored, the capacitor 102 is connected to the first transistor 1 from the variable voltage source 101 because the electrodes are electrically connected.
03, and a current is output. On the other hand, when the information "0" is stored, the capacitor 102 is not destroyed and the electrodes are kept insulated, so that no current is output to the outside. Therefore, the information "1" or "1"
It can be determined whether "0" has been stored.

[0006]

However, if the electrodes forming the capacitor 102 in the conventional semiconductor memory device are made of Si in which impurities are diffused at a high concentration, the resistance value of the capacitor 102 after dielectric breakdown becomes extremely high. There is a problem that becomes higher. When the resistance value of the capacitor 102 is high, the value of the current output from the first transistor 103 is low, so that it is difficult to determine whether the information “1” is stored at the time of output. Although it is possible to reduce the resistance value of the capacitor 102 after dielectric breakdown by increasing the area of the electrode, a new problem arises in that it becomes difficult to reduce the size of the device.

On the other hand, there has been proposed a semiconductor memory device which solves the above-mentioned problem by forming the electrode of the capacitor 102 with a metal material. FIG. 13 is a sectional view showing an example of a semiconductor memory device in which the electrodes of the capacitor are made of metal. A first electrode 117 made of a metal material and a metal region 111 whose surface is covered with a barrier metal region 112
Has a structure in which the dielectric layer 113 is sandwiched between the capacitors 11.
9 are configured. The first electrode 117 is connected to the variable voltage source 101 (not shown). The metal region 111 in contact with the barrier metal region 112 is connected to the first transistor 103 and the first transistor 103 (not shown) through the external connection conductive layer 114. 2 transistor 104. When the electrodes of the capacitor 102 are formed of metal as described above, the resistance value of the capacitor 102 whose insulation has been broken can be reduced. Therefore, there is an advantage that a sufficient current is output when the information "1" is reproduced, and the stored information "1" or "0" can be easily determined.

However, when the electrode of the capacitor 102 is made of metal, a new problem arises that is different from the case where Si is used for the electrode. When the resistance value of the capacitor 102 after the insulation breakdown is reduced, the current flowing immediately after the breakdown of the insulating film becomes extremely large in the circuit including the variable voltage source 101, the broken capacitor 102, and the second transistor 104. In the above example, the voltage of the variable voltage source 101 immediately after the storage of the information “1” remains at 8 to 10 V, and the resistance of the capacitor 102 after breakdown when a metal material is used for the electrode is 500Ω or less. The current flowing in the semiconductor memory device is 16 to 20 mA. Generally, when a current of 10 mA or more flows in a circuit of a semiconductor device, a surface wiring, a bonding wire, and the like may be broken. Therefore, in a semiconductor memory device using a metal material as an electrode of the capacitor 102, there is a possibility that a surface wiring, a bonding wire, and the like of a circuit may be broken by a current flowing immediately after the insulating layer of the capacitor 102 is broken. If the surface wiring or the like is broken and the circuit is disconnected, a current may not be output at the time of reproduction even though the information "1" is stored. Further, even when the circuit is not disconnected, there is a problem that a large current flows to cause power loss.

In order to avoid destruction of the surface wiring and the like in the circuit, the capacitor 102 and the control unit 118 in the circuit of FIG.
It is conceivable to connect a resistor having a high resistance value between them. For example, in the above example, in order to suppress the current flowing through the circuit immediately after the destruction of the capacitor to about 1 mA, a resistor of 8 to 10 kΩ may be connected. By doing so, it is possible to prevent a large current from flowing in the semiconductor memory device immediately after the dielectric breakdown of the capacitor. However, a new problem arises in this case as well. Since the resistance value of the dielectric breakdown of the capacitor 102 generally depends on the magnitude of the current flowing through the capacitor 102 at the time of dielectric breakdown, when the current at the time of breakdown of the capacitor is about 1 mA, the capacitor is not sufficiently destroyed and after the dielectric breakdown. Have higher resistance values. Therefore, the information "is similar to the case where Si is used for the electrode of the capacitor 102.
A problem arises in that a sufficient current cannot be output during the reproduction of 1 ".

Furthermore, a semiconductor memory device that stores information "1" by destroying a capacitor is used for a DRAM having a memory cell and a redundant circuit for replacing a defective memory cell with a redundant memory cell. There are many. In other words, it is used to store information for replacing a defective memory cell found in an inspection stage after package sealing with a redundant memory cell in a redundant circuit. In this case, it is manufactured on the same semiconductor substrate as the DRAM memory cell. Is done. Therefore, when the structure of the semiconductor memory device is significantly different from the structure of the DRAM memory cell, a special process is required separately in the manufacturing process, which is also inefficient.

The present invention has been made in order to solve such problems of the prior art, and an object of the present invention is to provide a semiconductor memory device capable of outputting a sufficiently large current when reproducing information. To provide.

Another object of the present invention is to provide a semiconductor memory device in which a surface wiring and a bonding wire of a circuit are not destroyed by a current flowing when information is stored.

Still another object of the present invention is to provide a semiconductor memory device capable of suppressing a large current from flowing in a circuit and suppressing power loss.

Still another object of the present invention is to provide a semiconductor memory device which can be manufactured in the same process as a memory cell when manufacturing the same on the same substrate as a memory cell of a DRAM.

[0015]

In order to achieve the above object, a first feature of the present invention is that a variable voltage source, a first electrode connected to the variable voltage source, and a first electrode arranged adjacent to the first electrode. A dielectric layer, a capacitor including a second electrode disposed adjacent to the dielectric layer, an overcurrent suppression circuit connected to the second electrode, and a control unit connected to the overcurrent suppression circuit. The gist of the present invention is that it is a semiconductor memory device. In the semiconductor memory device according to the first aspect of the present invention, information can be stored as "1" when the capacitor is destroyed and "0" when the capacitor is not destroyed. Or, the destroyed state is “0”,
The state that is not destroyed may be stored as “1”. Here, the “overcurrent suppression circuit” is used to prevent an excessive current from flowing so that a large current flowing in the semiconductor memory device when the capacitor is destroyed does not destroy the surface wiring and the bonding wire. Circuit. or,
The "control unit" is to flow the current flowing when the capacitor is destroyed to the ground, record (write) information, and output the current corresponding to the stored information to the outside when reproducing (reading) the information. It is a circuit part for performing.

In the first aspect of the present invention, by providing an overcurrent suppressing circuit, disconnection occurs in other circuit portions even though a high voltage is applied by a variable voltage source to cause a dielectric breakdown of a capacitor, and information is lost. It is possible to prevent a situation in which no current is output at the time of reproducing information despite storage. In addition, since an overcurrent suppression circuit can prevent a large current from flowing, there is an advantage that power loss can be suppressed low.

It is desirable that the overcurrent suppressing circuit be formed of a parallel circuit of a first resistor and a second resistor having a larger resistance than the first resistor. With such a configuration, when a high voltage is applied by a variable voltage source for information storage and a capacitor is destroyed, current flows to the first resistor having a low resistance value after passing through the destroyed capacitor. Flow in. Here, the first resistor is destroyed by the flow of a large current and is disconnected. However, since a second resistor having a large resistance value is connected in parallel to the first resistor, an excessive current is suppressed from flowing. For this reason, unnecessary disconnection such as unnecessary surface wiring does not occur in the entire circuit in the semiconductor memory device, and it is possible to output a current corresponding to a storage state at the time of reproducing information. Further, since a large current flows through the capacitor at the moment when the capacitor is destroyed, it is possible to prevent a disadvantage that the capacitor is not sufficiently destroyed and information cannot be sufficiently stored.

Further, the first resistance and the second resistance are equal to the second resistance.
Is 100 times the resistance of the second resistor to 10 times the resistance of the second resistor.
Desirably it is 00 times. By setting the resistance value of the first resistor and the resistance value of the second resistor in this manner, the overcurrent flows almost only to the first resistor immediately after the capacitor is destroyed, so that the first resistor can be reliably destroyed. It is possible. Also, at the time of reproducing information, it is possible to output a current with a sufficiently detectable magnitude.

It is useful that the second resistor has conductivity by diffusing impurities into the semiconductor single crystal region.
The impurity diffusion layer has an advantage that the resistance value can be adjusted by changing the impurity density, and a resistance value suitable for the second resistor can be easily set. Another advantage is that it can be easily formed in a semiconductor device.

It is also desirable that the first resistor is made of a metal material. Here, the metal material is a concept including not only a material made of the same metal but also a bonding made of different metals. This is because the metal has good conductivity, so that the first resistor having a low resistance value can be obtained.

Preferably, at least one of the first electrode and the second electrode is made of a metal material. With such a configuration of the capacitor, the resistance value of the capacitor after dielectric breakdown can be reduced. In the prior art, when the electrode of a capacitor is made of a metal material, a large current flows in the semiconductor memory device because the resistance value of the capacitor after dielectric breakdown is low. Therefore, there is a fear that wiring and bonding in the semiconductor memory device may be damaged. However, by providing the overcurrent suppression circuit in the feature of the present invention, there is no possibility that a large current flows in the semiconductor memory device immediately after the capacitor is destroyed. Therefore, it is possible to use a metal material for the electrode of the capacitor, and since the current output at the time of reproducing the information can be sufficiently detected from the outside without a low value by using the metal material, is the information stored? This has the advantage that the determination of whether or not it is easy is made. It is also desirable that at least one of the first electrode and the second electrode is made of conductive polysilicon. This is because, depending on the structure of the capacitor, it is possible to increase the area of the electrode, and in this case, even if the electrode is not made of metal, the resistance after dielectric breakdown of the capacitor becomes low.

Also, the capacitor is in contact with the U-shaped second electrode along the inner wall of the deep trench, the dielectric layer laminated on the entire inner surface of the first electrode, and the surface without the dielectric layer. It is desirable to include a first electrode formed by the above method. As a result, the surface area of the first and second electrodes becomes larger than the occupied volume, so that there is an advantage that the resistance value of the resistor formed by dielectric breakdown of the capacitor can be reduced.

A second feature of the present invention is that a plurality of DRAM memory cells and a redundant memory cell having a first capacitor provided on a partial area of a semiconductor substrate and another area of the same semiconductor substrate are provided. A semiconductor provided with a variable voltage source, a second capacitor connected to the variable voltage source, an overcurrent suppression circuit connected to the second capacitor, and a control unit connected to the overcurrent suppression circuit, provided above. This is a storage device. Here, "DRAM" is a dynamic random access memory.
And "DRAM memory cell"
Are the individual memory cells constituting The "redundant memory cell" is an extra memory cell provided in advance to replace a defective memory cell.

According to a second feature of the present invention, the first and second DRAM memory cells and the redundant memory cells are formed on the same semiconductor substrate.
Providing the semiconductor memory device according to the feature (1) has an advantage that the semiconductor memory device can be used to store information for replacing a defective memory cell with a redundant memory cell in a redundant circuit.

It is desirable that the first capacitor and the second capacitor have the same structure. Since the second capacitor has the same structure as the first capacitor forming the DRAM memory cell and the redundant memory cell, the manufacture of the capacitor can be performed in the same step in the manufacture of the semiconductor memory device, and the efficiency is improved. It has the advantage that it can be manufactured.

Also, as in the first aspect of the present invention, the overcurrent suppressing circuit is a circuit in which a first resistor and a second resistor having a resistance larger than the resistance of the first resistor are connected in parallel. It is desirable that the resistance of the second resistor be 100 to 1000 times the resistance of the first resistor. It is also desirable that the second resistor has an impurity diffusion layer. Preferably, at least one of the first electrode and the second electrode is made of a metal material or made of conductive polysilicon. The second capacitor is in contact with a U-shaped second electrode along the inner wall of the deep trench, a dielectric layer laminated on the entire inner surface of the first electrode, and a surface without the dielectric layer. It is desirable to include a first electrode formed by the above method.

A third feature of the present invention is that a variable voltage source, a first electrode connected to the variable voltage source, a dielectric layer broken down adjacent to the first electrode, a dielectric layer broken down And a control circuit connected to the overcurrent suppression circuit and a control unit connected to the overcurrent suppression circuit as a unit. The gist is that there is. When specific information is actually stored in the fourth aspect of the present invention, the storage of the information is retained by the circuit configuration according to the third aspect of the present invention, and the information can be reproduced by passing a current. .

A fourth feature of the present invention is that a variable voltage source
A capacitor comprising a first electrode connected to the variable voltage source, a dielectric layer adjacent to the first electrode, a second electrode adjacent to the dielectric layer, a first resistor connected to the second electrode, A method of storing information by using a circuit including an overcurrent suppression circuit including a parallel circuit of a second resistor having a resistance value larger than the resistance value of the first resistor and a control unit connected to the overcurrent suppression circuit. In the step of applying a voltage of a magnitude capable of dielectric breakdown to the dielectric layer by a variable voltage source,
The dielectric layer is broken down by a voltage and the first electrode and the second
The main object of the present invention is to provide a method of storing information including a step of conducting between the electrodes and a step of disconnecting only the first resistor in the parallel circuit due to an overcurrent flowing through the first resistor.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the width of the layers, the ratio of the thickness of each layer, and the like are different from actual ones. In addition, it goes without saying that the drawings include portions having different dimensional relationships and ratios.

(First Embodiment) As shown in FIGS. 1 and 3, a semiconductor memory device according to a first embodiment has a variable voltage source 1, a capacitor 2 connected to the variable voltage source 1, and a capacitor 2. An overcurrent suppression circuit 5 composed of a parallel circuit of a first resistor 3 and a second resistor 4 connected to the control circuit 8 and a control unit 8 connected to the overcurrent suppression circuit 5.

The semiconductor memory device according to the first embodiment is manufactured on a semiconductor substrate 10 as shown in FIG. An impurity diffusion layer 12 and an element isolation region 1 provided so as to surround the impurity diffusion layer 12 are formed above the semiconductor substrate 10.
1 is arranged. A first insulating interlayer 13 is laminated on the semiconductor substrate 10, and two first insulating interlayers 13 are formed on the impurity diffusion layer 12 so as to penetrate the first insulating interlayer 13 vertically.
Of the conductive layer 14 is formed. The first conductive layer 14 is used as a contact plug, and an interface between the impurity diffusion layer 12 and the first conductive layer 14 forms an ohmic junction.
The first insulating interlayer film 13 is a silicon oxide film (SiO2
), A silicon nitride film (Si ₃ N ₄ film), or the like, and the first conductive layer 14 is made of aluminum (Al), copper (Cu), tungsten (W), or the like. It is also possible to use polysilicon or the like having conductivity for the first conductive layer 14.

On the first insulating interlayer 13, a second insulating interlayer 15 is laminated. Inside the second insulating interlayer 15 and on the first conductive layer 14, the second insulating interlayer 1
The second conductive layer 16 is formed so as to penetrate the wire 5 vertically. The second conductive layer 16 is used as a wiring layer for electrically connecting to another circuit (not shown) manufactured on the same substrate. The second insulating interlayer film 15 is made of S
io2, _Si 3 made of an insulating material such as _{N 4,} the second conductive layer 16 of Al, made of a metal such as Cu.

On the second insulating interlayer film 15, a third insulating interlayer film 17 is laminated. Inside the third insulating interlayer 17 and on the second conductive layer 16, the third insulating interlayer 1
A third conductive layer 18 is formed so as to penetrate through 7 vertically. The third conductive layer 18 has a role of a contact plug electrically connected to the second conductive layer 16 and includes Al, C
In addition to the u and W metals, it is possible to use conductive polysilicon or the like. The third insulating interlayer film 17 is made of S
io2, an insulating material such as _Si 3 _{N 4.}

The first electrode 21, the capacitor connection conductive layer 20, and the external connection conductive layer 19 are formed on the third insulating interlayer film 17.
Are arranged respectively. The first electrode 21, the capacitor connection conductive layer 20, and the external connection conductive layer 19 are electrically insulated from each other by having an insulating layer between them. The capacitor connection conductive layer 20 and the external connection conductive layer 19 are provided on the two third conductive layers 18, respectively. or,
The first electrode 21 is electrically connected to the variable voltage source 1, and the external connection conductive layer 19 is electrically connected to the control unit 8.

A barrier metal region 23 is formed on the first electrode 21, the capacitor connection conductive layer 20, and the external connection conductive layer 19. The barrier metal region 23 is electrically connected to the capacitor connection conductive layer 20 and the external connection conductive layer 19 by being in contact therewith. On the other hand, a dielectric layer 22 is provided between the barrier metal region 23 and the first electrode 21.
Are sandwiched between the first electrode 21 and the barrier metal region 2.
3 is electrically insulated. The barrier metal region 23 is formed of TiN, TiW, a refractory metal silicide, or the like. Above the barrier metal region 23, a metal region 24
Are laminated. For the metal region 24, a metal such as Al or Cu is used. A second electrode 37 is composed of the barrier metal region 23 and the metal region 24 stacked on the barrier metal region 23.

The capacitor 2 is connected to the first electrode 21
And a dielectric layer 22 laminated on the first electrode 21 and a second electrode 37 disposed on the dielectric layer 22. The barrier metal region 23 is for preventing a metal atom in the metal region 24 from diffusing into the dielectric layer 22 to leak current. The dielectric layer 22 is made of SiO.
2, formed of Si ₃ N ₄ or the like. To protect the semiconductor memory device according to the first embodiment, an insulating film 25 and a passivation 26 are stacked on the upper surface of the device.

The first resistor 3 is formed by a portion where the barrier metal region 23 contacts the external connection conductive layer 19. The second resistor 4 is formed by the impurity diffusion layer 12, the first conductive layer 14, the second conductive layer 16, and the third conductive layer 18. In particular, since the conductivity of the impurity diffusion layer 12 can be changed by changing the impurity density, the resistance value R2 of the second resistor 4 can be set to a desired value. Usually, the ratio of the resistance value R2 of the second resistor 4 to the resistance value R1 of the first resistor 3 is 1000: 1 to 10: 1.
It is set to be about 0: 1. First resistor 3
The overcurrent suppression circuit 5 shown in FIG.

It should be noted that the variable voltage source 1 may be provided on the semiconductor substrate 10 or externally provided that it can apply a voltage sufficient to break the insulation of the capacitor 2. There is no. The control unit 8 may be any unit that does not include the first transistor 6 and the second transistor 7 as long as it can change the path of current flow when storing and reproducing information.

Next, the operation of the semiconductor memory device according to the first embodiment will be specifically described with reference to FIGS. 1 to 3 while separately storing information and reproducing information.

(Storage of Information) Information is stored by applying a high voltage to the capacitor 2 by the variable voltage source 1 to destroy the capacitor. The capacitor 2 sandwiches the dielectric layer 22 between the first electrode 21 and the second electrode 37, and does not flow current at a normal voltage. However, when a voltage higher than the withstand voltage of the dielectric layer 22 is applied to the capacitor 2, dielectric breakdown occurs, the first electrode 21 and the second electrode 37 conduct, a current flows, and the storage state of the information “1” become. Specifically, it is as follows.

First, the gate voltage of the second transistor 7 of the control unit 8 shown in FIG. 1 is controlled in advance to make it conductive. On the other hand, the gate voltage of the first transistor 6 is controlled to set the first transistor 6 in a cutoff state. Therefore, the current flowing into the control unit 8 through the external connection conductive layer 19 flows through the second transistor 7 to the ground.

After the second transistor 7 is turned on, a high voltage is applied to the capacitor 2 by the variable voltage source 1. When SiO 2 is used as the material of the dielectric layer 22 and the thickness of the dielectric layer 22 is 5 to 7 nm, the dielectric breakdown voltage is about 8 to 10 V. Capacitor 2 by voltage source 1
A voltage of 8 to 10 V or more may be applied to this. Since the second transistor 7 is conductive, the second electrode 37 of the capacitor 2 is connected to the ground, and the potential of the variable voltage source 1 is applied to the dielectric layer 22 of the capacitor 2 as it is. Becomes When a high voltage is applied from the variable voltage source 1, the dielectric layer 22 of the capacitor 2 is broken, and the first electrode 21 and the second electrode 37 are electrically connected. Thereafter, the capacitor 2 is replaced by a resistor 29 shown in FIG. Function. The material of the dielectric layer 22 is SiO2, and the thickness is 5 to 5.
When the thickness is 7 nm, the size of the resistor 29 after the destruction of the capacitor is about 500Ω. Therefore, FIG.
As shown in (a), a current flows, and the current further flows into the overcurrent suppression circuit 5. As described above, since the resistance value R2 of the second resistor 4 of the overcurrent suppression circuit 5 is much larger than the resistance value R1 of the first resistor 3, most of the current flowing through the capacitor 2 is almost equal to the resistance value R1. 1 flows into the resistor 3.

Since the resistance between the source and the drain of the second transistor 7 is very small and the resistance value R1 of the first resistor 3 is small, the resistance of the whole circuit is equal to the resistance value of the resistor 29 composed of the capacitor 2 after breakdown. Is determined by Therefore, the resistance value of this circuit is about 500Ω. Since the voltage of the variable voltage source 1 when storing the information "1" is 8 to 10 V, the current I1 flowing through the circuit is 16 to 20 mA. Since such a large current flows, heat is generated in the first resistor 3, and the contact portion between the barrier metal region 23 and the external connection conductive layer 19 shown in FIG. That is, as shown in FIGS. 2B and 2C, the first resistor 3 is disconnected, and the current flows through the second resistor 4 having a large resistance value. Therefore 16-20m
The current of A does not flow into the control unit 8 or the like, and the information “
At the time of storing 1 ", the circuit portion other than the first resistor 3 is not destroyed by the current due to the large current.

That is, after the first resistor 3 is disconnected, as shown in FIG. 2B, a circuit comprising the variable voltage source 1, the resistor 29, the second resistor 4, and the second transistor 7 is provided. Holds. The value of the resistance value R2 of the second resistor 4 is set to, for example, 7.5.
If the impurity density and the geometric shape of the impurity diffusion layer 12 are set so as to be kΩ, the resistance value of the entire circuit becomes 8 kΩ, including the resistance value of the resistor 29 after dielectric breakdown of the capacitor 2 of 500Ω. Accordingly, the current I2 flowing through the entire circuit shown in FIG. 2B after the first resistor 3 is disconnected has a value of about 1 mA. In a normal semiconductor device, the magnitude of the current at which the wiring and the contact are destroyed is about 10 mA. Therefore, after the first resistor 3 is disconnected, the semiconductor memory device according to the first embodiment is damaged at all. The current flows without fail through the resistor 29, the second resistor 4, and the second transistor 7 to the ground.

Therefore, even when a high voltage is applied by the variable voltage source 1 when information "1" is stored, wirings and contacts other than the first resistor 3 are not broken.
Even if the first resistor 3 is destroyed, the second resistor 4 connected in parallel with the first resistor 3 exists, so that the first electrode in the semiconductor memory device according to the first embodiment is provided. Electrical continuity between 21 and external connection conductive layer 19 is ensured. Furthermore, since a large current of about 16 to 20 mA flows when the capacitor 2 is destroyed, there is no fear that the capacitor 2 will not be sufficiently destroyed. Furthermore, since a large current does not flow through the circuit in the semiconductor memory device according to the first embodiment except when the capacitor 2 is destroyed, power loss can be suppressed.

(Reproduction of Information) Reproduction of information is performed first by referring to FIG.
In the circuit configuration shown in FIG.
Set to a low pressure of about 2V. Next, the control unit 8 controls the gate voltage of the first transistor 6 to make the first transistor 6 conductive. At the same time, the second transistor 7 is turned off by controlling the gate voltage of the second transistor 7, and the current flowing into the control unit 8 flows through the first transistor 6 to the outside. Therefore, the current is
As shown in (c), the voltage is output from the variable voltage source 1 to the outside through the resistor 29, the second resistor 4, and the first transistor 6.

When the information “1” is stored, the capacitor 2 is destroyed and functions as the resistor 29 as described above.
Therefore, the variable voltage source 1 supplies the resistor 29, the second resistor 4, the first
Through the transistor 6, a current is output to an external device (not shown). On the other hand, when the information “0” is stored, the capacitor 2 does not pass the current. Variable voltage source 1
Is significantly smaller than the voltage at the time of storage of the information "1", so that the capacitor 2 is not newly broken and becomes conductive. Therefore, information "1" or "1" depends on whether a current is output through the first transistor 6.
The storage state of "0" can be determined.

Next, a method of manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. The variable voltage source 1 and the control unit 8 can be manufactured by using a well-known method, and a description thereof will be omitted.

(A) First, the semiconductor substrate 10 is prepared, a resist film is applied on the surface of the semiconductor substrate 10, and a resist pattern 31 having an opening in a region where the element isolation region 11 is to be formed is formed by photolithography. Using this resist pattern 31 as a mask, anisotropic etching such as reactive ion etching (RIE) is performed, and FIG.
A trench (trench) as shown in FIG. After removing the resist pattern 31, a thick SiO 2
Deposit _two films. Next, by performing a planarization process such as chemical mechanical polishing (CMP), the SiO ₂ film deposited on the surface of the semiconductor substrate 10 is removed, and SiO _{2 is formed} in the groove.
Embed the membrane.

(B) Next, a resist film is applied on the surface of the semiconductor substrate 10, and the resist film is formed by photolithography as shown in FIG.
As shown in FIG. 3B, a resist pattern 32 having an opening in a region where the impurity diffusion layer 12 is formed is formed. Using the resist pattern 32 as a mask, the semiconductor substrate 10 is
A p-type impurity ion such as ¹¹ B ^{+ is} implanted with a dose required for a desired resistance value (for example, 3 × 10 ¹¹ cm ⁻² to 8 × 10
^{(About 14} cm ⁻² ) into the semiconductor substrate 10. Thereafter, the resist pattern 32 is removed, and a diffusion temperature and a diffusion time are set so as to form a diffusion layer necessary for obtaining a desired resistance value. For example, when heat treatment is performed at 1150 ° C. for about 5 hours, the impurity diffusion layer 12 becomes It is formed.

(C) Next, as shown in FIG.
An SiO2 film (first insulating interlayer film) 13 is deposited by a method. Next, a resist film is applied on the first insulating interlayer film 13, and a resist pattern 33 having an opening in a region where the first conductive layer 14 is to be formed is formed by photolithography. Next, RIE is performed using the resist pattern 33 as a mask.
Etching by a method or the like is performed to form an opening as shown in FIG.

(D) Next, a high-melting-point metal such as W or molybdenum (Mo) is deposited by sputtering or vapor deposition. Then, by a flattening process such as CMP, FIG.
The first conductive layer 14 is buried in the opening as shown in FIG. Note that polysilicon (doped polysilicon) containing a p-type impurity is deposited on the entire surface of the first insulating interlayer film 13 including the groove by the CVD method, and then planarized by CMP, so that the polysilicon is formed in the groove. Embed the first
The conductive layer 14 may be used.

(E) In the same manner as in (d), as shown in FIG. 5A, the second insulating interlayer film 15 and the second conductive layer 1 are formed.
6, the third insulating interlayer 17 and the third conductive layer 18, the first
, The capacitor connection conductive layer 20, and the external connection conductive layer 19 are formed.

(F) Next, as shown in FIG. 5B, a SiO 2 film or the like is deposited on the upper surface by a CVD method to form a dielectric layer 22. Thereafter, a resist pattern 34 having an opening in a partial region on the capacitor connection conductive layer 20 and the external connection conductive layer 19 as shown in FIG. 5C is formed on the dielectric layer 22 by photolithography. afterwards,
Using the resist pattern 34 as a mask, the dielectric layer 20 is selectively etched by RIE or the like to expose partial surfaces of the capacitor connection conductive layer 20 and the external connection conductive layer 19. After that, the resist pattern 34 is removed.

(G) Next, a resist pattern 35 having an opening in a region where the barrier metal region 23 is to be formed is formed on the surface of the dielectric layer 22 by photolithography. Using this resist pattern 35 as a lift-off mask, a TiN film is deposited on the entire surface by a sputtering method or the like performed in an atmosphere containing nitrogen as shown in FIG. After that, if the resist pattern 35 and the TiN film deposited on the resist pattern 35 are removed, the barrier metal region 23 is patterned.

(H) Next, a resist film 36 is applied on the surfaces of the dielectric layer 22 and the barrier metal region 23. Next, a resist pattern 36 having an opening on the barrier metal region 23 is formed by a photolithography method, and the resist pattern 36 is used as a lift-off mask as shown in FIG.
Deposit metals such as i, Mo, W, and cobalt (Co).
After that, the resist pattern 36 and the resist pattern 3
By removing the metal adhering to 6, the metal region 24 is removed.
Is patterned. In the steps (g) and (h), since the resist patterns 35 and 36 have the same pattern, a metal material for forming the metal region 24 is deposited continuously after the metal deposition for forming the barrier metal region 23. Then, the resist pattern 35 is lifted off.
It is also useful to remove the metal deposited on the resist pattern 35. Finally, as shown in FIG. 6B, an insulating film 25 and a passivation 26 are formed on the metal region 24.
Is deposited to complete the semiconductor memory device according to the first embodiment.

As described above, according to the first embodiment of the present invention, even if a large current flows when the capacitor 2 is destroyed for storing the information "1", the wires other than the first resistor 3 are disconnected. Therefore, even when information "1" is stored, the entire circuit is not disconnected. Therefore, even when the capacitor 2 is destroyed in reproducing the information "1", no current is output.

According to the first embodiment of the present invention,
Since there is no fear of disconnection of a circuit in the semiconductor memory device when storing the information “1”, a large current can flow through the capacitor 2 when storing the information “1”. Therefore, the disadvantage that the capacitor 2 is not sufficiently destroyed due to the low current flowing through the circuit does not occur.

According to the first embodiment of the present invention,
Since the magnitude of the current flowing through the circuit in the semiconductor memory device can be controlled by the second resistor 4, the first resistor constituting the capacitor 2 can be controlled.
It is possible to use, for the electrode 21 and the second electrode 37, a metal having a low resistance value of the resistor 29 formed of the capacitor 2 after the dielectric breakdown.

Further, according to the first embodiment of the present invention,
The high current flowing when the capacitor 2 is broken is not discharged to the outside of the circuit but is cut off, so that the power loss can be suppressed low.

(Second Embodiment) A semiconductor memory device according to a second embodiment has a variable voltage source 1 as shown in FIG.
Capacitor 60 having trench structure connected to
A parallel circuit including a first resistor (second conductive layer) 3 and a second resistor 4 connected to the stack capacitor 60; a first resistor (second conductive layer) 3 and a second resistor 4 and a control unit 8 connected thereto. As shown in FIG. 7, the semiconductor memory device according to the second embodiment is manufactured on a semiconductor substrate 41. An impurity diffusion layer is provided on a partial region above the semiconductor substrate 41, and an element isolation region is provided on a partial region where the impurity diffusion layer does not exist.
Is provided. An insulating layer 47a on the semiconductor substrate 41;
Are stacked inside the insulating layer 47a and over the region where the impurity diffusion layer 46 is present.
4 is formed so as to penetrate the insulating layer 47a vertically. Note that the second layer is formed by the impurity diffusion layer 46 and the first conductive layer 44.
Is formed. Therefore, by adjusting the impurity density in the impurity diffusion layer 46, the resistance value of the second resistor 4 can be set to a desired value. Note that the interface between the first conductive layer 44 and the impurity diffusion layer 46 forms an ohmic junction. The first conductive layer 44 has a function as a contact plug and is made of a high melting point metal such as Mo, Co, or W, but may be formed of doped polysilicon having the same conductivity as the impurity diffusion layer 46.

A first resistor (second conductive layer) 3 is formed on the upper surface of the insulating layer 47a and on a part of the region including the first conductive layer 44. First resistor (second conductive layer)
3 is electrically connected to the two first conductive layers 44, respectively. The first resistor (second conductive layer) 3 is desirably made of a high melting point metal such as W, Mo, or Co having a lower resistance than the impurity diffusion layer 46. A stack capacitor 60 having a trench structure and a doped polysilicon region 56 are formed on the upper surface of the first resistor (second conductive layer) 3. The stacked capacitor 60 has a U-shaped second electrode 53 along the inner wall of the deep trench having a large aspect ratio.
And a dielectric layer 54 laminated on the entire inner surface of the second electrode 53 and a columnar first electrode 55 provided in contact with the inner surface of the dielectric layer 54. The second electrode 53 is connected to the first resistor (second conductive layer) 3,
The electrode 55 is insulated by the dielectric layer 54.
Also, the doped polysilicon region 56 has a first resistance (second
Is formed on a partial region of the conductive layer 3), and is formed of columnar polysilicon doped with impurities at a high concentration. The first electrode 55 and the second electrode 53 are made of metal, but may be made of doped polysilicon.
The dielectric layer 54 is formed of an insulating material such as SiO2 or _Si 3 _{N 4.} An interface between the doped polysilicon region 56 and the first resistor (second conductive layer) 3 forms an ohmic junction.

The first electrode 55 is connected to the anode electrode 57 provided on the upper part, and the anode electrode 57 is connected to the variable voltage source 1. Further, a cathode electrode 58 is laminated on the upper surface of the doped polysilicon region 56,
The cathode electrode 58 is connected to the control unit 8. The anode electrode 57 and the cathode electrode 58 are made of a metal such as Al or Cu, but may be made of conductive polysilicon.

The variable voltage source 1 may be provided on the semiconductor substrate 41 or provided externally, as long as it can apply a voltage sufficient to break the insulation of the stack capacitor 60 at the maximum. If there is no problem. Control unit 8
May be any as long as it has a first transistor 6 and a second transistor 7 and can change the path through which current flows when information is stored and reproduced.

For comparison, the structure of the semiconductor memory device according to the second embodiment is shown in the left part of FIG. 7 in which a memory cell of a DRAM using a conventionally known stack capacitor provided on the same semiconductor substrate 41 is shown. The structure of is shown. As can be seen from FIG. 7, both structures have many common parts. For this reason, when manufacturing as a part of a DRAM on the same substrate as a semiconductor memory device for recording information for replacing a defective memory cell with a redundant memory cell, a new special manufacturing process is not required. Further, since the manufacturing process can be performed in the same manner as the manufacturing of the stacked capacitor memory, there is an advantage that the manufacturing cost can be reduced.

Next, the operation of the semiconductor memory device according to the second embodiment will be described with reference to FIGS. 1, 2 and 7 separately for storing and reproducing information.

(Storage of Information) Information "1" is stored by applying a high voltage from the variable voltage source 1 to the dielectric layer 54 of the stack capacitor 60 to cause dielectric breakdown. Since the dielectric layer 54 of the stack capacitor 60 is broken down and the resistance of the first resistor 3 is much smaller than that of the second resistor 4, as in the case of the first embodiment, FIG. The current flows as shown in (). Only the resistor 29 and the first resistor 3 are present in the equivalent circuit shown in FIG.
Since the resistance of the resistor 3 is very small, the resistance of the entire circuit can be kept low. Therefore, a large current flows through the first resistor 3, and the first resistor 3 is melted by Joule heat and disconnected.
On the other hand, although the first resistor 3 is disconnected, the presence of the second resistor 4 connected in parallel with the first resistor 3 causes a new
The equivalent circuit shown in FIG. Since the resistance value of the second resistor 4 is much larger than that of the first resistor 3, only a small current flows through the circuit. Accordingly, conduction between the anode electrode 57 and the cathode electrode 58 is ensured without breaking the surface wiring and the bonding wire in the semiconductor memory device according to the second embodiment. As described above, the information “1” is stored.

(Reproduction of Information) Information is reproduced by applying a low voltage from the variable voltage source 1 and detecting whether or not a current is output from the control unit 8 by an external device (not shown). That is, it is basically the same as the reproduction of information in the first embodiment. When the information “1” is stored, the equivalent circuit becomes as shown in FIG.
The resistance 4 causes conduction between the anode electrode 57 and the cathode electrode 58, so that current flows to the control unit 8. On the other hand, when the information "0" is stored, no current flows due to the presence of the dielectric layer 54 constituting the stack capacitor 60. Therefore, information “1” or “0” can be determined based on whether or not the current is output from the control unit 8 to the outside.

(Method of Manufacturing Semiconductor Device) Next, a method of manufacturing a semiconductor memory device according to the second embodiment will be described with reference to FIG.
This will be described with reference to FIGS. Note that the variable voltage source 1 and the control unit 8 can be manufactured by a known method, and thus description thereof is omitted here.

(A) First, an element isolation region 42 and an impurity diffusion layer 46 are formed on a semiconductor substrate 41 as shown in FIG.
Is provided. Further, an insulating layer 47a is deposited by a CVD method or the like,
The first conductive layer 44 is formed in a partial region of the insulating layer 47a. Since these steps can be performed in the same manner as the steps (A) to (D) of the method for manufacturing the semiconductor memory device according to the first embodiment, illustration and detailed description of the steps are omitted.

(B) Next, an interlayer insulating film 48 is deposited on the semiconductor substrate 41, and an insulating layer 47 is further formed on the interlayer insulating film 48.
grow b. Then, a resist film is applied on the surface of the insulating layer 47b to form a resist pattern 61 having an opening in a region where the second conductive layer (first resistor) 3 is to be formed. Using this resist pattern 61 as an etching mask, a groove as shown in FIG. 8B is formed by RIE or the like.

(C) Next, refractory metals such as W, Mo, Co, and Ti are deposited by vapor deposition or sputtering. After depositing the refractory metal, the refractory metal deposited on the insulating layer 47b is removed by a planarization process such as CMP while leaving the refractory metal deposited in the groove, thereby forming a first resistor (second conductive layer). Form 3

(D) Next, in order to secure a region for forming the stack capacitor 60 and the impurity diffusion layer 46, FIG.
As shown in (d), the insulating layer 47b and the first resistor (second
An insulating layer 47c is stacked on the conductive layer 3). Next, a resist pattern 62 having an opening in a region where the stack capacitor 60 is to be formed is formed on the surface of the insulating layer 47c by photolithography. This resist pattern 62
Is etched by the RIE method or the like using as an etching mask to form a deep groove (trench) reaching the first resistor (second conductive layer) 3 as shown in FIG.
A part of the surface of the first resistor (second conductive layer) 3 is exposed.

(E) Next, the resist pattern 62 is not removed and is used as a lift-off mask, and a high melting point metal such as W is deposited on the groove and the resist pattern 62 formed in the step (d) by vapor deposition or sputtering. To be deposited. Thereafter, by removing the resist pattern 62 and the metal deposited thereon, the second electrode 53 is patterned inside the groove as shown in FIG. 9B.

(F) Next, an SiO 2 film is deposited on the insulating layer 47c and the second electrode 53 inside the groove by the CVD method. As a result, as shown in FIG. 9C, the dielectric layer 54 is formed on the second electrode 53 and the dielectric layer 63 is formed on the insulating layer 47c.
Is formed. Thereafter, the dielectric layer 63 is removed in a planarization process such as CMP, and only the dielectric layer 54 inside the groove remains as shown in FIG. 9D.

(G) Next, a high melting point metal such as W is deposited on the insulating layer 47c by vapor deposition or sputtering.
At this time, the metal is also buried in the groove where the dielectric layer 54 is formed. After that, the metal deposited on the surface of the insulating layer 47c is removed by a planarization process such as CMP. As a result, as shown in FIG. 10A, the first electrode 55 is buried in the groove, and a stacked capacitor having a trench structure is completed. Further, the insulating layer 4 is formed on the flattened insulating layer 47c.
7d is laminated.

(H) Next, a resist pattern 64 having an opening in a partial region of the surface of the insulating layer 47d is formed on the surface of the insulating layer 47d by photolithography.
Then, etching is performed by RIE or the like using the resist pattern 64 as an etching mask to form a groove as shown in FIG. 10B.

(I) Next, the resist pattern 64 is removed, and a new resist film is applied to the surface of the insulating layer 47d. Then, the first electrode 5 is formed using photolithography.
A resist pattern 65 having an opening is formed on the resist pattern 5. Using the resist pattern 65 as an etching mask, R
Etching is performed by the IE method or the like to expose the surface of the first electrode 55 as shown in FIG.

Next, the resist pattern 65 is left as a lift-off mask without being removed.
As shown in (d), a metal such as W is deposited by vapor deposition or sputtering. Thereafter, the resist pattern 65 and the metal deposited on the resist pattern 65 are removed. As a result, the metal selectively remains on the first electrode 55.

Next, a resist pattern 66 which is the same pattern as the resist pattern 64 used in FIG. 10B is formed by photolithography.
By using the same method as in the above step, a metal region connecting the first electrode 55 and the anode electrode 57 is completed as shown in FIG.

(ヲ) Next, a resist pattern 67 having an opening in a region where the impurity diffusion layer 46 is to be formed is formed on the surface of the insulating layer 47d by photolithography.
Using this resist pattern 67 as an etching mask, R
Etching such as the IE method is performed to form a groove as shown in FIG. 11B, and a part of the surface of the first resistor (second conductive layer) 3 is exposed. After removing the resist pattern 67,
A doped polysilicon is deposited by a CVD method using diborane (B2H6) or the like as a dopant. Next, the doped polysilicon deposited on the impurity layer 47d is removed by a planarization process such as CMP, and the doped polysilicon is buried in the trench to form a doped polysilicon region 56. After that, after depositing the insulating layer 47e by the CVD method or the like, a groove is formed by etching the insulating layer 47e, and metal is deposited on the entire insulating layer 47e. Then C
The metal is buried in the groove by removing the metal deposited in other than the groove by a planarization process such as MP. An anode electrode 57 and a cathode electrode 58 are formed by the buried metal, and as shown in FIG.
The semiconductor memory device according to the embodiment is completed.

(Other Embodiments) As described above, the present invention has been described with reference to the first and second embodiments. However, the description and drawings constituting a part of this disclosure limit the present invention. Should not be understood to be. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, when the first electrode 21 is made of metal in the first embodiment, it is also effective to cover the upper and lower surfaces of the first electrode 21 with barrier metal regions. This is because metal atoms in the first electrode can be more effectively prevented from diffusing into the dielectric layer 22. Also, instead of providing the first electrode 21 and the second electrode 37 with the barrier metal region, it is effective to add Si atoms in the electrodes in a solid solution amount or more. This is because leakage current can be suppressed by preventing interdiffusion between Si and the metal. Further, the first electrode 21 and the second electrode 37 are made of a material other than metal.
For example, it is also effective to form the conductive layer by using doped polysilicon. Only one of the first electrode 21 and the second electrode 37 may be formed of doped polysilicon or the like.

The numerical values shown in the first and second embodiments do not limit the present invention. For example, the present invention can be sufficiently implemented even if the thickness of the dielectric layers 22 and 54 in the capacitor is other than 5 to 7 nm.
The resistance value of 40 is not limited to 7.5 kΩ. When the capacitor is destroyed, a current sufficient to destroy the capacitor flows through the semiconductor memory device according to the present invention, and after the breakdown, 1
If a current sufficiently lower than 0 mA flows, a variable voltage source, a capacitor, a first resistor, and a second resistor having various electrical characteristics can be used.

In the first embodiment, it is effective to increase the number of insulating interlayers and conductive layers for electrical connection with another circuit manufactured on the same substrate. It is also effective to simplify the manufacturing process by reducing the number of insulating interlayer films.

Further, in the first and second embodiments, the impurity to be contained in the impurity diffusion layer or the doped polysilicon is constituted by a p-type impurity such as B. ), N of arsenic (As), etc.
It goes without saying that the effects of the present invention can be realized even when the type impurities are contained.

Further, the method of manufacturing the semiconductor memory device according to the first and second embodiments need not always be performed as described. For example, in the second embodiment, the doped polysilicon region 56 is
It may be formed earlier than zero. Then, a metal having a relatively low melting point, such as Al, can be used as the first electrode 55 of the stacked capacitor 60.

Further, the impurity diffusion layer 12 according to the first embodiment and the impurity diffusion layer 46 according to the second embodiment other than a semiconductor layer such as polysilicon as long as the resistance value of the second resistor can be increased. May be used.

As described above, it should be understood that the present invention includes various embodiments and the like not described herein. Accordingly, the present invention is limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0090]

As described above, according to the present invention,
A semiconductor memory device capable of outputting a sufficiently large current at the time of reproducing information can be provided.

Further, according to the present invention, it is possible to provide a semiconductor memory device in which circuit wiring and bonding are not destroyed by a current flowing when information is stored.

Further, according to the present invention, it is possible to provide a semiconductor memory device capable of suppressing a large current from flowing in a circuit and suppressing a power loss.

Further, according to the present invention, it is possible to provide a semiconductor memory device which can be manufactured in the same process as that of a memory cell when the memory cell is manufactured on the same substrate as a memory cell of a DRAM.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a semiconductor memory device according to first and second embodiments.

FIG. 2 is an equivalent circuit diagram showing an operation of the semiconductor memory device according to the first and second embodiments.

FIG. 3 is a sectional view showing the structure of the semiconductor memory device according to the first embodiment;

FIG. 4 is a diagram showing main steps of a method for manufacturing the semiconductor memory device according to the first embodiment.

FIG. 5 is a view showing main steps of a method for manufacturing the semiconductor memory device according to the first embodiment.

FIG. 6 is a diagram showing main steps of a method for manufacturing the semiconductor memory device according to the first embodiment.

FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor memory device according to a second embodiment and a structure of a memory cell using a stack capacitor provided on the same semiconductor substrate.

FIG. 8 is a diagram showing main steps of a method for manufacturing a semiconductor memory device according to a second embodiment.

FIG. 9 is a diagram showing main steps of a method for manufacturing a semiconductor memory device according to a second embodiment.

FIG. 10 is a diagram showing main steps of a method for manufacturing a semiconductor memory device according to a second embodiment.

FIG. 11 is a diagram showing main steps of a method for manufacturing a semiconductor memory device according to a second embodiment.

FIG. 12 is an equivalent circuit diagram of a conventional semiconductor memory device.

FIG. 13 is a sectional view showing the structure of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 101 Variable voltage source 2, 102 Capacitor 3 1st resistance 4 2nd resistance 5 Overcurrent suppression circuit 6, 103 1st transistor 7, 104 2nd transistor 8, 118 Control part 10, 41, 105 Semiconductor Substrate 11, 42, 106 Element isolation region 12, 39, 46 Impurity diffusion layer 13 First insulating interlayer 14 First conductive layer 15 Second insulating interlayer 16 Second conductive layer 17 Third insulating interlayer 18 Third conductive layer 19, 114 External connection conductive layer 20 Capacitor connection conductive layer 21, 55, 117 First electrode 22, 51, 54, 63, 113 Dielectric layer 23, 112 Barrier metal region 24, 111 Metal region 25, 115 Insulating film 26, 116 Passivation 29 Resistance 31-36 Resist pattern 37, 53 Second electrode 43 Memory transformer Gate 44 first conductive layer 45 bit line 47a, 47b, 47c, 47d, 47e insulating layer 48 interlayer insulating film 49 second conductive layer 50, 52 electrode 56 doped polysilicon region 57 anode electrode 58 cathode electrode 59, 60 Stack capacitor 61, 62 Resist pattern 64-67 Resist pattern 107-109 Insulating interlayer film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 AD24 AD48 CR12 CR14 GA05 GA28 GA30 JA02 JA32 JA36 JA39 JA40 MA06 MA17 MA20 PR03 PR22 PR40 ZA14

Claims (20)

[Claims] A capacitor comprising a variable voltage source, a first electrode connected to the variable voltage source, a dielectric layer adjacent to the first electrode, and a second electrode adjacent to the dielectric layer; A semiconductor memory device comprising: an overcurrent suppression circuit connected to the second electrode; and a control unit connected to the overcurrent suppression circuit. 2. The overcurrent suppression circuit according to claim 1, wherein the overcurrent suppression circuit comprises a circuit in which a first resistor and a second resistor having a resistance value larger than the resistance value of the first resistor are connected in parallel. Item 2. The semiconductor memory device according to item 1. 3. The semiconductor device according to claim 2, wherein said second resistor includes an impurity diffusion layer formed in a semiconductor substrate.
13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 2, wherein said first resistor is made of a metal material. 5. The semiconductor memory according to claim 2, wherein a resistance value of said second resistor is 100 to 1000 times a resistance value of said second resistor. apparatus. 6. The method according to claim 1, wherein at least one of said first and second electrodes is made of a metal material.
7. The semiconductor memory device according to claim 1. 7. The semiconductor memory device according to claim 1, wherein at least one of said first and second electrodes is made of conductive polysilicon. 8. At least one of the first electrode and the second electrode includes a barrier metal region adjacent to the dielectric layer and a metal material different from the barrier metal region adjacent to the barrier metal region. 7. The semiconductor memory device according to claim 6, comprising: 9. The U-shaped second electrode along an inner wall of a deep trench, the dielectric layer laminated on the entire inner surface of the second electrode, and the dielectric layer. 8. The semiconductor memory device according to claim 1, further comprising: the first electrode formed in contact with an inner surface of the semiconductor memory device. 10. A plurality of DRAM memory cells and a redundant memory cell each having a first capacitor provided on a partial region of a semiconductor substrate, and a variable voltage source provided on another region of the semiconductor substrate. A second capacitor comprising a first electrode connected to the variable voltage source, a dielectric layer adjacent to the first electrode, a second electrode adjacent to the dielectric layer, and the second capacitor And a control unit connected to the overcurrent suppression circuit. 11. The overcurrent suppression circuit according to claim 11, wherein the overcurrent suppression circuit includes: a first resistor;
A second resistor having a resistance greater than the resistance of the first resistor;
11. The semiconductor memory device according to claim 10, wherein said resistance comprises a circuit connected in parallel. 12. The semiconductor memory device according to claim 11, wherein said second resistor includes an impurity diffusion layer formed in a semiconductor substrate. 13. The semiconductor memory device according to claim 11, wherein said first resistor is made of a metal material. 14. The semiconductor device according to claim 11, wherein the resistance value of said second resistor is 100 to 1000 times the resistance value of said first resistor. . 15. The semiconductor memory device according to claim 10, wherein said second capacitor has the same structure as said first capacitor. 16. The semiconductor memory device according to claim 10, wherein at least one of said first and second electrodes is made of a metal material. 17. The semiconductor memory device according to claim 10, wherein at least one of said first electrode and said second electrode is made of conductive polysilicon. 18. The U-shaped second electrode along an inner wall of a deep trench, the second capacitor, the dielectric layer laminated on the entire inner surface of the second electrode, 18. The semiconductor device according to claim 10, further comprising: the first electrode formed in contact with an inner surface of the dielectric layer.
7. The semiconductor memory device according to claim 1. 19. A variable voltage source, a first electrode connected to the variable voltage source, a dielectric breakdown layer adjacent to the first electrode, and a first electrode adjacent to the dielectric breakdown layer. A semiconductor comprising, in part, a circuit configuration including, as a unit, a resistor including two electrodes, an overcurrent suppression circuit connected to the second electrode, and a control unit connected to the overcurrent suppression circuit. Storage device. 20. A capacitor comprising a variable voltage source, a first electrode connected to the variable voltage source, a dielectric layer adjacent to the first electrode, and a second electrode adjacent to the dielectric layer. An overcurrent suppression circuit connected to the second electrode, the overcurrent suppression circuit including a parallel circuit of a first resistor and a second resistor having a resistance value larger than the resistance value of the first resistor, and connected to the overcurrent suppression circuit; A method of storing information by using a circuit including a control unit, wherein a step of applying a voltage large enough to cause dielectric breakdown of the dielectric layer to the dielectric layer by the variable voltage source; A step of causing a dielectric breakdown of the dielectric layer to conduct between the first electrode and the second electrode; an overcurrent flows through the first resistor, and only the first resistor in the parallel circuit And a step of disconnecting the wire. Storage method.