JP2002353229A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an HBT(Hetero Junction Bipolar Transistor) of which the operational characteristics are improved by reducing the resistance of a base lead-out region, and its manufacturing method. SOLUTION: An opening 7A comprises an n<-> -type silicon layer 8 and an n<+> -type silicon layer 8a arranged so as to bulge out from an opening 6A until reaching the sidewall of a nitride film 7. Moreover, the opening 7A comprises, on the n<-> -type silicon layer 8 and the n<+> -type silicon layer 8a, a p<+> -type poly crystal silicon germanium film 9B led out in the lateral direction on the surface of a nitride film 7, and a poly crystal silicon film 10B on the surface of this silicon germanium film 9B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a hetero bipolar transistor (hereinafter referred to as HBT) used as a high-speed communication device.
r)).

[0002]

2. Description of the Related Art An HBT uses a heterojunction at the PN junction of a conventional bipolar transistor and utilizes the fact that the potential barrier against holes is higher than that of electrons.
The amount of holes injected from the base to the emitter is controlled, and is characterized by a high current amplification factor and excellent high-frequency characteristics.

The HBT is disclosed in, for example, JP-A-6-333933 (prior art 1) and JP-A-11-204439 (prior art 2). The HBT disclosed in Prior Art 1 realizes a heterojunction bipolar transistor using silicon germanium having a bandgap more than silicon in the intrinsic base region, thereby reducing the current amplification factor h _FE of the bipolar transistor without decreasing the intrinsic gain. The density of the region can be increased, and high f _T can be realized.

The HBT disclosed in the prior art 2 is:
As in Prior Art 1, a heterojunction bipolar transistor using silicon germanium is disclosed, and a structure that enables high-speed operation is disclosed.

(Conventional HBT structure) Here, the conventional HBT
The structure of the BT will be described with reference to FIG.
On the surface of a single crystal silicon substrate 1 which is a semiconductor substrate, n ⁺
A type buried layer 2 is provided, and an n ⁻ type collector layer 3 serving as an active region is defined by the element isolation insulating film 4 on the n ⁺ type buried layer 2.

An oxide film 6 having an opening 6A of a predetermined size is provided on n ^- type collector layer 3. An n ^- type silicon layer 8 is provided inside the opening 6A,
An n ⁺ -type silicon layer 8 a is provided in an upper layer region of the n ⁻ -type silicon layer 8.

A silicon germanium film 9A made of a p-type single crystal region is provided on n ⁺ type silicon layer 8a. Further, this silicon germanium film 9A
Is provided with a silicon film 10A made of an intrinsic single crystal region. The region composed of the silicon germanium film 9A constitutes the intrinsic base region.

On the other hand, a silicon germanium film 9B made of a p-type polycrystalline region is provided on oxide film 6 so as to be continuous with silicon germanium film 9A. Further, on the silicon germanium film 9B,
A silicon film 10B made of a polycrystalline region and provided so as to be continuous from the silicon film 10A is provided. In FIG. 26, the silicon germanium film 9A and the silicon germanium film 9B and the silicon film 10B provided on the left side of the silicon film 10A constitute a base extraction region.

On the silicon film 10A, a silicon film 1
A polysilicon electrode 13 connected to an n-type emitter diffusion layer 13a provided at 0A is provided with an isolation film 12 interposed therebetween. The emitter diffusion layer 13a is formed of the silicon film 10
A is provided. In addition, a silicide layer 14 is provided in an upper layer region of the polysilicon electrode 13.

On one silicon film 10B, a silicide layer 15 is provided along the surface from the end of the side wall 18. In FIG. 26, the right end surfaces of the oxide film 6, the silicon germanium film 9B, and the silicon film 10B are covered with a sidewall 19.

On the surface of single-crystal silicon substrate 1 in the right region of FIG. 26, n ⁺ connected to n ⁺ -type buried layer 2 is provided.
A mold collector leading region 5 is provided, and a silicide layer 17 is provided above the collector leading region 5.

A base electrode 21, an emitter electrode 22, and a collector electrode 23 are connected to the silicide layer 14, the silicide layer 15, and the silicide layer 17, respectively, with an interlayer separation film 20 interposed therebetween.

(Manufacturing Process of Conventional HBT) Next, a manufacturing process of the HBT having the above structure will be described with reference to FIGS.
This will be described with reference to FIG. First, referring to FIG. 27, after forming n ⁺ -type buried layer 2 on the surface of single crystal silicon substrate 1, an n ^-- type epitaxial silicon formation layer is formed on n ⁺ -type buried layer 2 by epitaxial growth. Form. Then, by the LOCOS method, forming an isolation insulating film 4, forming the active region n ^- -type collector layer 3, and the n ^-
A mold collector extraction region 5 is defined.

Next, referring to FIG. 28, an oxide film 6 is deposited on the entire upper surface of single crystal silicon substrate 1. Thereafter, an opening 6A having a predetermined size is formed on the n ⁻ -type collector layer 3 by using a photoengraving technique. Next, referring to FIG. 29, n ⁻ -type silicon layer 8 doped with phosphorus is selectively epitaxially grown inside opening 6A of oxide film 6 where the silicon formation layer is exposed. Thereafter, the n ⁺ -type silicon layer 8a is selectively epitaxially grown.

Next, referring to FIG. 30, a silicon germanium film 9 doped with boron is formed on the surface of single crystal silicon substrate 1. At this time, the silicon germanium film 9 is formed under conditions (non-selective formation conditions) to be formed both on the epitaxially grown n ⁺ type silicon layer 8a and on the oxide film 6. As a result, the silicon germanium film 9 is also epitaxially grown on the epitaxially grown n ⁺ -type silicon layer 8a, and a p-type single crystal silicon germanium film 9A (intrinsic base region) is formed. On the oxide film 6, a p-type polycrystalline silicon germanium film 9B is formed.
Is formed.

Next, referring to FIG. 31, an intrinsic silicon film 10 is formed on the surface of silicon germanium film 9. At this time, silicon also epitaxially grows on the single crystal silicon germanium film 9A (intrinsic base region), and the single crystal silicon film 1
OA is formed. On the polycrystalline silicon germanium film 9B, a polycrystalline silicon film 10B is formed.
Is formed.

Next, referring to FIG.
A nitride film is deposited on the surface of the substrate. Thereafter, a dummy pattern 11 having a predetermined size is formed above the n ⁻ -type collector layer 3 by using a photoengraving technique. Thereafter, using the dummy pattern 11 as a mask, boron is implanted into the polycrystalline silicon germanium film 9B.

Next, referring to FIG. 33, the dummy pattern 11 made of a nitride film is receded (narrowed) by etching with phosphoric acid. Thereafter, an oxide film 12 is deposited on the entire surface of the silicon film 10, and the surface of the oxide film 12 is planarized by a CMP method. Next, referring to FIG. 34, dummy pattern 11 is removed by wet etching to expose single crystal silicon film 10A.

Next, referring to FIG.
A and a polysilicon doped with phosphorus are formed on the oxide film 12. Next, RTA (Rapid Thermal An
neal) to diffuse phosphorus from polysilicon to form an emitter diffusion layer 13a. Thereafter, a polysilicon electrode 13 is formed by using a photolithography technique. afterwards,
Using the polysilicon electrode 13 as a mask, the oxide film 12
Is removed by dry etching.

Next, referring to FIG. 36, a mask having a predetermined shape is formed by photolithography, and an oxide film 6 and a polycrystalline silicon germanium film located above n ⁻ type collector lead-out region 5 are formed. 9B and polycrystalline silicon film 10
B is removed. Then, the side surface of the polysilicon electrode 13,
And a sidewall 18 made of an oxide film covering the side surfaces of the oxide film 12, and a side wall made of an oxide film covering the side surfaces of the oxide film 6, the silicon nitride film 7, the polycrystalline silicon germanium film 9B, and the polycrystalline silicon film 10B. A wall 19 is formed.

Thereafter, a heat treatment is applied after depositing Co on the surface by a known silicidation process. Thereby, the silicide layer 14 is formed on the surface of the polysilicon electrode 13.
Then, a silicide layer 15 is formed on the surfaces of the silicon films 10A and 10B whose surfaces are exposed, and a silicide layer 17 is formed on the surface of the n ⁻ -type collector lead-out region 5.
Thereafter, after depositing the interlayer separation film 20, a contact hole communicating with the silicide layer 14, the silicide layer 15, and the silicide layer 17 is opened by using a photoengraving technique, a wiring layer is further formed, and a predetermined patterning step is performed. By using aluminum wiring, the base electrode 2
1, the emitter electrode 22, and the collector electrode 23 are formed, and the SiGe (silicon germanium) -HBT shown in FIG. 26 is completed.

[0022]

The structure and manufacturing method of the above-structured SiGe-HBT have the following problems. FIG. 37 is a partially enlarged cross-sectional view in which a region near the silicon germanium film 9A (intrinsic base region) is enlarged. In the SiGe-HBT, reducing the resistance of the base extraction region is important for speeding up the operation of the HBT. Therefore, the silicide layer 15 is formed on the surface of the silicon film 10B constituting the base extraction region.

In the structure of the HBT formed in the above step, in the step shown in FIG. 32, boron is implanted into the polycrystalline silicon germanium film 9B using the dummy pattern 11 as a mask. Therefore, as shown in FIG. 37, a region 9C in which boron is not implanted is formed in a part of the silicon germanium film 9B, and a parasitic resistance remains in the current path indicated by the arrow P2 in FIG.
Despite the formation of the silicide layer 15, there is a problem that the expected resistance of the base extraction region cannot be reduced. In addition, since the region 9C is formed of polysilicon, a variation in resistance occurs due to the arrangement of the grain boundaries of polysilicon, and a problem that the variation in element characteristics also increases.

In order to avoid the formation of the region 9C into which boron is not implanted, as shown in FIG. 38, the opening 6A of the oxide film 6 and the opening 7A of the silicon nitride film 7 are increased in the lateral direction. Alternatively, a method may be considered in which the silicon germanium film 9A is overhanged in the lateral direction, and boron is implanted also at the interface between the silicon germanium film 9B and the silicon germanium film 9A. However, when this manufacturing process is adopted, there is a possibility that boron diffuses into the central portion of the n ⁻ -type silicon layer 8 as shown by an arrow H in the figure, thereby deteriorating the operating characteristics of the HBT.

Therefore, the present invention has been made to solve the above-mentioned problems, and the operating characteristics of the HBT can be further improved by lowering the resistance of the base extraction region without deteriorating the operating characteristics of the HBT. Shall be
It is an object to provide a semiconductor device and a method for manufacturing the same.

[0026]

In order to achieve the above object, in a semiconductor device according to the present invention, a first conductivity type single crystal silicon layer provided on a surface of a semiconductor substrate; A first insulating layer selectively provided, a first insulating layer having a first opening communicating with the active region, and covering a surface of the single crystal silicon layer; A second insulating layer provided on a surface, having a second opening larger than the first opening so as to include the first opening, filling the first opening, and forming a second insulating layer in the second opening; (2) a first conductivity type single crystal semiconductor layer provided so as to protrude from the first opening until reaching the opening side wall of the insulating layer; and a second conductivity type first crystal layer provided on the surface of the single crystal semiconductor layer. A single crystal semiconductor layer and the second insulating layer A first polycrystalline semiconductor layer of a second conductivity type formed on the surface and provided continuously with the first single crystal semiconductor layer; and a second single crystal semiconductor layer provided on the surface of the first single crystal semiconductor layer. A second polycrystalline semiconductor layer formed on a surface of the first polycrystalline semiconductor layer and provided continuously with the second single crystal semiconductor layer; and a first single crystal provided on the second single crystal semiconductor layer. A first conductivity type impurity diffusion layer connected to the semiconductor layer.

As described above, the first conductive type single crystal semiconductor layer provided so as to protrude from the first opening to reach the opening side wall of the second insulating layer in the second opening is provided. Since the length of the first and second single-crystal semiconductor layers of the second conductivity type formed on the layer can be increased as compared with the related art, the connection region between the first and second single-crystal semiconductor layers can be increased. , It is possible to lower the resistance in this connection region.

Preferably, in the above invention, the active region and the single crystal semiconductor layer constitute a collector region, the first single crystal semiconductor layer constitutes an intrinsic base region, and the impurity diffusion layer constitutes an emitter region. According to this configuration,
Good HBT characteristics can be obtained by lowering the resistance of the base.

Preferably, in the above invention, the active region and the single crystal semiconductor layer form an emitter region, the first single crystal semiconductor layer forms an intrinsic base region, and the impurity diffusion layer forms a collector region. According to the present invention, in the configuration in which the emitter is located down, the contact area between the base region and the emitter region can be smaller than that of the conventional structure.
As compared with the conventional structure, it is possible to obtain a higher current amplification factor (Hfe).

Preferably, in the above invention, the first single crystal semiconductor layer and the first polycrystalline semiconductor layer are silicon germanium.

Next, in order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a step of forming a first conductivity type single crystal silicon layer on a surface of a semiconductor substrate; Selectively forming an active region of the first conductivity type in the layer, forming a first insulating layer covering the surface of the single crystal silicon layer, and forming a second insulating layer covering the surface of the first insulating layer Forming a second opening in the second insulating layer; and forming a first opening in the first insulating layer that is smaller than the opening of the second opening and communicates with the active region. And filling the first opening so as to protrude from the first opening until the second opening reaches the side wall of the opening of the second insulating layer.
Forming a conductive type single crystal semiconductor layer, and forming a semiconductor layer on the surfaces of the single crystal semiconductor layer and the second insulating layer to form a second layer on the surface of the single crystal semiconductor layer.
Forming a first single-crystal semiconductor layer of a conductivity type and forming a first polycrystalline semiconductor layer of a second conductivity type on the surface of the second insulating layer; By forming a semiconductor layer on the surface of the crystalline semiconductor layer, a second single crystal semiconductor layer is formed on the surface of the first single crystal semiconductor layer, and a second polycrystalline semiconductor layer is formed on the surface of the first polycrystalline semiconductor layer. Forming a dummy pattern having a width smaller than a lateral length of the second single crystal semiconductor layer on the second single crystal semiconductor layer, and using the dummy pattern as a mask, Introducing a second conductivity type impurity into a part of the first single crystal semiconductor layer and the first polycrystalline semiconductor layer; removing the dummy pattern; and adding the first single crystal semiconductor layer to the second single crystal semiconductor layer. Diffusion of first conductivity type connected to crystalline semiconductor layer And forming a.

Preferably, in the above invention, the step of forming the single-crystal semiconductor layer fills the first opening by utilizing selective formation and lateral formation of silicon germanium, and forms the second opening. In the above, silicon germanium is formed so as to protrude from the first opening until reaching the side wall of the opening of the second insulating layer.

In the above invention, preferably, the step of forming the second insulating layer includes a step of forming a silicon nitride film.

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, the first conductivity type single device is formed so as to protrude from the first opening until the second opening reaches the side wall of the opening of the second insulating layer. Forming the crystalline semiconductor layer forms a first polycrystalline semiconductor layer of the second conductivity type which is laterally extended on the surface of the second insulating layer, and forms a second polycrystalline semiconductor on the surface of the first polycrystalline semiconductor layer. A semiconductor layer can be formed.

In addition, a dummy pattern having a width smaller than the horizontal length of the single crystal semiconductor layer is formed on the single crystal semiconductor layer, and the dummy pattern is used as a mask to form one of the first single crystal semiconductor layers. And a step of introducing a second conductivity type impurity into the first polycrystalline semiconductor layer and the first polycrystalline semiconductor layer, so that a connection region between the first single crystal semiconductor layer and the first polycrystalline semiconductor layer also has a second conductivity type. Can be introduced, and the parasitic resistance in this region, which has conventionally been a problem, can be reduced.

Further, since the second opening of the second insulating layer is provided smaller than the first opening of the first insulating layer, the second insulating layer is formed by the first insulating layer when the impurity of the second conductivity type is introduced. Even when the impurity of the second conductivity type is diffused toward the single crystal semiconductor layer, the impurity is diffused only to the single crystal semiconductor layer located in the protruding region located in the second opening above the first insulating layer. The impurity of the second conductivity type does not reach the central region of the single crystal semiconductor layer which affects the operation characteristics of the semiconductor device, and thus the deterioration of the operation characteristics of the semiconductor device can be prevented.

In addition, the second region of the single crystal semiconductor layer
Since the diffusion of the conductivity type impurity can be prevented, the junction area between the single crystal semiconductor layer and the diffusion region of the second conductivity type impurity is reduced by implanting the second conductivity type impurity until reaching the first insulating layer. And the junction capacitance between the single crystal semiconductor layer and the diffusion region of the impurity of the second conductivity type can be reduced.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to each embodiment of the present invention and a method of manufacturing the same will be described below with reference to the drawings.

(Embodiment 1) (Structure of HBT) The structure of an HBT in this embodiment will be described with reference to FIG. FIG. 1 is a sectional view showing the structure of the HBT according to the present embodiment. An n ⁺ -type buried layer 2 of a first conductivity type is provided on the surface of a single-crystal silicon substrate 1 as a semiconductor substrate, and an n ⁻ -type collector layer 3 forming an active region is provided on the n ⁺ -type buried layer 2. Are defined by the element isolation insulating film 4.

An oxide film 6 as a first insulating film having an opening 6A of a predetermined size is provided on n ⁻ -type collector layer 3, and is formed on oxide film 6 more than opening 6A. A silicon nitride film 7 as a second insulating film having a large opening 7A is provided. Inside opening 6A and opening 7A, n ⁻ type silicon layer 8 as a single crystal semiconductor layer is provided.
Fills the first opening 6A and fills the second opening 7A.
Is provided so as to protrude from the first opening 6A until reaching the side wall of the opening of the silicon nitride film 7.

On the n ⁺ -type silicon layer 8a, there is provided a silicon germanium film 9A as a first single-crystal semiconductor layer of the second conductivity type comprising a p-type single-crystal region. Further, on this silicon germanium film 9A, there is provided a silicon film 10A as a second single crystal semiconductor layer composed of an intrinsic single crystal region. The region composed of the silicon germanium film 9A constitutes the intrinsic base region.

On the other hand, a silicon germanium film 9B as a first polycrystalline semiconductor layer comprising a p-type polycrystalline region is provided on silicon nitride film 7 so as to be continuous from silicon germanium film 9A. ing.
Further, on the silicon germanium film 9B, a silicon film 10 as a second polycrystalline semiconductor layer formed of a polycrystalline region and provided continuously from the silicon film 10A.
B is provided. In FIG. 1, the silicon germanium film 9A and the silicon germanium film 9B and the silicon film 10B provided on the left side of the silicon film 10A constitute a base extraction region.

The silicon film 1 is formed on the silicon film 10A.
A polysilicon electrode 13 connected to an emitter diffusion layer 13a as an n-type impurity diffusion layer provided at 0A is provided with an isolation film 12 interposed therebetween. Emitter diffusion layer 13
a is provided so as to be connected to the silicon film 10A. In addition, a silicide layer 14 is provided in an upper layer region of the polysilicon electrode 13.

On one silicon film 10 B, a silicide layer 15 is provided along the surface from the end of the sidewall 18. In FIG. 1, an oxide film 6, a silicon nitride film 7, a silicon germanium film 9
B and the right end face of the silicon film 10B are covered with a sidewall 19.

Further, the single crystal silicon substrate 1 of the surface of the right region in FIG. 1, is connected to the n + -type buried layer 2 n ⁺
A mold collector leading region 5 is provided, and a silicide layer 17 is provided above the collector leading region 5.

The base electrode 21, the emitter electrode 22, and the collector electrode 23 are connected to the silicide layer 14, the silicide layer 15, and the silicide layer 17, respectively, with an interlayer separation film 20 interposed therebetween.

(HBT Manufacturing Process) Next, the HBT manufacturing process according to the present embodiment having the above structure will be described.
This will be described with reference to FIGS. First, referring to FIG. 2, on the surface of the single crystal silicon substrate 1, after forming the n ⁺ -type buried layer 2, on the n ⁺ -type buried layer 2 by epitaxial growth, a thickness of about 1 [mu] m, the impurity concentration 1 × 10
An n ⁻ -type epitaxial silicon formation layer of about ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ is formed. After that, the element isolation insulating film 4 is formed by the LOCOS method, and the active region n is formed.
^A- type collector layer 3 and an n ^- type collector extraction region 5 are defined.

Next, referring to FIG. 3, an oxide film 6 having a thickness of about 10 nm to 300 nm and a silicon nitride film 7 having a thickness of about 10 nm to 500 nm are deposited on the entire upper surface of single crystal silicon substrate 1. . Then, using photoengraving technology, n
^- opening 7A in the silicon nitride film 7 on the type collector layer 3
Is formed, and the oxide film 6 is formed using the silicon nitride film 7 as a mask.
An opening 6A whose opening width is substantially the same as the opening 7A is formed.
Thereafter, wet etching is performed with phosphoric acid to retreat the opening 7A of the silicon nitride film 7 by 0.01 μm to 0.5 μm. Note that the silicon nitride film 7 needs to have such a thickness as to remain even after wet etching with phosphoric acid.

Next, referring to FIG. 4, the impurity concentration doped with phosphorus is set to 1 × 10 6 in opening 6 A of oxide film 6 where silicon formation layer is exposed and in opening 7 A of silicon nitride film 7. An n ⁻ -type silicon layer 8 of about ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ is selectively epitaxially grown. Thereafter, the concentration of the impurity doped with phosphorus is 1 × 10 ¹⁶ c
An n ⁺ -type silicon layer 8a of about m ⁻³ to 1 × 10 ¹⁹ cm ⁻³ is selectively epitaxially grown. At this time, the n ⁻ -type silicon layer 8 and the n ⁺ -type silicon layer 8a are grown so as to protrude from the first opening 6A in the second opening 7A until reaching the opening side wall of the silicon nitride film 7. This is because a silicon germanium film 9 described later is continuously grown. The total film thickness at the central portion between the n ⁻ type silicon layer 8 and the n ⁺ type silicon layer 8a is
It is about 1 μm. By having this film thickness,
Sufficient withstand voltage characteristics can be obtained.

Next, referring to FIG.
On the surface of the plate 1, 1 × 10¹⁸cm^-3~ 1 × 10²⁰
cm^-3About 20 nm to 200 nm
The silicon germanium film 9 is formed. This and
And epitaxially grown n ⁺Type silicon layer 8a
On both the upper surface and the upper surface of the silicon nitride film 7.
Subject (non-selective formation conditions), the silicon germanium film 9
Is formed. As a result, the epitaxially grown n
⁺On the silicon layer 8a, a silicon gel
The crystal film 9 is also epitaxially grown to form a p-type single crystal silicon.
Recongermanium film 9A (intrinsic base region) formed
Is done. On the silicon nitride film 7, a p-type
Polycrystalline silicon germanium film 9B is formed
You.

Next, referring to FIG. 6, an intrinsic silicon film 10 having a thickness of about 10 nm to 100 nm is formed on the surface of silicon germanium film 9. As a result, on the single-crystal silicon germanium film 9A (intrinsic base region), silicon is also epitaxially grown to form a single-crystal silicon film 10A. On the polycrystalline silicon germanium film 9B, a polycrystalline silicon film 10B is formed.

Next, referring to FIG. 7, a nitride film having a thickness of about 10 nm to 10000 nm is deposited on the surface of silicon film 10. Thereafter, a dummy pattern 11 made of a nitride film having a lateral width smaller than the lateral width of the silicon film 10A by about 0.01 μm to 0.5 μm is formed above the n ⁻ -type collector layer 3 by photolithography. I do. Thereafter, using the dummy pattern 11 as a mask, boron is introduced toward a part of the single-crystal silicon germanium film 9A and the polycrystalline silicon germanium film 9B. At this time, the conditions for introducing boron are as follows:
keV to 50 keV, implantation dose 1 × 10 ¹⁴ cm ⁻² to 1 × 1
Perform at 0 ¹⁷ cm ^-2 .

Next, referring to FIG. 8, dummy pattern 11 made of a nitride film is receded (narrowed) by etching with phosphoric acid. Thereafter, an oxide film 12 is deposited on the entire surface of the silicon film 10, and the surface of the oxide film 12 is planarized by a CMP method. Next, referring to FIG. 9, dummy pattern 11 is removed by wet etching to expose single crystal silicon film 10A.

Next, referring to FIG.
A is formed on A and the oxide film 12 with polysilicon doped with phosphorus at 1 × 10 ²⁰ cm ⁻³ or more. Then, R
Heat treatment is performed by TA at 700 ° C. to 1000 ° C. for 10 seconds to 5 minutes to form an emitter diffusion layer 13a. Thereafter, a polysilicon electrode 13 connected to the emitter diffusion layer 13a is formed by using a photolithography technique. Thereafter, oxide film 12 is removed by dry etching using polysilicon electrode 13 as a mask.

Next, with reference to FIG. 11, by photolithography to form a mask having a predetermined shape, n ^- located above the -type collector lead-out region 5, an oxide film 6, the silicon nitride film 7, multi The crystalline silicon germanium film 9B and the polycrystalline silicon film 10B are removed. Thereafter, a sidewall 18 made of an oxide film covering the side surface of the polysilicon electrode 13 and the side surface of the oxide film 12, an oxide film 6, a silicon nitride film 7, a polycrystalline silicon germanium film 9B,
Then, a side wall 19 made of an oxide film covering the side surface of the polycrystalline silicon film 10B is formed.

Thereafter, a heat treatment is applied after depositing, for example, Co on the surface by a known silicidation process. Thereby, the silicide layer 14 on the surface of the polysilicon electrode 13, and the silicon film 10A and the silicide layer 15 on the surface of the silicon film 10B, the surface is exposed, n ^-
Silicide layer 17 is formed on the surface of mold collector extraction region 5. Although the case where a cobalt silicide layer is formed as the silicide layer has been described, a titanium silicide layer, a tungsten silicide layer, or the like can be applied.

After depositing an interlayer separation film 20, the silicide layer 14 and the silicide layer 1 are formed by photolithography.
5, a contact hole leading to the silicide layer 17 is opened, a wiring layer is further formed, and a predetermined patterning step is performed, whereby a base electrode 21, an emitter electrode 22, and a collector electrode 23 are formed by aluminum wiring, SiGe (silicon germanium) -HB having a structure according to the present embodiment shown in FIG.
T is completed.

(Operation / Effect) As described above, according to the structure of the SiGe-HBT of the present embodiment, the opening 6 is formed until the opening 7A reaches the side wall of the silicon nitride film 7 at the opening 7A.
N it is provided so as pushed out from the A ^- by having an -type silicon layer 8 and the n ⁺ -type silicon layer 8a, n ^- silicon germanium film of a single crystal formed on the -type silicon layer 8 and the n ⁺ -type silicon layer 8a 9A can be made longer than before, and impurities can be implanted into a single crystal SiGe connection region of the silicon germanium film 9A and the silicon germanium film 9B. , The resistance can be reduced. Further, since the single crystal is used, it is possible to suppress the influence of the variation in the resistance value due to the grain boundary.

Further, the SiGe-H according to the present embodiment
According to the BT manufacturing method, the first opening 6A is formed until the second opening 7A reaches the opening side wall of the silicon nitride film 7.
The n ^- type silicon layer 8 and the n ⁺ type silicon layer 8a are formed so as to protrude from the silicon nitride film 7.
It is possible to form a p-type polycrystalline silicon germanium film 9B which is laterally drawn out on the surface of the substrate and a polycrystalline silicon film 10B on the surface of the silicon germanium film 9B.

On the n ⁻ -type silicon layer 8 and the n ⁺ -type silicon layer 8a, a nitride film having a width smaller than the lateral length of the n ⁻ -type silicon layer 8 and the n ⁺ -type silicon layer 8a is formed. By forming a dummy pattern 11 and using the dummy pattern 11 as a mask to introduce boron into a part of the single-crystal silicon germanium film 9A and the polycrystalline silicon germanium film 9B, FIG. As shown, it is possible to introduce boron also into the connection region 9C between the silicon germanium film 9A and the polycrystalline silicon germanium film 9B, thereby reducing the parasitic resistance in this region, which has been a problem in the past. And a current path path with a small parasitic resistance value as shown by an arrow P1 in FIG. 12 can be realized.

The opening 7A of the silicon nitride film 7 is
Since it is provided smaller than the opening 6A of the oxide film 6, when the boron is introduced, boron is reduced by the oxide film 6 to n ^−.
Even if it diffuses toward n type silicon layer 8 and n ⁺ type silicon layer 8a, n ⁻ type silicon layer 8 and n ⁺ located in the protruding region located at opening 7A above oxide film 6
Is diffused only to the silicon type layer 8a.
Boron does not reach the central regions (mushroom-shaped shaft portions) of the n ⁻ -type silicon layer 8 and the n ⁺ -type silicon layer 8a which affect the operating characteristics of the e-HBT, and the SiGe-HBT
Can be prevented from deteriorating the operating characteristics of the device.

[0062] Further, n ^- since the diffusion of boron into the central region of -type silicon layer 8 and the n ⁺ -type silicon layer 8a can be prevented, by implanting, for example, to reach a boron oxide film 6, n ^- -type silicon layer 8 and n ⁺ -type silicon layer 8a and it is possible to reduce the pn junction area between the diffusion region of boron, n ^- reduce the pn junction capacitance of the -type silicon layer 8 and the n ⁺ -type silicon layer 8a and the diffusion region of the boron It is also possible to make it.

(Embodiment 2) (Structure of HBT) Next, the structure of the HBT according to the present embodiment will be described with reference to FIG. FIG.
FIG. 2 is a cross-sectional view illustrating a structure of the HBT according to the present embodiment. The difference between the structure of the HBT of the present embodiment and the structure of the HBT of the first embodiment is that the silicon germanium film 9B and the silicon film are provided on the end surface of the silicon nitride film 71 on the n ⁺ -type collector extraction region 5 side. 1
0B is formed so as to wrap around and the silicon film 10B is covered with the side wall 19, and other structures are the same. Therefore, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

(Manufacturing Process of HBT) Next, the manufacturing process of the HBT according to the present embodiment having the above structure will be described.
This will be described with reference to FIGS. First, referring to FIG. 14, the steps up to formation of oxide film 6 are the same as the manufacturing steps of the first embodiment described with reference to FIGS. Next, a silicon nitride film 71 having a thickness of about 10 nm to 500 nm is deposited. Thereafter, the silicon nitride film 71 on the n ⁻ -type collector layer 3 is patterned by using a photolithography technique, and the opening 7 is formed on the n ⁺ -type collector lead-out region 5 side.
Form 1B. After that, an opening 6A smaller than the opening 7A is formed in the oxide film 6.

Next, referring to FIG. 15, a silicon forming layer
Opening 6A of oxide film 6 where silicon is exposed, and silicon nitride
Inside the opening 7A of the film 7, the impurity concentration doped with phosphorus is
Degree 1 × 10¹⁵cm^-3~ 1 × 10¹⁷cm^-3Degree n^-Type
The silicon layer 8 is selectively epitaxially grown. So
After that, the impurity concentration doped with phosphorus is 1 × 10 ¹⁶
cm^-3~ 1 × 10¹⁹cm^-3Degree n⁺Type silicon layer 8a
Is selectively epitaxially grown. At this time, n^-
Type silicon layer 8 and n⁺Mold silicon layer 8a
At 71A, the opening reaches the side wall of the silicon nitride film 7
It is grown so as to protrude from the opening 6A. this
Is to connect a silicon germanium film 9 described later
It is for growing. Note that n^-Type silicon layer 8 and n⁺
The total film thickness at the center with the mold silicon layer 8a is about
It is about 0.5 μm to 2.0 μm. Have this thickness
Thereby, sufficient withstand voltage characteristics can be obtained.

Next, the surface of the single crystal silicon substrate 1 is
Ron 1 × 10¹⁸cm^-3~ 1 × 10 ²⁰cm^-3Degree dope
Silicon germanium with a thickness of about 20 nm to 200 nm
A new film 9 is formed. At this time, epitaxial
Grown n⁺Of silicon nitride layer 8a and silicon nitride
(Only on oxide film 6)
Under conditions not to form), the silicon germanium film 9
Perform formation. As a result, the epitaxially grown n⁺
On the silicon layer 8a, a silicon gel
Film 9 is also epitaxially grown to form a p-type single crystal silicon.
Congelmanium film 9A (intrinsic base region) is formed
It is. On the silicon nitride film 71, a p-type
Polycrystalline silicon germanium film 9B is formed
You.

Next, referring to FIG. 16, an intrinsic silicon film 10 having a thickness of about 10 nm to 100 nm is formed on the surface of silicon germanium film 9.
As a result, on the single-crystal silicon germanium film 9A (intrinsic base region), silicon is also epitaxially grown to form a single-crystal silicon film 10A.
On the polycrystalline silicon germanium film 9B, a polycrystalline silicon film 10B is formed.

Next, referring to FIG.
A nitride film is deposited on the surface of the substrate. Thereafter, the silicon film 10 is formed above the n ⁻ -type collector layer 3 by using a photoengraving technique.
A dummy pattern 11 made of a nitride film having a lateral width smaller than the lateral width of A by about 0.01 μm to 0.5 μm.
To form Thereafter, using the dummy pattern 11 as a mask, boron is introduced toward a part of the single-crystal silicon germanium film 9A and the polycrystalline silicon germanium film 9B. At this time, boron is introduced under the conditions of an implantation energy of 5 keV to 50 keV and an implantation amount of 1 × 1.
It is carried out at 0 ¹⁴ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² .

Next, referring to FIG. 18, dummy pattern 11 made of a nitride film is receded (narrowed) by etching with phosphoric acid. Thereafter, an oxide film 12 is deposited on the entire surface of the silicon film 10, and the surface of the oxide film 12 is planarized by a CMP method. Next, referring to FIG. 19, dummy pattern 11 is removed by wet etching to expose single crystal silicon film 10A.

Next, referring to FIG.
A and a polysilicon doped with 4 × 10 ²⁰ cm ⁻³ or more of arsenic is formed on the oxide film 12. Then, R
Heat treatment is performed by TA at 700 ° C. to 1000 ° C. for 10 seconds to 5 minutes to form an emitter diffusion layer 13a. Thereafter, a polysilicon electrode 13 connected to the emitter diffusion layer 13a is formed by using a photolithography technique. Thereafter, oxide film 12 is removed by dry etching using polysilicon electrode 13 as a mask.

Thereafter, a sidewall 18 made of an oxide film covering the side surface of the polysilicon electrode 13 and the side surface of the oxide film 12, the oxide film 6, the silicon nitride film 7, the polycrystalline silicon germanium film 9B, and the polycrystalline silicon Side wall 1 made of an oxide film covering the side surface of silicon film 10B
9 are formed.

Thereafter, a heat treatment is applied after depositing Co on the surface by a known silicidation process. Thereby, the silicide layer 14 is formed on the surface of the polysilicon electrode 13.
Then, a silicide layer 15 is formed on the surfaces of the silicon films 10A and 10B whose surfaces are exposed, and a silicide layer 17 is formed on the surface of the n ⁻ -type collector lead-out region 5.
Thereafter, after depositing the interlayer separation film 20, a contact hole communicating with the silicide layer 14, the silicide layer 15, and the silicide layer 17 is opened by using a photoengraving technique, a wiring layer is further formed, and a predetermined patterning step is performed. Thereby, the base electrode 21, the emitter electrode 22, and the collector electrode 23 are formed, and the SiGe-HBT having the structure according to the present embodiment shown in FIG. 13 is completed.

(Operation / Effect) As described above, the same operation and effect as those of the first embodiment can be obtained also in the structure and manufacturing method of the SiGe-HBT according to the present embodiment.
According to the present embodiment, since opening 71B is formed in the step shown in FIG. 14, position above n ⁻ -type collector lead-out region 5 described in FIG. Since the oxide film 6, the silicon nitride film 7, the polycrystalline silicon germanium film 9B, and the polycrystalline silicon film 10B need not be etched and removed, the manufacturing process can be simplified.

(Embodiment 3) (Structure of HBT) Next, the structure of the HBT according to the present embodiment will be described with reference to FIG. FIG.
FIG. 2 is a cross-sectional view illustrating a structure of the HBT according to the present embodiment. The difference between the HBT structure according to the present embodiment and the HBT structure according to the first embodiment is that the manufacturing process of the n-type silicon layer 80 is different. Is different, and the other structures are the same. Therefore, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

(Manufacturing Process of HBT) Next, the manufacturing process of the HBT according to the present embodiment having the above structure will be described.
This will be described with reference to FIGS. First, the steps up to the step of forming opening 6A in oxide film 6 are the same as those in the first embodiment.

Next, referring to FIG. 22, the opening 6A of oxide film 6 where the silicon formation layer is exposed and the inside of opening 7A of silicon nitride film 7 have an impurity concentration of 1 × 10 An n-type silicon layer 80 of about ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ is selectively formed. At this time, the n-type silicon layer 80 is connected to the silicon nitride film 7 in the opening 7A.
Is grown so as to protrude from the opening 6A until reaching the side wall of the opening. This is because a silicon germanium film 9 described later is continuously grown.

In this embodiment, the n-type silicon layer 80 is formed by growing the silicon layer 80 under a UHV-CVD condition at a substrate temperature of 700 ° C. or less and without a facet. Thereby, the silicon layer can be grown only in the concave portion surrounded by the silicon nitride film 7. The film thickness at the center of the n-type silicon layer 80 is about 1
It is about μm. With this thickness, sufficient withstand voltage characteristics can be obtained.

Next, referring to FIG.
On the surface of the substrate 1, 1 × 10 ¹⁷cm^-3~ 1 × 10
²⁰cm^-3About 20 nm to 200 nm
Then, a silicon germanium film 9 is formed. This and
On the epitaxially grown n-type silicon layer 80,
And conditions for forming both on silicon nitride film 7
(Non-selective formation conditions), the silicon germanium film 9
Perform formation. As a result, epitaxially grown n-type
On the silicon layer 80, silicon gel
The film 9 is also epitaxially grown to a p-type single crystal silicon.
The germanium film 9A (intrinsic base region) is formed.
You. On the silicon nitride film 7, a p-type
A crystalline silicon germanium film 9B is formed.

Next, referring to FIG. 24, an intrinsic silicon film 10 having a thickness of about 10 nm to 100 nm is formed on the surface of silicon germanium film 9.
As a result, on the single-crystal silicon germanium film 9A (intrinsic base region), silicon is also epitaxially grown to form a single-crystal silicon film 10A.
On the polycrystalline silicon germanium film 9B, a polycrystalline silicon film 10B is formed.

Next, referring to FIG.
A nitride film is deposited on the surface of the substrate. Thereafter, the silicon film 10 is formed above the n ⁻ -type collector layer 3 by using a photoengraving technique.
A dummy pattern 11 made of a nitride film having a lateral width smaller than the lateral width of A by about 0.01 μm to 0.5 μm.
To form Thereafter, using the dummy pattern 11 as a mask, boron is introduced toward a part of the single-crystal silicon germanium film 9A and the polycrystalline silicon germanium film 9B. At this time, boron is introduced under the conditions of an implantation energy of 5 keV to 50 keV and an implantation amount of 1 × 1.
It is carried out at 0 ¹⁴ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² .

Thereafter, through the same steps as shown in FIGS. 8 to 11 described in the first embodiment, the SiGe-HBT having the structure of the present embodiment shown in FIG.
Is completed.

(Function / Effect) As described above, the structure and manufacturing method of the SiGe-HBT according to the present embodiment
The same operation and effect as in the first embodiment can be obtained.

In each of the above embodiments, n ⁻
Collector region 3, n ⁻ type silicon layer 8 and n ⁺ type silicon layer 8a form a collector region, silicon germanium film 9A forms an intrinsic base region, and emitter diffusion layer 13a forms an emitter region. As described above, the emitter region is formed by the n ⁻ type collector layer 3, the n ⁻ type silicon layer 8, and the n ⁺ type silicon layer 8a, the intrinsic base region is formed by the silicon germanium film 9A, and the emitter diffusion layer 13a is formed. , It is also possible to adopt a structure constituting a collector region. In this configuration, the emitter is located down, and the contact area between the base region and the emitter region can be made smaller than that of the conventional structure.
fe) can be obtained.

The embodiments disclosed this time are illustrative in all aspects and are not considered to be restrictive. The technical scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

[0085]

According to the semiconductor device according to the present invention,
The second opening is formed on the single crystal semiconductor layer by having the first conductivity type single crystal semiconductor layer provided so as to protrude from the first opening until reaching the opening side wall of the second insulating layer. Since the length of the first and second single-crystal semiconductor layers of the second conductivity type can be increased as compared with the conventional case, impurities can be implanted into the connection regions of the first and second single-crystal semiconductor layers. Thus, it is possible to reduce the resistance in this connection region.

According to the method of manufacturing a semiconductor device according to the present invention, it is possible to introduce a second conductivity type impurity into a connection region between the first single crystal semiconductor layer and the first polycrystalline semiconductor layer. Thus, it is possible to reduce the parasitic resistance in this region, which has conventionally been a problem, and its variation. Further, even when the impurity of the second conductivity type is diffused toward the single crystal semiconductor layer by the first insulating layer when the impurity of the second conductivity type is introduced, the impurity is located in the second opening over the first insulating layer. Since the impurity is diffused only to the single crystal semiconductor layer located in the protruding region, the second conductivity type impurity does not reach the central region of the single crystal semiconductor layer which affects the operation characteristics of the semiconductor device, and the operation of the semiconductor device Deterioration of characteristics can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of an HBT according to a first embodiment.

FIG. 2 is a cross-sectional view of a first manufacturing step of the HBT according to the first embodiment.

FIG. 3 is a second manufacturing step cross-sectional view of the HBT according to the first embodiment;

FIG. 4 is a sectional view of a third manufacturing step of the HBT according to the first embodiment;

FIG. 5 is a sectional view of a fourth manufacturing step of the HBT according to the first embodiment.

FIG. 6 is a fifth manufacturing step cross-sectional view of the HBT according to the first embodiment.

FIG. 7 is a cross-sectional view of a sixth manufacturing step of the HBT according to the first embodiment.

FIG. 8 is a sectional view of a seventh manufacturing step of the HBT according to the first embodiment.

FIG. 9 is a sectional view of an HBT according to the first embodiment in an eighth manufacturing step.

FIG. 10 is a sectional view of a ninth manufacturing step of the HBT according to the first embodiment.

FIG. 11 is a cross-sectional view showing a tenth manufacturing step of the HBT according to the first embodiment.

FIG. 12 is a diagram illustrating the function and effect of the HBT structure according to the first embodiment.

FIG. 13 is a sectional view showing a structure of an HBT according to a second embodiment.

FIG. 14 is a sectional view showing a third manufacturing step of the HBT according to the second embodiment.

FIG. 15 is a sectional view of a fourth manufacturing step of the HBT according to the second embodiment.

FIG. 16 is a fifth manufacturing step cross-sectional view of the HBT according to the second embodiment.

FIG. 17 is a sectional view of a sixth manufacturing step of the HBT according to the second embodiment.

FIG. 18 is a sectional view of a seventh manufacturing step of the HBT according to the second embodiment.

FIG. 19 is a sectional view of an HBT according to the second embodiment in an eighth manufacturing step.

FIG. 20 is a cross-sectional view of a ninth manufacturing step of the HBT according to the second embodiment.

FIG. 21 is a sectional view showing a structure of an HBT according to a third embodiment.

FIG. 22 is a sectional view showing a third manufacturing step of the HBT according to the third embodiment.

FIG. 23 is a sectional view of a fourth manufacturing step of the HBT according to the third embodiment.

FIG. 24 is a sectional view showing a fifth manufacturing step of the HBT according to the third embodiment.

FIG. 25 is a sectional view of a sixth manufacturing step of the HBT according to the third embodiment.

FIG. 26 is a cross-sectional view showing the structure of an HBT according to the related art.

FIG. 27 is a cross-sectional view of a first manufacturing step of the HBT according to the related art.

FIG. 28 is a sectional view of a second manufacturing step of the HBT according to the conventional technique.

FIG. 29 is a sectional view showing a third manufacturing step of the HBT according to the related art.

FIG. 30 is a sectional view showing a fourth manufacturing step of the HBT according to the related art.

FIG. 31 is a sectional view showing a fifth manufacturing step of the HBT according to the related art.

FIG. 32 is a sectional view showing a sixth manufacturing step of the HBT according to the related art.

FIG. 33 is a sectional view showing a seventh manufacturing step of the HBT according to the related art.

FIG. 34 is a sectional view of an HBT in an eighth manufacturing process according to the related art.

FIG. 35 is a sectional view showing a ninth manufacturing step of the HBT according to the conventional technique.

FIG. 36 is a sectional view showing a tenth manufacturing step of the HBT according to the related art.

FIG. 37 is a cross-sectional view for explaining a problem of the HBT in the related art.

FIG. 38 is a partially enlarged cross-sectional view for explaining a problem of the HBT in the related art.

[Explanation of symbols]

1 single-crystal silicon substrate, 2 n ⁺ type buried layer, 3
n ⁻ type collector layer, 4 element isolation insulating film, 5 n ⁺ type collector lead region, 6 oxide film, 6A opening, 7,71 silicon nitride film, 7A opening, 8 n ⁻ type silicon layer (single crystal), 8a n ⁺ type silicon layer (single crystal), 9A
Silicon germanium film (single crystal), 9B silicon germanium film (polycrystal), 10A silicon film (single crystal), 10B silicon film (polycrystal), 11 dummy pattern (nitride film), 12 isolation film, 13 polysilicon electrode, 13a Emitter diffusion layer, 14, 15, 1
7 silicide layer, 18, 19 sidewall, 20
Interlayer separation film, 21 base electrode, 22 emitter electrode,
23 Collector electrode, 80 n-type silicon layer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masami Hayashi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Yoshiryuu Kawama 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Katsuhiro Imada 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Tatsuhiko Ikeda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F term in Ryo Denki Co., Ltd. (reference) 5F003 BB05 BB06 BB07 BB08 BC02 BC08 BE07 BE08 BF03 BF06 BF10 BG03 BG06 BH06 BH07 BH18 BH93 BM01 BP32 BP33 BP34 BS06 BS08

Claims (7)

[Claims] A first conductivity type single crystal silicon layer provided on a surface of a semiconductor substrate; and a first conductivity type single crystal silicon layer selectively provided in the single crystal silicon layer.
A conductive type active region, a first insulating layer having a first opening communicating with the active region, and covering a surface of the single crystal silicon layer; and a first opening provided on a surface of the first insulating layer. A second insulating layer having a second opening larger than the first opening so as to include the portion, and filling the first opening and reaching the opening side wall of the second insulating layer at the second opening. A first conductivity type single crystal semiconductor layer provided so as to protrude from the first opening, a second conductivity type first single crystal semiconductor layer provided on a surface of the single crystal semiconductor layer, A first polycrystalline semiconductor layer of a second conductivity type formed on the surface of the insulating layer and provided continuously with the first single crystal semiconductor layer; and a second single crystal provided on the surface of the first single crystal semiconductor layer A semiconductor layer formed on a surface of the first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer provided continuously with the crystal semiconductor layer; and a first conductivity type impurity diffusion layer provided in the second single crystal semiconductor layer and connected to the first single crystal semiconductor layer. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said active region and said single-crystal semiconductor layer constitute a collector region, said first single-crystal semiconductor layer constitutes an intrinsic base region, and said impurity diffusion layer constitutes an emitter region. 3. The semiconductor device according to claim 1, wherein said active region and said single-crystal semiconductor layer constitute an emitter region, said first single-crystal semiconductor layer constitutes an intrinsic base region, and said impurity diffusion layer constitutes a collector region. 4. The semiconductor device according to claim 1, wherein the first single crystal semiconductor layer and the first polycrystalline semiconductor layer are made of silicon germanium.
4. The semiconductor device according to any one of items 1 to 3. 5. A step of forming a first conductivity type single crystal silicon layer on a surface of a semiconductor substrate; a step of selectively forming a first conductivity type active region in the single crystal silicon layer; Forming a first insulating layer covering the surface of the silicon layer, forming a second insulating layer covering the surface of the first insulating layer, and forming a second opening in the second insulating layer; Forming a first opening smaller than the opening of the second opening in the first insulating layer through the active region; filling the first opening, and forming a second opening in the second opening; Forming a first conductivity type single crystal semiconductor layer so as to protrude from the first opening until reaching the opening side wall of the insulating layer; and forming a semiconductor layer on surfaces of the single crystal semiconductor layer and the second insulating layer. Forming the single crystal semiconductor layer Forming a first single-crystal semiconductor layer of the second conductivity type on the surface and forming a first polycrystalline semiconductor layer of the second conductivity type on the surface of the second insulating layer; By forming a semiconductor layer on the surface of the first polycrystalline semiconductor layer, a second single crystal semiconductor layer is formed on the surface of the first single crystal semiconductor layer, and a second polycrystalline semiconductor layer is formed on the surface of the first polycrystalline semiconductor layer. Forming a crystalline semiconductor layer; and forming a dummy pattern having a width smaller than a lateral length of the second single crystal semiconductor layer on the second single crystal semiconductor layer, using the dummy pattern as a mask. Introducing a second conductivity type impurity into a part of the first single crystal semiconductor layer and the first polycrystalline semiconductor layer; removing the dummy pattern; A first conductivity type connected to the first single crystal semiconductor layer Forming an impurity diffusion layer of the above. 6. The step of forming the single-crystal semiconductor layer includes filling the first opening using selective formation of silicon germanium and lateral growth, and forming the second opening.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the silicon germanium is formed so as to protrude from the first opening until reaching the opening side wall of the second insulating layer in the opening. 7. The method according to claim 5, wherein forming the second insulating layer includes forming a silicon nitride film.