JP2002351683A - Program updating control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start updating a program again without problems even when a fault is generated at the time of updating the program. SOLUTION: In the case that a key is inputted (S301) and whether or not it is an updating request key is judged (3302), the reception processing of updating data is performed (S304) and whether or not they are data for updating for BOOT is judged (S305). In the case of judging that it is the updating instruction of a code for BOOT, whether or not a second nonvolatile memory is in an initial state is confirmed (S306). In the case that it is already written, the code updating processing of a first nonvolatile memory is performed (S308). In the case that it is not written yet, the code updating processing of writing an optimum code for BOOT to the second nonvolatile memory is performed (S307). Whether or not an updating processing is normally ended is judged (S309), and in the case that it is normally ended, the code updating processing of the first nonvolatile memory part is performed (S308).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program update control system which can provide a restartable system even if a problem occurs when updating a program in a nonvolatile memory in a system using a nonvolatile memory. It is about the method.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus equipped with a microcomputer or the like has a minimum BOO in a mask ROM or the like.
A code for T and the like is held, and the portion is not rewritable, so that the code can be used for initial startup. However, with this configuration, if the configuration is changed by the user after the shipment, the boot code may not be able to be activated with the BOOT code prepared at the time of shipment, depending on the power-on situation.

Further, a program (BO) is stored in a nonvolatile memory.
OT code and application), when updating the contents of this non-volatile memory,
If the update of the program is interrupted due to a data transmission error or unexpected trouble of turning off the power, the system cannot be restored, and a problem such as replacement of the board may occur.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation. When updating a program in a nonvolatile memory, the present invention is performed once before writing data to the first nonvolatile memory. By writing the optimal BOOT code into the second nonvolatile memory (OTP area) in which only the first nonvolatile memory can be written,
It is an object of the present invention to provide a system in which a program can be re-updated many times without any problem by using the second nonvolatile memory even if a problem occurs.

[0005]

According to the present invention, there is provided a system in which a rewritable first nonvolatile memory and a once-writable second nonvolatile memory (OTP area) are mounted. When updating the BOOT code mounted in the nonvolatile memory of the above, after writing the optimal BOOT code in the second nonvolatile memory,
A program update control method including a program for updating a first nonvolatile memory.

According to the present invention, in the above-mentioned program update control method, an optimum B is stored in the second nonvolatile memory.
When writing the OOT code, the system configuration at that time is automatically determined, and the optimum BOOT code is selectively written. The present invention further provides the program update control method, wherein
The OOT code can be switched and written into the first nonvolatile memory or the second nonvolatile memory by an external signal.

According to the present invention, in the above-mentioned program update control method, when a problem occurs in the middle of writing a BOOT code in the second nonvolatile memory,
The first non-volatile memory is not updated. The present invention further provides the program update control method, wherein when the program is updated, the first update data for the nonvolatile memory and the update data for the second nonvolatile memory are received together, and the data of the update data is received. The data is automatically discriminated from the structure and written into each memory.

Further, according to the present invention, in the above-mentioned program update control method, when a program is updated, the BOOT code update data and the application update data are received together, and the BOOT code update data is automatically determined from the data structure of the update data. The application code updates the first and second nonvolatile memories, and the application data updates only the first nonvolatile memory. The present invention further provides the program update control method, wherein the second nonvolatile memory is already updated when the first nonvolatile memory is updated.
The non-volatile memory is not updated.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a program update control method according to the present invention will be described below with reference to the drawings.
The following embodiment is an example of the present invention and does not limit the technical scope of the present invention. FIG.
FIG. 1 is a block diagram showing a configuration in an embodiment of an apparatus for implementing a program update control method according to the present invention.

In the figure, 1 is a CPU, 2 is a memory controller, 3 is a first nonvolatile memory, 4 is a second nonvolatile memory (OTP memory: a memory which can be written only once), 5 is a standard and extension DRAM, 7
Denotes a key input unit, 8 denotes a parallel I / F, 9 denotes an optional display LCD unit, and 6 denotes an I / O for managing the key input unit 7, the parallel I / F 8 and the LCD unit 9. Department. Reference numeral 10 denotes a switch for selecting a memory at the time of startup. When the switch 10 is on the A side, the switch is switched from the first nonvolatile memory 3 to the second nonvolatile memory when the switch 10 is on the B side. The memory is started from the memory 4.

FIG. 2 is a diagram showing a memory configuration in the first and second nonvolatile memories. First nonvolatile memory 3
Address (0x00000-0x0FFF) in B
In the OOT code section 21, the BOOT code is stored, and the address (0x1000 to 0x1FFF) is stored.
Is a code updating unit 22 in which a code updating program is stored, and the address (0x2000 to 0xFFFF) is
The application unit 23 stores application codes.

The BOOT code section 21 has a power supply O.
A code updating program is installed in the initialization routine and device driver of each part required at the time of N, the boot part of the OS, and the code updating part 22. One of the functions is a first nonvolatile memory. When updating, the optimal BOOT
A code for writing only the application code to the second nonvolatile memory is included. Further, the application code in the application unit 23 includes actual code that actually runs on the OS. In addition, the code section 24
In the nonvolatile memory 4 at the time of shipment, which is in an initial state (ALL “1”).

FIG. 3 is a flowchart showing the procedure of a program update process in the program update control method of the present invention. The process waits for a key input as a code data update instruction input (step S301). If there is any key input, it is determined whether or not it is an update request key (step S302). If it is determined in step S302 that the code is other than an update request, data processing corresponding to the key is performed (step S303).

On the other hand, if it is determined in step S302 that the request is an update request, a process of receiving update data is performed (step S304). This data is parallel I / F
8, and the received data is stored in the DRAM 5. Then, the data received in step S304 is
It is determined whether or not the data is BOOT update data (step S305). If it is determined in step S305 that the data is not BOOT update data, an update process (hereinafter, referred to as “code update process A”) of the specified code portion of the first nonvolatile memory is performed (step S30).
8).

If it is determined in step S305 that the received data is an instruction to update the BOOT code,
Before updating the BOOT code in the first nonvolatile memory, it is confirmed whether or not the second nonvolatile memory is in the initial state (step S306). As a determination method in this case, since all bits of the value of the nonvolatile memory in the initial state are “1”, the data of the head address is read and the FF is read.
Or not.

As another method, it is also possible to write a specific code at a specific address in the second nonvolatile memory after writing to the second nonvolatile memory, and to compare with the data. . Then, step S306
In step S308, if it is determined that the data has already been written, code update processing A is performed (step S308). If it is determined in step S306 that data has not been written, a code update process (hereinafter, referred to as “code update process B”) for writing an optimal BOOT code into the second nonvolatile memory is performed (hereinafter, referred to as “code update process B”). Step S307).

Next, it is determined whether or not the update processing in step S307 is completed normally (step S309). If the update processing is completed normally, code update processing A of the first nonvolatile memory is performed (step S309). S308). Step S
If it is determined in 309 that an error has occurred, an error message is displayed (step S310), and the code update processing B is interrupted.

FIG. 4 is a flowchart showing a detailed procedure of a process (code update process B) of writing an optimum BOOT code into the second nonvolatile memory (OTP) in step S307 of FIG. First, the second nonvolatile memory (OTP) is set in a writable mode (step S401). Next, the minimum required basic common part (C
Write a basic driver for PU initialization and the like, an OS activation unit, and a code update unit (step S402). The basic common part is necessary in any system, and is written first.

It is determined whether an error has occurred during the writing (step S403). If it is determined that a writing error has occurred, the process is interrupted. In addition, when the writing is normally performed, it is confirmed whether or not the optional LCD unit 9 shown in FIG. 1 is mounted (step S404), and if not, the step S407 is performed.
To the next step S40
At 5, the LCD driver section is written. At the time of writing the LCD driver, it is determined whether or not an error has occurred (step S406). If it is determined that a writing error has occurred, the process is interrupted.

On the other hand, if the writing was successful,
Similarly, it is checked whether the optional extended DRAM unit 5 shown in FIG. 1 is mounted (step S40).
7) If it is not mounted, the process proceeds to step S410. If it is mounted, in the next step S408, the driver of the extension DRAM is written. At the time of writing to the driver for the extension DRAM, it is determined whether or not an error has occurred (step S409). If an error has occurred, the process is interrupted.

When the data can be written normally, a specific fixed address in the second nonvolatile memory (OTP) is determined so that it can be recognized that the data has been written to the second nonvolatile memory (OTP). The written code is written (step S410), and the process ends. In the flow of FIG. 4, the optimal BOO for the second nonvolatile memory
Although the T code is written, it is also possible to select a plurality of dedicated drivers and write the optimal BOOT code by the same processing method.

FIG. 5 is a diagram showing an example of the configuration of the update data received in step S304 of FIG. The update data 501 is stored in the BOOT update data section 502.
And an application update data section 503. The BOOT update data section 502 has a common specification in the first and second non-volatile memories, and has Header information 504 indicating information about data, and a basic OS section 50.
5, an LCD driver 506 as an extended function, an extended memory driver 507, and a utility unit 508.

In step S305 of FIG.
The next step is determined by determining the der information 504. The application update data unit 503 includes Header information 509 indicating information about data and application update data 510.

FIG. 6 is a flowchart showing a detailed procedure of the process (code update process A) of writing the optimal BOOT code into the first nonvolatile memory in step S308 of FIG. First, the first nonvolatile memory is set to a writable mode (step S601). Next, it is determined whether only the application section is updated (step S
602) If only the application unit, proceed to S612. If the BOOT code is to be updated, the minimum required basic common parts (basic driver such as CPU initialization, OS startup unit, and code update unit) Is written (step S60).
3). It is determined whether or not an error has occurred during this writing (step S604). If it is determined that a writing error has occurred, the writing mode of the first memory is canceled (step S615), and the process is interrupted.

When writing is normally performed,
It is confirmed whether or not the LCD unit 9 is mounted (step S605). If the LCD unit 9 is not mounted, the process proceeds to step S608. If the LCD unit 9 is mounted, the LCD driver unit is written in the next step S606. . At the time of writing the LCD driver, it is determined whether or not an error has occurred (step S607). If it is determined that a writing error has occurred, the writing mode of the first memory is released (step S615). Stop processing.

On the other hand, when the writing is normally completed,
It is confirmed whether or not the extended DRAM unit 5 is mounted (step S608).
Proceeding to 611, if it is mounted, in the next step S609, writing to the driver section of the extension DRAM is performed.

It is determined whether or not an error has occurred at the time of writing the driver of the extension DRAM (step S61).
0) When an error occurs, the write mode of the first memory is released (step S615), and the process is interrupted. If the writing has been normally completed, it is determined whether or not the application section has been updated (step S611). If not, the process proceeds to step S614. If there is, the application portion is written (step S611). S61
2). Further, in this writing process, it is determined whether or not an error has occurred (step S613). If an error has occurred, the writing mode of the first memory is released (step S615), and the process is interrupted. If it is determined that there is no error, the write mode of the first memory is released (step S614), and normal termination processing is performed. In both normal and error cases in FIG. 6,
Finally, the write code of the first memory is released.

FIG. 7 is a diagram showing an example of a data structure obtained by combining the BOOT update data dedicated to the first and second nonvolatile memories. The update data 701 includes a BOOT update data section 702 dedicated to the second nonvolatile memory section and a BOOT update data section 70 dedicated to the first nonvolatile memory section.
3 and an application update data section 704. The second non-volatile memory section dedicated data section 702 includes a Header section 705 indicating information about data,
S unit 706, LCD driver 707 as an extended function,
Extended memory driver 708, Utility unit 709
It is composed of

The first non-volatile memory unit-dedicated data unit 703 includes a header representing information about data.
A unit 710 and data 711 in which a basic OS and an extended function unit are integrated. In addition, the application update data unit 704 includes H indicating information about data.
FIG. 8 is a flowchart showing a procedure of a first non-volatile memory update process (code update process A) using the data shown in FIG. 7, which is composed of an header section 712 and an update data section 713. is there.

First, the first nonvolatile memory is set to a writable mode (step S801), and all the BOOT-related codes are written (step S802). At the time of this writing, it is determined whether or not an error has occurred (step S
803) If it is determined that a write error has occurred, the write mode of the first memory is released (step S807), and the process is interrupted.

If there is no error, the application section is written (step S804). At this time, it is determined whether or not a write error has occurred (step S805). Then, the write mode of the first memory is released (step S807), and the process is interrupted. On the other hand, when there is no error, the write mode of the first memory is released (step S806), and the normal end processing is performed. In both normal and error cases, the memory write mode is released.
As described above, for all of the data shown in FIGS. 5 and 7, by receiving all update data in one transfer and automatically determining the data, a configuration is possible in which the program can be updated efficiently. Has become.

FIG. 9 is a flowchart showing a processing procedure when the power is turned on in the program update control method of the present invention. After the power is turned on, first, the information of the switch 10 inputted to the memory controller 2 in FIG. 1 is looked at (step S901), and if it is on the A side, the program is started from the address 0x000 in the first nonvolatile memory. Is started (step S902). Next, the BOOT code and the OS are activated (step S903), and the application is further activated (step S904). Subsequent processing is the same processing operation as in FIG.

On the other hand, if the switch is on the B side in step S901, the program is started from the address 0x10000 in the second nonvolatile memory (step S905), and then the BOOT code and code update unit are started. (Step S906). Subsequent processing is the same processing operation as in FIG. As described above, even if a failure occurs in the first nonvolatile memory for some reason, it is possible to reliably start up the first nonvolatile memory.

[0034]

According to the present invention, by writing the BOOT code in the OTP area of the second nonvolatile memory, even if a problem occurs at the time of updating the first nonvolatile memory, the second nonvolatile memory can be used. Restart can be performed more reliably than the OTP area. Furthermore, according to the present invention, the optimal BO
By automatically writing the OT code, the reliability of the restart can be improved and the memory size can be reduced.

Further, according to the present invention, when a problem occurs at the time of updating the first non-volatile memory, it is possible to reliably start up from the second non-volatile memory and avoid the risk of becoming unusable as a system. . Further, according to the present invention, both memory data can be transmitted and received at one time,
The updating procedure is also simplified, and it is possible to prevent occurrence of a mistake. Further, according to the present invention, when updating has already been performed, updating is not performed, and unnecessary processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an apparatus for implementing a program update control method according to the present invention.

FIG. 2 is a diagram illustrating an example of a memory configuration in first and second nonvolatile memories.

FIG. 3 is a flowchart illustrating a procedure of a program update in the program update control method of the present invention.

FIG. 4 is a flowchart showing a detailed procedure of a process (code update process B) of writing an optimal BOOT code into a second nonvolatile memory (OTP) in step S307 of FIG. 3;

FIG. 5 is a diagram illustrating an example of a configuration of update data received in step S304 of FIG. 3;

FIG. 6 is a flowchart illustrating a detailed procedure of a process (code update process A) of writing an optimal BOOT code into the first nonvolatile memory in step S308 of FIG. 3;

FIG. 7: BOOT dedicated to first and second nonvolatile memories
FIG. 4 is a diagram showing an example of a data configuration in which update data for use is combined.

8 is a flowchart illustrating a procedure of a first non-volatile memory update process (code update process A) using the data illustrated in FIG. 7;

FIG. 9 is a flowchart showing a processing procedure when the power is turned on in the program update control method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... memory controller, 3 ... 1st non-volatile memory, 4 ... 2nd non-volatile memory (OTP), 5
... DRAM for standard and expansion, 6 ... I / O section, 7 ... Key input section, 8 ... Parallel I / F, 9 ... LCD section for display, 10
… Switch to select memory at startup.

Claims (7)

[Claims] 1. A rewritable first non-volatile memory and a once-writable second non-volatile memory (O
In a system equipped with a TP area, when updating the BOOT code installed in the first nonvolatile memory, an optimal BOOT for the second nonvolatile memory is used.
A program update control method, comprising a program for updating a first nonvolatile memory after writing a code for T. 2. An optimal BO for the second nonvolatile memory.
2. The program update control method according to claim 1, wherein when writing the OT code, the system configuration at that time is automatically determined, and the optimum BOOT code is selectively written. 3. The BOOT code selected at the time of startup is
2. The program update control method according to claim 1, wherein the first nonvolatile memory or the second nonvolatile memory is switchable and writable by an external signal. 4. An optimal BO for the second nonvolatile memory
2. The program update control method according to claim 1, wherein if a problem occurs in the middle of writing the OT code, the update processing of the first nonvolatile memory is not performed. 5. When updating a program, the update data for the first non-volatile memory and the update data for the second non-volatile memory are received together, and automatically determined from the data structure of the update data. 2. The program update control method according to claim 1, wherein the data is written into a memory of the program. 6. When a program is updated, the BOOT code update data and the application update data are received together, and automatically determined from the data structure of the update data.
The BOOT code update data includes the first and second codes.
2. The program update control method according to claim 1, wherein the non-volatile memory is updated, and the application update data updates only the first non-volatile memory. 7. When updating the first nonvolatile memory,
2. The program update control method according to claim 1, wherein the updating of the second nonvolatile memory is not performed when the second nonvolatile memory has already been updated.