JP2002341833A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a planar display device in which a narrow frame is realized without increasing the occupancy area of a peripheral driving circuit. SOLUTION: Buffers that constitute the peripheral driving circuit include a plurality of inverters. Odd numbered inverters are load MOS type inverters and even numbered inverters are CMOS type inverters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly to a flat panel display integrated with a driving circuit in which a driving circuit is integrally formed on a substrate on which a pixel TFT is formed.

[0002]

2. Description of the Related Art A flat display device using a plasma, a light emitting diode, a liquid crystal or the like can make a display portion thinner, and the demand for the display device such as office equipment and a computer or a special display device is increasing. ing.

In particular, amorphous amorphous silicon (a-Si) or polycrystalline polysilicon (p-S
i) Thin film transistor (TFT; Thin F)
2. Description of the Related Art A flat display device in which an image transistor (ilm transistor) is arranged as a pixel switching element in a matrix and connected to a display element to perform display has a high display quality and low power consumption, and thus has been actively developed.

[0004] In particular, a TFT using p-Si is a-S
The mobility is about 10 to 100 times higher than that of a TFT using i. Therefore, taking advantage of the advantage, not only can the pixel be used as a pixel switching element, but also the peripheral driving circuit can be formed integrally with the pixel switching element on the same substrate. This makes it possible to realize a low-cost and high-performance flat display device.

[0005] Among the peripheral driving circuits, some TFTs apply a high voltage of 10 V or more to a drain portion from a voltage source. Taking a buffer arranged in the peripheral drive circuit as an example, a plurality of CMOS inverters each formed by a pair of TFTs having different conductivity types as shown in FIG. 6 are formed. When a relatively large drain voltage is applied to the TFT, an electric field concentrates on the junction between the channel region and the source region of the semiconductor layer and the junction between the channel region and the drain region. Electrons and hot holes are likely to occur.

Since these hot electrons and hot holes have extremely high energy, the quality of crystals at the interface between the gate insulating film and the channel region and between the channel region and the source / drain region is deteriorated, and the threshold voltage of the TFT is reduced. And hinders the stable operation of the TFT, for example, by reducing the mobility or decreasing the mobility. In addition, avalanche breakdown in which the characteristic deterioration progresses is caused, and the reliability and the durability of the TFT are deteriorated, such as the gate insulating film is broken or the source / drain regions are broken.

[0007] This decrease in reliability is caused by the fact that, of the TFTs constituting the peripheral drive circuit, the n-type TFT is turned off when the source is turned off.
Appears remarkably when a large voltage is applied between the drains. In particular, the influence on the mobility in the linear region (triode region) is large, and the mobility decreases with time, as shown in FIG.

Conventionally, in order to cope with the decrease in mobility of the n-type TFT, an LDD (Lightly Dopant) is added to the TFT.
An ed Drain) structure, an offset structure, a multi-gate structure, a structure in which the gate length is increased, and the like are employed, and measures are taken to reduce the concentration of the electric field so that the TFT characteristics hardly deteriorate.

[0009]

However, when these structures are adopted, the element area of the TFT is correspondingly increased, and the frame of the flat display device is widened.

In addition, since the TFT used in the drive circuit has a large number of elements, the manufacturing process becomes complicated, so that an operation failure due to a processing defect is likely to occur, which causes a reduction in yield.

Therefore, in the present invention, in view of the above technical problems,
It is an object of the present invention to provide a flat display device that achieves a narrow frame without increasing a TFT element area.

[0012]

A plurality of signal lines arranged on an insulating substrate, a plurality of scanning lines arranged substantially orthogonal to the signal lines, and a vicinity of each intersection of the signal lines and the scanning lines. And a pixel electrode connected via the switching element, a counter electrode disposed to face the pixel electrode, a light modulation layer held between these electrodes, the signal line and the A driving circuit for driving a scanning line, wherein the driving circuit includes a buffer including at least two or more inverters, and the buffer includes a load MOS inverter and a CM.
It is characterized in that OS type inverters are arranged alternately.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings, taking a liquid crystal display device as an example. FIG.
FIG. 2A is a schematic plan view of the liquid crystal display device, and FIG. 2B is a partially schematic enlarged view of the array substrate of FIG.
2 shows a partially enlarged view of a driving circuit of the liquid crystal display device.

As shown in FIG. 1, a plurality of signal lines 101 arranged on a transparent insulating substrate 100 are electrically insulated from each other and a plurality of scanning lines arranged substantially orthogonal to the signal lines 101. A line 102, a pixel TFT serving as a switching element disposed near these intersections,
And a display pixel P connected to the pixel. The display pixel P has a pixel electrode 10 electrically connected to the pixel TFT.
3, a counter electrode 104 disposed to face the pixel electrode, and a liquid crystal material held as a light modulation layer 105 between the electrodes.

The pixel TFT is formed using p-Si, and a signal line driving circuit 110 for driving the signal line 101 and a scanning line driving circuit 120 for driving the scanning line 102 include:
It is formed simultaneously on the same substrate as the substrate on which the pixel TFT is formed.

The liquid crystal display device 1 according to this embodiment has a V
This is a 10.4 type XGA liquid crystal display device driven by line inversion, in which four divided areas of the screen are simultaneously driven. Each area is divided into 32 signal lines with 24 signal lines as one block, and is sequentially driven in block units.

Since the above-described area obtained by dividing the screen into four parts operates in the same manner, one of these areas will be described in detail below.

As shown in FIG. 1B, the signal line drive circuit 110 includes a video bus 115 for transmitting an analog video signal supplied from an external drive circuit, and a plurality of flip-flop circuits FFn (n = 0 to 0). 32), and a polarity selection circuit 112 which is arranged corresponding to each stage of the flip-flop circuit FFn and controls one signal line to select two video bus lines having different polarities to be described later. , An adjacent flip-flop circuit FF
a pulse cut circuit 113 for outputting a signal from which an overlapped portion of the output of n has been removed to an output circuit;
An output circuit 114 for outputting a control signal for controlling the timing of sampling of the analog video signal based on the signal input from the third circuit 3, and a signal for electrically connecting the video bus 115 and the signal line based on the output of the output circuit 114 And a line selection circuit 116.

As shown in FIG. 2, the video bus 115 has a positive video bus line for transmitting a positive analog video signal with respect to a reference voltage, and a negative video bus for transmitting a negative analog video signal. And a line. The video bus 115 includes a number of video bus lines corresponding to one block. In this example, 12 video bus lines each having a positive polarity and a negative polarity are provided, and a total of 24 video bus lines are arranged in one area. .

The signal line selection circuit 116 has 32 stages of analog switch circuits ASWn corresponding to the signal lines of each block.
(N = 1 to 32) and are configured to sequentially select signal lines for each block. That is, a pair of TFTs of different conductivity types and a p-type TFT PSWm (m = 1,
2) and an n-type TFT NSWm are arranged, and twelve sets of analog switches constitute one stage of the analog switch circuit ASWn with two adjacent signal lines as one set. The twelve analog switches are connected to corresponding positive and negative video bus lines. That is,
One set of analog switches of each block is connected to one set of video bus lines for positive polarity and negative polarity. Each TFT of each analog switch is connected to the same video bus line for each conductivity type.
PSW1 and PSW2 are connected to the same video bus line for positive polarity, and n-type TFTs NSW1 and NSW2 are connected to the same video bus line for negative polarity. Furthermore, the control terminal (gate) of the TFT constituting each analog switch
In the 1/32 horizontal display period, the p-type TFT PSW1 connected to one signal line and the n-type TFT NSW2 connected to the other signal line are simultaneously in the ON state, and n is connected to one signal line. The type TFT NSW1 and the p-type TFT PSW2 connected to the other signal line are controlled to be in the OFF state, and the polarity inversion of the voltage applied to each signal line can be realized for each frame.

By using such an analog switch, the number of video bus lines can be halved.

Incidentally, these drive circuits 110 and 120
Has a large number of inverters, and includes a buffer composed of a plurality of stages of inverters. For example, each of the buffer circuits BU of 32 blocks constituting the output circuit 114
Fn is provided with a plurality of buffers composed of even-numbered inverters and a plurality of buffers composed of odd-numbered inverters.

More specifically, the analog switch p
The buffer connected to the gate of the type TFT PSWm is composed of even-numbered stages, and the buffer connected to the gate of the n-type TFT NSWm is composed of odd-numbered stages of inverters. As an example, FIG. 2 illustrates a buffer circuit BUFn including a buffer having three stages of inverters and a buffer having four stages of inverters.

FIG. 3A shows a buffer in which inverters are connected in even-numbered stages, in this case, four stages. FIG. 3B shows signal waveforms at various parts in FIG. 3A.

As shown in FIG. 3A, this buffer is composed of a load MOS type inverter comprising a resistor and a p-type TFT, a p-type TFT and an n-type TFT on the same substrate as the substrate on which the pixel TFT is formed. A CMOS type inverter composed of TFTs. The odd-numbered stages are load MOS type inverters and the even-numbered stages are CMOS type inverters.
The load MOS type inverter and the CMOS type inverter are connected alternately. Here, the signal input to the first-stage inverter is a High level during a period of selecting one block of signal lines in one horizontal scanning period, and a period of selecting a signal line of another block in one horizontal scanning period. Is a signal for outputting a low level. As shown in FIG. 3B, a signal in which the period during which the Low level is output is longer than the period in which the High level is output, and in the present embodiment, a signal having a duty ratio of 1:31 is used. Is entered.

In the present embodiment, a display device driven for each of a plurality of signal lines (blocks) has been described. However, in a display device driven sequentially for each signal line, for example, the entire screen of the present embodiment is used. Are sequentially driven corresponding to the signal lines in each of the four divided regions, the duty ratio is 1:
A signal such as 767 is input.

Although the duty ratio for the data transfer period in one horizontal scanning period has been described, a signal whose Low level period is longer than the High level period is also output for the blanking period.

As described above, in a device in which a signal whose Low-level period is longer than the High-level period is input to the first-stage inverter in each horizontal scanning period, at least the odd-numbered-stage inverter is constituted by the load MOS type inverter. . The resistor of the load MOS type inverter is formed by partially providing a p-Si film having a resistance value of about 1 × 10 ⁷ Ω and lightly doped with an N-type impurity to a wiring.

When a high-level signal is input to the first-stage inverter (FIG. 3), the p-type T
The FT is turned on, and VDD is input to the second-stage inverter as a high-level signal (FIG. 3).
Since the second-stage inverter is a CMOS type inverter, the n-type TFT is in the ON state, and the ground voltage is Low.
This signal is input to the third-stage inverter as a level signal (FIG. 3), and thereafter, this operation is repeated according to the number of inverter stages. As shown in FIG.
If the operation is performed immediately after the output of the type inverter, a state in which the signal waveform is recovered can be used.

As described above, by arranging the resistor at the position of the n-type TFT of the inverter in which the characteristic deterioration is remarkable, it is possible to achieve an inverter with a small characteristic change with time. In addition, by applying this to a flat panel display device, it is possible to suppress malfunction.

Further, since the plurality of inverters constituting the buffer are configured so that the load MOS type inverter and the CMOS type inverter are alternately arranged, the number of TFTs can be reduced, resulting in defective TFT processing. Lowering of the production yield can be suppressed.

In the load-type inverter, since a resistor is disposed instead of the n-type TFT, the area occupied by the element can be reduced, so that every other inverter constituting a buffer is a load-type inverter. Accordingly, it is possible to achieve a narrow frame of the flat display device.

Further, in the buffer formed by the even-numbered inverters, the signal from the final-stage inverter is taken out from the CMOS inverter, so that the signal can be taken out with suppressed signal waveform distortion. Become.

In the above embodiment, the resistor and p
In the above description, the load MOS type inverter is constituted by the TFTs. However, this resistor uses an n-type TFT (W / L
(= 20/11 μm). For example, when an n-type TFT that is not a conventional structure (LDD structure, offset structure, etc) for suppressing characteristic deterioration as shown in FIG. 4 is in an OFF state, a large voltage of about 10 V is applied between a source and a drain. The characteristics are intentionally deteriorated with the lapse of time and can be regarded as a resistor. FIG. 5 shows the IV characteristics of the n-type TFT before and after the characteristic deterioration. When the resistance of the n-type TFT of the load MOS inverter is deteriorated and used as a resistor, the resistance value is approximately 1 × 10 ⁷ Ω, and the n-type TF of the CMOS inverter formed at the next stage of the load MOS inverter
It can be regarded as a resistor having a resistance 200 times higher than the resistance of T (W / L = 20/11 μm).

By forming a load MOS type inverter using an n-type TFT whose resistance has been intentionally increased by utilizing the characteristic deterioration of the n-type TFT as a resistor as described above, for example, an LD
A step for forming D becomes unnecessary, and a reduction in manufacturing yield can be suppressed. In addition, a flat display device without increasing the area occupied by the TFT can be achieved.

In the above embodiment, a liquid crystal display device using a liquid crystal material as the light modulation layer has been described as an example.
The present invention is not limited to this, and can be applied to all flat display devices such as an organic EL display device having an organic light-emitting body in a light modulation layer.

[0037]

According to the present invention, it is possible to suppress an increase in the TFT area and achieve a narrow frame of the flat display device. In addition, the manufacturing yield can be improved without increasing the number of TFT manufacturing steps.

[Brief description of the drawings]

FIG. 1A is a schematic plan view of a liquid crystal display device according to an embodiment of the present invention, and FIG. 1B is a partially enlarged schematic diagram.

FIG. 2 is a partially enlarged plan view of a liquid crystal display device according to one embodiment of the present invention.

FIG. 3A is a diagram showing a part of a driving circuit according to an embodiment of the present invention, and FIG. 3B is a diagram showing a signal waveform thereof.

FIG. 4 is a diagram showing a resistor according to one embodiment of the present invention.

FIG. 5 is an IV characteristic diagram of an n-type TFT constituting a buffer according to one embodiment of the present invention.

FIG. 6 is a partial circuit diagram showing a conventional drive circuit.

FIG. 7 is a diagram showing characteristic deterioration of a conventional n-type TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Flat panel display 100 ... Insulating substrate 101 ... Signal line 102 ... Scanning line 103 ... Pixel electrode 104 ... Counter electrode 105 ... Light modulation layer 114 ... Buffer circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680G 5G435 H01L 29/786 H01L 29/78 614 F Term (Reference) 2H092 GA59 JA25 JB22 JB31 KA03 KA04 NA22 NA24 NA29 5C006 BB16 BC11 BC20 BF33 BF34 EB05 5C080 AA10 BB05 DD22 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 5C094 AA15 AA42 BA43 CA19 DB01 DB05 EA04 EA07 A04 EB07 A04 EB07 A04 EB07 A02 EB07

Claims (6)

[Claims] A plurality of signal lines disposed on an insulating substrate;
A plurality of scanning lines arranged substantially orthogonal to the signal line, a switching element arranged near each intersection of the signal line and the scanning line, and a pixel electrode connected via the switching element; A flat display device comprising: a counter electrode disposed to face a pixel electrode; a light modulation layer held between the electrodes; and a drive circuit for driving the signal line and the scan line. Is at least 2
A flat display device comprising a buffer having the above inverter, wherein the buffer is configured by alternately arranging load MOS type inverters and CMOS type inverters. 2. The method according to claim 1, wherein the load MOS type inverter is a PMOS.
The flat display device according to claim 1, wherein the flat display device is a type inverter. 3. A plurality of signal lines arranged on an insulating substrate;
A plurality of scanning lines arranged substantially orthogonal to the signal line, a switching element arranged near each intersection of the signal line and the scanning line, and a pixel electrode connected via the switching element; A flat display device comprising: a counter electrode disposed to face a pixel electrode; a light modulation layer held between the electrodes; and a drive circuit for driving the signal line and the scan line. Is at least 2
In each of the horizontal scanning periods, the signal input to the first-stage inverter is longer than the period during which the Low signal is input and the period during which the High signal is input. A flat panel display device comprising a MOS inverter and a CMOS inverter at an even-numbered stage. 4. The load MOS type inverter comprises a resistor and a p-type TFT.
A flat display device as described in the above. 5. The flat panel display device according to claim 3, wherein said buffer comprises an even number of inverters. 6. The switching element and the p-type TF
The flat display device according to claim 4, wherein T is a polycrystalline silicon TFT.