JP2002340770A - Probe of scanning probe microscope having channel structure of field effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the probe of a scanning probe microscope(SPM) having the channel structure of a field effect transistor formed at the tip thereof, and its fabricating method. SOLUTION: A probe structure is formed by etching a semiconductor substrate, e.g. a single crystal silicon wafer, and the inclining etched face at the tip thereof is doped to form a source, a channel and a drain. Firstly, it can serve as a probe for reading out charges of a sample being measured. Secondly, peripheral apparatus can be minimized in size because the quantity of charges can be converted directly into a value of current (voltage). It means that a microprobe or a high performance probe can be realized. Thirdly, charges can be collected and measured by means of that probe using a charge trap technology, for example. Fourthly, charges can be measured at a relatively far distance as compared with an existing SPM and the sensitivity is enhanced when the charges are measured at a short distance. Fifthly, it is applicable to an apparatus for determining the three-dimensional surface shape of a sample because of a fact that the strength of electric field depends on the distance between a chip and a sample.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor at the tip of a chip.
channel; FET channel) scanning probe microscop
e; SPM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Scanning probe microscopes (SPMs) have been developed as various types of microscopes capable of measuring various physical quantities using a method of scanning a probe.

The basic structure of an SPM has a very sharp tip (with a radius of curvature of 10 nm or less), a tip having a tip, a scanner for scanning the tip on a sample, and controlling and receiving these signals to process them. It is composed of a control and information processing system. Although the SPM has evolved in various forms, the principle that the probe operates according to the physical quantity to be measured is slightly different, and the STM (scanning) that uses the current flowing due to the voltage difference between the tip and the sample tunneling
microscope), AFM (atomic force microscope) using force acting between various atoms between tip and sample, MFM (magnetic for force) using force between sample magnetic field and magnetized tip
ce microscope), SNOM (scanning near-field optical microscop) with improved resolution limit due to wavelength of visible light
e), EFM (electrosta
Technologies such as tic force microscope) were developed. There have also been many developments in the type of chip associated with the sample and its precision in fabrication. The properties of substances that can be measured by SPM developed based on various principles are not limited to the surface shape level of basic applications, but also the coefficient of friction, thermal conductivity, magnetic domain (magnetic dope)
main), ferroelectric domain, potential difference,
Fine measurement of various physical properties such as electrochemical properties has become possible.

FIG. 1 is a schematic block diagram of a disk device using an existing SPM probe. The disk device using the SPM probe includes a disk 8 including a large circular substrate, an electrode layer laminated on the substrate, and a ferroelectric layer laminated on the electrode layer, and the ferroelectric layer. A microchip for reading information while reciprocating in a section corresponding to 1/4 of the optical wavelength in a direction perpendicular to the disk surface according to the polarity of the dielectric polarization, and a reflection for reflecting light. Head 9 comprising means, said head 9
And an optical system 100 for detecting the recorded information by recognizing a difference in an optical path due to the reciprocal movement in the vertical direction.

The disk 8 has a circular substrate 8a on which an electrode layer 8b and a ferroelectric layer 8c on which information is recorded by dielectric polarization are sequentially laminated. In the head 9 composed of an SPM probe, information is recorded by forming dielectric polarization directly on the ferroelectric layer 8c, and the polarity of this dielectric polarization reduces the optical wavelength to １ of the optical wavelength in the direction perpendicular to the disk surface. A microchip 9a for reading information while reciprocating in a corresponding section, a reflector 9b for reflecting light, and the microchip 9a and the reflector 9b
Is provided. And optical system 1
Reference numeral 00 denotes a laser diode 1 as a light source, a collimating lens 2 for converting light emitted from the light source 1 into parallel light, and a beam splitter 3 for passing the parallel light as it is and separating the light reflected on the disk surface. An objective lens 5 for focusing parallel light to a track on the disk surface up to the diffraction limit, a focusing lens 6 for focusing reflected light, and a photodetector 7 for converting the focused reflected light into an electric signal.

[0006] The operating principle of the disk device having such a configuration is as follows. A ferroelectric thin film is deposited on the electrode plate,
By polarizing microscopic parts with microtip electrodes,
The difference between the polarized part and the non-polarized or non-polarized part can be caused by moving the microchip to which a certain voltage is applied. Can be distinguished from each other. Therefore, different electrostatic forces are applied to microchips having heads to which a constant voltage is applied according to the amount of polarization of the disk surface, and if these electrostatic forces raise or lower the microchip by λ / 4, λ / 2 Only the light having the optical path difference of the light is separated from the beam splitter 3 and detected by the photodetector 7.

FIG. 2 is a schematic block diagram of an apparatus for reading the surface shape (TOPOLOGY) of an object using an existing SPM probe. As shown, when the sample 21 is moved by the x, y, z scanner 22 controlled by the controller 25 while the cantilever probe 19 is vibrated by the piezo element 20, the sharp tip 19a of the cantilever probe 19 is obtained. Scans along the surface shape of the sample 20. Therefore, the body of the cantilever probe 19 reflects the laser beam emitted from the laser light source 23 to the photodetector 24 while moving up and down according to the surface shape of the sample.
By detecting the quantity of the reflected light reflected in this manner by an electric signal, the surface shape of the test target can be displayed on the display 27.
To reproduce.

As can be seen from the above examples, the SPM technique for measuring the phenomenon acting between the probe and the sample using a physical instrument and a laser uses the distance between the tip of the probe tip and the sample. Must be very close and the tip of the tip must be very sharp. Such techniques have many difficulties in control, such as being very dependent on the flatness of the substrate.
Also, since the size of the entire system is large, it is a decisive problem when manufacturing a microminiature hard disk or the like.

[0009]

SUMMARY OF THE INVENTION Accordingly, the technical problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and has a simple structure and a peripheral device. It is an object of the present invention to provide a scanning probe microscope probe in which a channel of a field effect transistor capable of easily detecting a force acting between a tip and a sample.

Another technical problem to be solved by the present invention is to provide a method of manufacturing the scanning probe microscope probe.

[0011]

In order to achieve the above-mentioned technical object, the present invention provides a rod-shaped probe made of a semiconductor and a first inclined surface at the center of a V-shaped tip at the tip of the probe.
A channel region formed by doping an impurity; and a source and a drain formed by doping a second impurity on both side slopes of a V-shaped tip at the tip of the probe with the channel region as a center. The present invention provides a scanning probe microscope probe in which a channel of a field effect transistor is formed.

According to another aspect of the present invention, a single crystal semiconductor substrate is etched along a crystal plane to form a tip, and a V-shaped tip at the tip of the probe is provided. Forming a channel region by doping a first impurity on a slope including a central point of the probe, and doping a source and a drain by doping a second impurity on both slopes of a V-shaped tip at the tip of the probe. Forming a probe of a scanning probe microscope in which a channel of a field effect transistor is formed.

In the present invention, in the step described in (1), the single crystal semiconductor substrate is a single crystal silicon substrate having a (100) plane, and both side slopes on which the source and the drain are formed are (111) planes. It is desirable to etch so that

According to the present invention, there is provided a rod-shaped probe formed by etching a (1) (100) plane single crystal semiconductor substrate along a crystal plane in order to achieve the other technical problems. Forming the tip portion into a V-shape having a first angle in a plane, and simultaneously etching the V-shape so that both side surfaces thereof have a (111) surface; and (2) a tip portion of the probe. Forming source and drain regions by doping a first impurity on both side inclined surfaces of the V-shaped chip; and (3) forming a center point of the inclined surface on which the source and drain regions doped with the first impurity are formed. Only the tip of the inclined surface is etched so that the head forms a second angle larger than the first angle so that the first impurity is removed.
Forming a channel doped with an impurity, the method comprising: fabricating a scanning probe microscope probe having a channel formed in a field effect transistor.

In the present invention, it is preferable that the first angle is 90 ° and the second angle is 136 °.

[0016]

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, a probe of a scanning probe microscope having a channel of a field effect transistor according to an embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

FIG. 3 is a perspective view showing a schematic structure of an SPM probe in which a channel of a field effect transistor according to the present invention is formed. As shown, the semiconductor substrate 200
Is etched to form a probe 210 structure, and the etched surface is doped to form a source 211, a channel 212, and a drain 213. In the drawing, reference numeral 220 denotes an electrode pad connected to the source 220 and the drain 213, respectively.

As described above, the FET in which the distance between the source 211 and the drain 213 is adjusted at the tip of the tip of the probe 210
When the channel structure is formed, the channel of the transistor at the tip of such a chip can detect a plurality of regions having different charge densities distributed on the sample and can be used as a device for collecting charges. A sample in which electric charges are collected in a minute area can be used for a storage device. In addition, the degree to which charges are collected on a specific sample can be measured.

The structure in which the channel of the FET is formed at the tip of the chip is based on the principle of a MOS transistor which responds sensitively to the voltage or charge applied to the gate, as shown in FIG. Simple circuit configuration,
There is an advantage that the charge amount between the chip and the sample surface can be directly converted into a current. That is, the existing SPM system shown in FIG. 1 or FIG. 2 requires an optical system and a complicated circuit system in addition to the cantilever, and the entire system is very large and requires high manufacturing costs. The tip of the probe for an SPM device as described above has a function of sufficiently sensing the physical state of the sample by simply connecting it to a simple signal amplifier as shown in FIG. This is a sensor that outputs an electric signal directly to the tip of the chip (FET channel structure)
This is because the output value can be determined immediately by amplifying the electric signal output from the sensor. In addition, the overall system can be downsized, which can be an effective technology when manufacturing a micro data storage device. In particular, when this device is used, when collecting charges on a sample, it is a great advantage that the amount can be adjusted only to a necessary amount. With this, it is also possible to inform the hard disk of the extent to which information is lost.

FIGS. 5A and 5B are SEM photographs of the SPM probe of the present invention being actually manufactured on a silicon wafer, respectively, wherein a structure for forming a channel of a transistor is formed at the tip of the probe. Indicates a state in which FIG. 5C shows an SPM probe having a completed channel structure. There may be various manufacturing processes for forming the channel structure of the FET at the tip of the probe. For example, after first doping an impurity into a region where a channel is formed, and then doping impurities forming a source and a drain on both side slopes excluding the region, or doping impurities forming a source and a drain, There may be a method of etching the central point to expose the channel region.

If the second method is applied, first, (100)
Using a surface silicon wafer, it is precisely etched so that a (111) plane appears on both inclined surfaces of the tip portion of the tip having a probe structure, and a source and a drain are formed on the inclined surface. Doping with one impurity. At this time,
The angle at which the (111) plane and the (111) plane meet is maintained at 90 ° on a plane viewed from above the probe. In the subsequent etching process, the (211) surface of the pointed portion is exposed, and the probe is etched so as to maintain 136 ° on a plane viewed from above, thereby removing the first impurity at the central pointed portion. Then, the channel region doped with the second impurity is formed, and at the same time, the source and the drain are determined, thereby completing the channel structure of the FET. At this time, whether the first and second impurities to be doped are n-type or p-type is determined as PNP-type or NPN-type FET depending on the type. This is the same as a general FET. 6A to 6C show the operation principle of the channel of the MOS transistor formed at the tip of the probe.

First, as shown in FIG.
If the concentration of the charge is made different and the chip having the FET channel structure passes over the sample 300, the sample 300
Depending on the concentration of electric charge 301 trapped on the surface of
The intensity of the electric field applied to the channel structure of the MOS transistor changes. MOS changes due to such electric field strength changes
Transistor channel structure 211, 212, 213
The channel width 212 formed in the source 21 is changed.
1 and the drain 213 have different current amounts. FIG. 6B shows NP
FIG. 6C shows the operation principle of the channel structure of the N-type FET.
The operating principle of the channel structure of the P-type FET is shown.

The cantilever probe equipped with the channel structure of the MOS transistor operating as described above can be applied to various fields such as a field of reading and writing of an HDD and a field of grasping the surface shape of a semiconductor thin film. In the case of an HDD, it is based on detecting charges trapped on the surface of the HDD defined as 0 and 1. When reading or writing, FET (Field Em
Using the principle of mision transistor, the amount of current flowing from the drain through the source changes depending on the amount of charge collected on the surface of the HDD. For example, if no electric charge is collected on the surface of the hard disk, no current flows from the drain to the source because the phenomenon is the same as that of applying no gate voltage to the FET. If there is a region where charges are collected on the surface of the HDD, the gate voltage of the FET is turned on, a channel between the drain and the source is formed by the gate voltage, and a current flows. Therefore, the information amount of the HDD rotating at high speed is
It can be measured with a cantilever probe that performs ET operation.

In some cases, the method is applied to measuring the surface morphology of a semiconductor thin film. In other words, while maintaining a constant voltage applied to the sample with a cantilever probe with a built-in FET channel structure, while changing the distance between the sample to be measured and the tip of the chip, VD
If the characteristics of the S-IDS are derived, it is understood from the obtained characteristics that the output characteristics and the sensing characteristics of the FET chip change depending on the distance. As described above, if the cantilever probe is scanned with a constant voltage applied to the sample, the intensity of the electric field applied to the FET channel structure of the probe changes due to the unevenness of the sample surface. The value changes. By using this, the surface shape of the semiconductor thin film can be understood by enlarging it.

<First Experimental Example> The current flow depending on the concentration of trapped charges of a sample was measured using a chip having a FET channel structure. While keeping the distance between the sample to be measured and the tip of the tip constant,
A constant gate voltage was applied to the sample. FIG. 7 shows the results of measuring drain-source current (IDS) values according to changes in drain-source voltage (VDS) at various gate voltage levels. The lowermost curve in such a VDS-IDS characteristic curve is a state in which no voltage is applied to the sample, that is,
When there is no charge and a voltage is applied to the sample while changing it at -5V intervals, a channel is formed between the drain and source due to the effect of the charge collected on the sample due to the characteristics of the FET. Shows that the current value changes.

Further, as shown in FIG. 8, the output characteristics and the sensing characteristics of the FET chip according to the concentration of trapped charges were found by deriving the characteristics of the VDS-IDS depending on the gate voltage change. That is, FIG. 8 shows the voltage applied to the sample while maintaining the distance between the sample and the chip constant and maintaining a constant VDS, that is, the ID based on the charge concentration.
It is a VG-IDS curve showing the change of S. As the voltage applied to the sample increases, that is, as the concentration of the charge in the sample decreases (closer to zero), the amount of the IDS sharply decreases. Further, the characteristic shows that the voltage applied to the sample decreases exponentially as the voltage applied to the sample decreases, and the characteristic shows that the saturation occurs at a certain stage. Information can be read from or written to the hard disk using such characteristics.

<Second Experimental Example> The current flow depending on the distance between the chip and the sample was measured with a cantilever probe having a FET channel structure. The distance between the tip and the sample is about 1
The characteristics of VDS-IDS were measured while changing the VG value while maintaining the value at m. The result is as shown in FIG. 7 shown in the experimental example.

FIG. 9 is a graph obtained by measuring the characteristics of VDS-IDS while changing the VG value while maintaining the distance between the chip and the sample at about 2 m. This graph is much affected by noise when compared with the graph of FIG. 7, and although the overall tendency is the same, it is output.
It can be seen that the value of IDS has greatly decreased. Thus, by listing the IDS measured using the X and Y coordinates by scanning together with the output characteristic change due to the distance between the chip and the sample, a three-dimensional sample surface form can be configured.
The field of application of the chip equipped with this FET to the SPM device is the measurement of sample morphology. Depending on the surface height of the sample
It has the same effect as changing the gate thickness in the MOSFET.
That is, since the IDS changes depending on the distance between the chip and the sample, if the constant VDS and VG are maintained, the surface morphology of the sample can be obtained while scanning the sample. The surface morphology of the sample can be obtained in three dimensions using the X and Y coordinates of the scanning and the IDS value at the scanning coordinates as the Z axis.

[0029]

As described above, the probe of the scanning probe microscope in which the channel structure of the field effect transistor according to the present invention is formed is formed by etching a semiconductor substrate such as a single crystal silicon wafer. By having a structure in which a source, a channel, and a drain are formed by doping the inclined etching surface of the previous chip portion, the following advantages are obtained.

First, it can function as a probe capable of reading out charges on a measurement sample.

Second, it is possible to directly convert a charge amount into a current (voltage) value, so that peripheral equipment can be minimized.
This means that microminiaturization and high performance can be achieved.

Third, charges can be collected at the probe using techniques such as charge trapping, and can also be measured at the same time.

Fourth, the electric charge can be measured at a relatively long distance as compared with the existing SPM, and when the measurement is performed in a close proximity, the sensitivity is improved and improved.

Fifth, the present invention can be applied to an apparatus for obtaining a three-dimensional surface morphology of a sample based on the fact that the electric field intensity changes depending on the distance between the chip and the sample.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a disk device using an existing SPM probe.

FIG. 2 is a schematic block diagram of an apparatus for reading a surface shape of an object using an existing SPM probe.

FIG. 3 is a perspective view showing a schematic structure of an SPM probe in which a channel of a field effect transistor according to the present invention is formed.

FIG. 4 is a schematic configuration diagram of an SPM system including an SPM probe in which a channel of the field effect transistor of FIG. 3 is formed.

5A to 5C are SEM photographs of the SPM probe in which the channel of the field-effect transistor of FIG. 3 is actually manufactured using single crystal silicon.

FIGS. 6A to 6C are diagrams illustrating an operation principle of a channel of a MOS transistor formed at a tip of a probe; FIGS.

FIG. 7 shows the drain-source current (IDS) value of the SPM probe having the channel of the field-effect transistor shown in FIGS. 5A to 5C at various gate voltage levels due to a change in drain-source voltage (VDS). Graph showing the results.

FIG. 8 shows a gate voltage applied to a sample while maintaining a constant distance between the sample and the tip of the SPM probe having the channel of the field effect transistor of FIGS. 5A to 5C and maintaining a constant VDS. (VG) drain source current (I
Curve showing the change in DS).

FIG. 9 shows the characteristics of VDS-IDS while changing the VG value while maintaining the distance between the tip and the sample at about 2 m with the SPM probe having the channel of the field effect transistor of FIGS. 5A and 5B. It is a measured graph. <Description of References> 200 Semiconductor substrate 210 Probe 211 Source 212 Channel 213 Drain 220 Electrode pad

Continuing on the front page (72) Inventor Ta Jonggyo South Korea Republic of Korea Gyeonggi-do Suwon-si 990, Umedana-dong, Paldal-gu Sumiko 2 apartment complex 111 Building No. 105 (72) Inventor Sin ▲ Hyung ▼ pos. 66 Kachimaul Apartment, No. 314, Kumi-dong, Tang-gu, No. 314, Building No. 1404 (72) Inventor Mari ▲ Youn ▼ 738 Suisheon-dong, Gangnam-gu, Seoul, South Korea

Claims (12)

[Claims] 1. A chip, a channel region formed by doping a first impurity on a central slope of the chip, and a second impurity doped on both side slopes of the chip around the channel region. A probe of a scanning probe microscope having a channel structure of a field effect transistor, comprising a source and a drain. 2. The scanning probe microscope according to claim 1, wherein the chip is formed using a single crystal silicon substrate having a (100) plane. Probe. 3. The method according to claim 1, wherein the first impurity is an n-type impurity,
The probe of a scanning probe microscope according to claim 1, wherein the impurity is a p-type impurity. 4. The method according to claim 1, wherein the first impurity is a p-type impurity.
The probe of a scanning probe microscope having a channel structure of a field effect transistor according to claim 1, wherein the impurity is an n-type impurity. 5. A step of (1) forming a chip by etching a single crystal semiconductor substrate along a crystal plane, and (2) forming a channel region by doping a first impurity on a central inclined surface of the chip. And (3) forming a source and a drain by doping a second impurity on both side slopes of the chip to form a source and a drain. Production method. 6. The method according to claim 1, wherein the single crystal semiconductor substrate is a single crystal silicon substrate having a (100) plane, and both side slopes on which the source and the drain are formed are formed.
6. The method of claim 5, wherein the etching is performed to have a (111) plane. 7. The method according to claim 1, wherein the first impurity is an n-type impurity,
6. The method of claim 5, wherein the impurity is a p-type impurity. 8. The method according to claim 1, wherein the first impurity is a p-type impurity,
6. The method according to claim 5, wherein the impurity is an n-type impurity. 9. (1) A (100) -plane single-crystal semiconductor substrate is etched along a crystal plane to form a rod-shaped probe, and a tip portion thereof has a V-shaped plane having a first angle in a plane. Simultaneously etching the V-shaped side surfaces so that both sides have a (111) surface; and (2) doping a first impurity on both side inclined surfaces of the V-shaped tip at the tip of the probe. Forming a source and drain region by using the first impurity; and (3) forming a central peak of the inclined surface on which the source and drain regions doped with the first impurity are formed by the first impurity.
Forming a channel doped with the second impurity in the tip by removing only the first impurity by etching only the tip of the inclined surface so as to form a second angle greater than the second angle. A method of manufacturing a probe of a scanning probe microscope in which a channel of a field effect transistor is formed. 10. The method of claim 9, wherein the first angle is 90 ° and the second angle is 136 °.
A method for manufacturing a probe of a scanning probe microscope in which a channel structure of a field-effect transistor according to item 1 is formed. 11. The semiconductor device according to claim 9, wherein the first impurity is an n-type impurity, and the second impurity is a p-type impurity.
A method for manufacturing a probe of a scanning probe microscope in which a channel structure of a field-effect transistor according to item 1 is formed. 12. The semiconductor device according to claim 9, wherein the first impurity is a p-type impurity, and the second impurity is an n-type impurity.
A method for manufacturing a probe of a scanning probe microscope in which a channel structure of a field-effect transistor according to item 1 is formed.