JP2002334434A - Delay control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the accuracy of a delay signal using for the fine adjustment of a pulse width of the laser irradiation is affected by the variance of the delay amount due to the wiring load of a delay buffer, or the like, as the speed of the write-in to a disk is increased to the high magnifying speed. SOLUTION: The circuit is constituted of a delay buffer 2 for delaying a reference clock 1 of a writing signal, one period detecting circuit 5 of the reference clock for detecting the number of stages of the delay buffer, by which the reference clock delays by one period, one period delaying selector 4 of the reference clock for selecting the number of stages of the delay buffer detected by the one period delaying circuit 5 of the reference clock, a delay amount table 11 of the delay buffer wherein each delay information of the delay buffer is stored, a delay amount selecting circuit 8a for calculating based on the number of stages of the delay buffer detected by the one period detecting circuit 5 of the reference clock and the information of the delay amount table of the delay buffer, and a delay amount selector 3 for selecting the number of stages of the delay buffer selected by the delay amount selecting circuit 8a, then the delay signal 10 taking into account of the variance of the delay amounts due to the wiring load of the delay bluffer, or the like, is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CD-R, a CD-R,
The present invention relates to a delay control circuit in a control device that records data on an optical disk such as an RW.

[0002]

2. Description of the Related Art One of rewritable optical disk media is a CD-RW. The CD-RW is an EF as shown in FIG.
The M signal is recorded by irradiating a laser beam. The laser irradiation method is shown in FIG.
By irradiating a plurality of pulsed lights as shown in (b) at regular intervals, one mark length is written as shown in FIG. 4 (c).

In CD-R, CD-RW, etc., the overall width of the pulse with respect to the mark length to be formed is somewhat smaller than the mark length as shown in the pulse waveform of FIG. As shown in FIG. 4 (e), it is necessary to perform writing with a small value. Further, the influence of residual heat varies depending on the length of the mark, the distance from the previous writing, and the time. Settings are required. Moreover,
When recording information on an optical disk, writing at a high speed is becoming an essential condition. Therefore, in writing at a high speed, it is necessary to finely adjust each pulse width with higher accuracy.

FIG. 5 shows a conventional delay control circuit, and FIG. 6 shows a relationship between a reference clock and a delay signal. In FIG. 5, reference numeral 2 denotes a delay buffer for delaying a reference clock 1 of a signal to be written on an optical disk, 3 denotes a delay amount selector,
Is a reference clock one cycle delay selector, 5 is a reference clock one cycle detection circuit, 6 is a reference clock one cycle delay signal, 7
Is a reference clock one cycle delay stage number signal, 8 is a delay amount selection circuit, 9 is a delay buffer stage number selection signal, and 10 is a delay signal.

A reference clock 1 is input to a reference clock one-cycle delay selector 4 and a reference clock one-cycle detection circuit 5, passes through the delay buffer 2 by the number of delay buffers selected by the delay amount selection circuit 8, and has an arbitrary delay amount. Delay signal 1
0 is output.

At this time, since the delay amount of the delay buffer 2 changes due to external factors such as temperature change and voltage change, first, the reference clock 1 cycle detection circuit 5 detects the reference clock 1 as shown in FIG. Detecting that the signal is delayed by one cycle, the number m of stages of the delay buffer 2 is obtained.

Here, if the delay buffers 2 are all configured to use buffers having the same performance, the delay amounts of the delay buffers 2 are considered to be substantially the same as shown in FIG. The delay amount of one stage of the delay buffer) = (reference clock cycle) / (the number m of stages for one cycle).

As a specific example, when the numerical value of the reference clock 1 is 4.8 nsec and the delay buffer 2 detects one cycle of the reference clock in 24 stages as shown in FIG. 6th stage of delay buffer 2, 2.4nsec
Selects the twelfth stage of the delay buffer 2.

Thus, the number of stages of the delay buffer 2 is
A delay buffer stage number selection signal 9 selected by the delay amount selection circuit 8 is input to the delay amount selector 3 and a delay signal 10 is output.

[0010]

However, since writing at a high speed is becoming an essential condition, a higher accuracy delay signal is required at higher speeds.
Conventionally, each delay buffer uses the same performance buffer to generate a delay signal assuming that the delay amount of each delay buffer is almost the same as shown in FIG. The amount of delay varies, and the error in the amount of delay due to the variation affects the accuracy of writing as the writing speed increases.

An object of the present invention is to provide a delay control circuit which can solve the above problems and calculate a delay amount in consideration of variations in delay buffers to generate a more accurate delay signal. With the goal.

[0012]

The delay control circuit of the present invention provides a delay buffer delay amount table in consideration of the variation of each delay buffer, and uses the reference clock 1 when measuring the delay amount in the delay buffer delay amount table. By correcting the ratio n / m of the number n of stages of the delay buffer that is delayed by the period and the number m of stages detected by the reference clock one-cycle detection circuit by multiplying the delay amount in the delay buffer delay amount table, a more accurate delay is achieved. Generate a signal.

According to this configuration, a more accurate delayed signal can be generated.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A delay control circuit according to the present invention comprises: a delay buffer for delaying a reference clock of a signal to be written on an optical disk; a reference clock one cycle detection circuit for detecting that the reference clock is delayed by one cycle; A reference clock one-period delay selector for switching the number of stages of the delay buffer detected by the reference clock one-period detection circuit, a delay buffer delay amount table storing delay information of each of the delay buffers, A delay amount selection circuit that calculates and selects a delay amount based on the number of stages of the delay buffer detected by the cycle detection circuit and information of the delay buffer delay amount table; and a delay amount selection circuit that selects the delay buffer selected by the delay amount selection circuit. A delay amount selector for switching the number of stages is provided.

An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows a delay control circuit according to the present invention. 2 is a delay buffer for delaying a reference clock 1 of a signal to be written on the optical disk, 3 is a delay amount selector, 4 is a reference clock 1 cycle delay selector, 5 is a reference clock 1 cycle detection circuit, 6 is a reference clock 1 cycle delay signal, 7 is a reference clock one cycle delay stage number signal, 8a is a delay amount selection circuit, 9 is a delay amount selection signal, 10 is a delay signal, 1
1 is a delay buffer delay amount table.

The delay buffer delay amount table 11 connected to the delay amount selection circuit 8a stores delay information of each of the delay buffers 2. The delay amount selection circuit 8a
The delay amount is calculated and selected based on the number of stages of the delay buffer 2 detected by the reference clock 1 cycle detection circuit 5 and the information of the delay buffer delay amount table 11.

The configuration of the delay amount selection circuit 8a will be described in detail based on the operation. When an arbitrary delay amount is selected, information on the delay amount of each delay buffer 2 in consideration of the wiring load and the like is obtained by performing a simulation based on layout information, for example, and the delay buffer delay as shown in FIG. A quantity table 11 is provided.

Then, as in the prior art, first, the reference clock 1
The cycle detection circuit 5 detects the number m of stages of the delay buffer 2 that is delayed by one cycle of the reference clock 1 and outputs a reference clock one cycle delay signal 6. Since the delay amount of each delay buffer 2 changes due to an external factor such as a temperature change or a voltage change, the delay amount selection circuit 8a operates only for one cycle of the reference clock when the delay amount of the delay buffer delay amount table 11 is measured. The delay amount is corrected by multiplying the delay amount in the delay buffer delay amount table 11 by n / m according to the ratio of the number n of stages of the delay buffer 2 to be delayed to the number m of stages detected by the reference clock 1 cycle detection circuit 5. Is configured.

For example, in the delay buffer delay amount table 11 as shown in FIG. 2A, when the reference clock 1 is detected as 4.8 nsec and the delay buffer 2 is detected as one cycle of the reference clock in 24 stages, that is, the delay buffer delay amount When operating under the same conditions as when measuring the delay amount in Table 11, FIG.
As shown in (b), 1.2nsec is the seventh stage of the delay buffer 2, 2.4nsec is the 13th stage, and 3.6nsec is the 19th stage, and the actual delay amounts are 1.22nsec, 2.41nsec and 3.63nsec, respectively. The delay amount in parentheses is a value calculated from the circle amount after the delay buffer delay amount table.

On the other hand, in the conventional circuit having no delay buffer delay amount table 11, as shown in FIG. 2C, the number of stages of the delay buffer 2 is 1.2 ns and the delay buffer 2 is 2.4 ns.
ec is the 12th stage, 3.6nsec is the 18th stage, and the actual delay amounts are 1.07nsec, 2.23nsec, 3.46nsec, respectively.
It can be seen that the error is larger than in this embodiment.

As described above, if the delay amount in the delay buffer delay amount table 11 is measured and written, the reference clock 1 cycle detection circuit 5 detects that the delay buffer 2 has one cycle of the reference clock in 16 stages. 3A, the delay amount selection circuit 8a calculates a value obtained by multiplying the delay amount of the delay buffer delay amount table 11 by 24/16 like the delay amount of FIG. As shown in FIG. 3B, the number of stages of the delay buffer 2 is 1.2 nsec = 4.
The stages, 2.4 nsec are 9 stages, and 3.6 nsec are 13 stages, and the actual delay amounts are 1.11 nsec, 2.52 nsec, and 3.68 nsec, respectively.

Also in this case, the number of stages of the delay buffer 2 in the conventional circuit is 1.2 nsec, as shown in FIG.
2.4nsec has 8 stages and 3.6nsec has 12 stages, and the actual delay amounts are 1.11nsec, 2.20nsec, and 3.39nsec, respectively. It can be seen that the error is smaller in this embodiment.

The delay buffer stage number selection signal 9 having the number of stages of the delay buffer 2 selected by the delay amount selection circuit 8a is input to the delay amount selector 3 and the delay signal 10 is output.

[0024]

As described above, according to the present invention, a delay buffer delay amount table is provided in consideration of the variation of each delay buffer, and the delay is delayed by one reference clock cycle when the delay amount of the delay buffer delay amount table is measured. By multiplying the ratio n / m of the number of stages n of the delay buffer to be executed and the number m of stages detected by the reference clock one-cycle detection circuit by the delay amount in the delay buffer delay amount table, a more accurate delay signal is generated. By generating a write pulse using this delay signal, it is possible to increase the write accuracy at a high double speed due to a variation in the delay amount of each delay buffer due to a wiring load or the like. In addition, it is possible to reduce the influence of variations generated in the diffusion step.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a delay control circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a delay buffer delay amount table according to the embodiment;

FIG. 3 is an explanatory diagram of a delay amount in an actual operation of the embodiment.

FIG. 4 is a waveform diagram at the time of signal writing.

FIG. 5 is a configuration diagram of a delay control circuit in a conventional configuration.

FIG. 6 is a timing chart showing a relationship between a reference clock and a delay signal in a conventional configuration.

FIG. 7 is an explanatory diagram of a delay amount of a delay buffer in a conventional configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference clock 2 Delay buffer 3 Delay amount selector 4 Reference clock 1 cycle delay selector 5 Reference clock 1 cycle detection circuit 6 Reference clock 1 cycle delay signal 7 Reference clock 1 cycle delay stage number signal 8a Delay amount selection circuit 9 Delay amount selection signal 10 Delay signal 11 Delay buffer delay amount table

Continued on the front page F term (reference) 5B079 AA10 CC02 DD06 5D044 AB01 BC04 CC06 GM02 GM15 5D090 AA01 BB03 BB07 CC01 DD05 EE01 FF17 FF21 KK04 5J001 AA11 DD09

Claims (1)

[Claims] 1. A delay buffer for delaying a reference clock of a signal to be written on an optical disk, a reference clock one-cycle detection circuit for detecting that the reference clock is delayed by one period, and a detection signal detected by the reference clock one-cycle detection circuit. A reference clock one-cycle delay selector for switching the number of stages of the delay buffer, a delay buffer delay amount table storing delay information of each of the delay buffers, and the delay buffer detected by the reference clock one-cycle detection circuit. A delay amount selection circuit that calculates and selects a delay amount based on the number of stages and the information of the delay buffer delay amount table, and a delay amount selector that switches the number of stages of the delay buffer selected by the delay amount selection circuit. Delay control circuit.