JP2002330077A - Method and program for correcting only loss, medium recording program for correcting only loss and circuit dedicated for correction of loss - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a program for correcting only Loss, a medium recording a program for correcting only Loss and a circuit dedicated for correction of Loss applicable to data correction processing in a data recorder/ reproducer or a data transmitter/receiver and can be specified to correct Loss through a simple arrangement. SOLUTION: Euclidean operating function not required at the time of executing only Loss correction is eliminated and a corresponding arrangement is employed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erasure-only correction method, a program for an erasure-only correction method, a recording medium on which a program for an erasure-only correction method is recorded, and an erasure correction circuit. The present invention can be applied to error correction processing in a transmission / reception device, and more specifically, can be applied to a data recorder, a data transmission device, and the like. The present invention eliminates the Euclidean arithmetic function that becomes unnecessary when only erasure correction is performed, and adopts a configuration corresponding to this elimination, so that erasure correction can be performed specifically for erasure correction with a simple configuration. To

[0002]

2. Description of the Related Art Conventionally, in various data processing apparatuses, error correction is performed by repeating normal correction and erasure correction. That is, FIG. 47 is a flowchart showing the processing procedure of this series of error correction processing.

In the following description, a finite field defined on a Galois field GF (2 ^m ) whose element is 2 ^m is used, and an RS (Reed of code length n with p parity added) is used.
-Solomon) shows a decoding procedure when a code is used. Also consider a case where there are ε erasure symbols (erasure errors) in the entire code and ν errors (normal errors) other than the erasure position. However, ε and ν satisfy the following relational expression.

[0004]

(Equation 1)

The erasure position counted from the head of the code is U _i (1 ≦ i ≦ ε), and the erasure pattern of this erasure position is V _i (1 ≦ i ≦ ε). Further, an error position other than the lost symbol shown in the same manner is defined as X _i (1 ≦ i ≦ ν), and an error pattern at this error position is defined as Y _i (1 ≦ i ≦ ν).
And Further, the coefficients of the syndrome polynomial are set by setting the highest-order coefficient S _p-1 of the syndrome polynomial S (x) to the lowest-order coefficient, and thereafter, sequentially until the lowest-order coefficient S ₀ becomes the highest-order coefficient. The decoding is performed using an inverse syndrome polynomial (equation (4)) in which the order of the coefficients is changed. The inverse syndrome polynomial is a polynomial having the reciprocal of the root of the original syndrome polynomial S (x) as a root, and is hereinafter simply referred to as a syndrome polynomial as appropriate.

[0006] In such an assumption, the error correction processing by the processing of FIG. 47, obtains the error position X _i other than loss symbols, and all the error pattern V _i and Y _i. That is, in the error correction process, the process proceeds from step SP1 to step SP2, where the calculation process of the syndrome and the calculation process of the erasure position polynomial are executed.

(Calculation of Syndrome) In the syndrome calculation process, the received data r
And the parity check matrix H, p syndromes S _j (0 ≦ j ≦ p−1) are obtained by the following equation. Here, S is a syndrome, c is transmission data,
e is error data.

[0008]

(Equation 2)

When the error data e is 0, the syndrome S becomes 0. A parity check matrix H for a code length n and a parity number p is expressed by the following equation.

[0010]

(Equation 3) A polynomial of degree p-1 having the syndrome S _j as a coefficient obtained in this manner is a syndrome polynomial, and is represented by the following equation.

[0011]

(Equation 4)

Here, from equation (3), the disappearance position U_iIs α
^m, J rows of error positions in the parity check matrix H
The element of the eye is (α^m)^j= U_i ^jBy being expressed,
Each coefficient S of the syndrome polynomial_jIs the disappearance position U_i, Wrong
Position X_i, Vanishing pattern V _i, Error pattern Y_iFor
And is expressed by the following equation.

[0013]

(Equation 5)

Accordingly, the syndrome polynomial is given by:
From equation (5), the following equation can be used. In error correction, the syndrome polynomial S
(X) is calculated.

[0015]

(Equation 6)

[0016] In calculation of the erasure position polynomial contrast (calculation of the erasure position polynomial) defines the ε following erasure position polynomial from the known ε erasures position U _s be defined in the same manner as described above . The vanishing position polynomial is x = U
_{In s} (1 ≦ s ≦ ε), a polynomial whose value is 0 can be set as in the following equation.

[0017]

(Equation 7)

(Calculation of Corrected Syndrome Polynomial) In the error correction process, the process proceeds to step SP3, where a process of calculating a corrected syndrome polynomial is executed. Wherein calculation of the modified syndrome polynomial is a remainder for x ^p of the product of the erasure position polynomial and syndrome polynomial, which defines the modified syndrome polynomial by the following equation.

[0019]

(Equation 8)

(Derivation of Error Position Polynomial and Error Evaluation Polynomial) Subsequently, in the error correction processing, step SP4
The error locator polynomial and the error evaluation polynomial are derived by the processing of the Euclidean mutual operation. That is, like the erasure locator polynomial, x = _Xt (1 ≦
(t ≦ ν), (Formula 7) is a polynomial in which the value is 0, and can be set as the following formula.

[0021]

(Equation 9)

The error evaluation polynomial is represented by Key equiati
on is a p-1 degree polynomial expressed by the following equation, and an error locator polynomial expressed by the modified syndrome polynomial T (x) described above with respect to equation (8) and the equation (9) Can be obtained from

[0023]

(Equation 10)

(Calculation of Error Pattern and Erasure Pattern) Subsequently, the error correction process proceeds to step SP5, where an error position is detected and an error pattern is detected. That is, in the error correction processing, an error locator polynomial by Expression (9)
When the erasure position polynomial by Equation (7) and the error evaluation polynomial by Equation (10) are found, Forney algorithm
The error pattern Y _i (1 ≦ i ≦ ε),
The disappearance pattern V _i (1 ≦ i ≦ ν) can be obtained.

That is, Forney algorithm
In the processing by m, a product polynomial obtained by multiplying the error locator polynomial and the erasure locator polynomial is defined by the following equation.

[0026]

[Equation 11]

First, the error pattern Y_iIf you ask for
As shown by the equation, the product multiplied by the equation (11)
Error pattern Y to be obtained by first differentiating the term_iError position
X _iIs assigned.

[0028]

(Equation 12)

[0029]

(Equation 13)

Here, the following equation can be obtained by substituting x = X _i into the error evaluation polynomial expressed by the equation (10) and modifying the equation (13).

[0031]

[Equation 14]

The equation (14) can be modified as follows, whereby the error pattern Y _i can be obtained.

[0033]

(Equation 15)

On the other hand, when the erasure pattern V _i is obtained, the error position U _i of the erasure pattern V _{i to be} obtained is calculated by the first derivative of the product polynomial expressed by the following equation (12). substitute.

[0035]

(Equation 16)

Here, the following equation can be obtained by substituting x = U _i into the error evaluation polynomial expressed by the equation (10) and transforming the equation using the equation (16).

[0037]

[Equation 17]

[0038] The equation (17) can be modified as shown in the following equation, thereby determining the lost pattern V _i.

[0039]

(Equation 18)

[0040] In the error correction processing (correction data) detects the error pattern and lost pattern in this way, at the subsequent step SP6, with respect to the received data r is the received signal, the error position X _i, the error By adding the pattern Y _i (1 ≦ i ≦ v) and at the disappearance position U _i , the disappearance pattern V _i (1 ≦ i ≦ v)
After correcting the received data r by adding ε),
The process proceeds to step SP7 to output the error-corrected data.

FIG. 48 is a block diagram showing an erasure correction circuit for performing such an error correction process. In the erasure correction circuit 1, the SYN block 2 receives the received signal r
, A syndrome polynomial is generated by calculating the syndrome, and a erasure position polynomial is generated from the erasure flag U.
The subsequent EUC block 3 generates a corrected syndrome polynomial from the syndrome polynomial and the erasure position polynomial which are the processing result D02 of the SYN block 2, and generates an error evaluation polynomial and an error from the corrected syndrome polynomial and the erasure position polynomial by Euclidean mutual operation processing. Generate a position polynomial. The subsequent CHS block 4 obtains an error position and an error pattern from the error evaluation polynomial and the error position polynomial which are the processing results D03 of the EUC block 3, and further corrects the received signal r to output an output signal c.

Of these blocks 2 to 4, the EUC block 3 is composed of two shift registers of column A and column B, a Galois field divider, a Galois field multiplier and a Galois field adder. Storing the coefficients of two polynomials that perform the Euclidean algorithm in one shift register;
Repeat the division process between polynomials.

FIGS. 49 to 53 show the EUC block 3
FIG. The EUC block 3 is configured by sequentially cascading respective units shown in FIGS. 49 to 53. Note that in FIGS. 49 to 53, the mutual connection relationship is indicated by the reference numeral attached to the signal line. That is, EUC block 3
Are the division unit DIV shown in FIG.
As shown in FIG. 53, a multiplication and addition unit MLT is provided. Among them, the division unit DIV (FIG. 49)
A divider 11 for executing the division of the highest coefficient in the Euclidean mutual operation, a switch 12 for setting various coefficients in this divider 11, and a register 13A for storing the highest coefficient
0, 13B0, the switches 13A0, 13B0 which initialize these registers 13A0, 13B0 and further store the coefficients.
4B01.

On the other hand, the multiplication and addition unit MLT (FIGS. 50 to 53) includes multipliers 15B1 to 15B1 corresponding to the respective coefficients.
15B12 and adders 16A1 to 16A12, these multipliers 15B1 to 15B12 and adders 16A1 to 16A
12 for switching the input to each of the switches 12
17AB12, and registers 18A1 to 18A1 for setting the coefficients which are the inputs of the switches 17AB1 to 17AB12, respectively.
18A12, 18B1 to 18B12, each register 18A
Switches 19A1 to 19A12 and 19B1 to 19B1 for switching inputs of 1 to 18A12 and 18B1 to 18B12
2.

Of these, the switching devices 19A1 to 19 in the A row are provided.
A12 indicates the corresponding output from the SYN block 2, the output of the corresponding adder 16A1 to 16A12, the output of the corresponding register 18A1 to 18A12 in column A, the output of the adder in the subsequent stage, and the preset value of logic 0 in the register in column A. 18A1
~ 18A12 so that it can be selectively output.
The column switchers 19B1 to 19B12 correspond to the corresponding adder 1
Outputs of 6A1 to 16A12, switches 17AB1 to 17A
The output of B12 and the preset value of logic 0 can be selectively output to the registers 18B1 to 18B12 in the B column. In the last-stage switch 19A12, a preset value of logic 0 is input to the input corresponding to the output of the adder in the subsequent stage.

The switches 17AB1 to 17AB12 are
Corresponding A-column and B-column registers 18A1-1
8A12 and the outputs of 18B1 to 18B12 can be selected and output to the corresponding adders 16A1 to 16A12.
The outputs of A1 to 18A12 and 18B1 to 18B12 can be selectively output to multipliers 15B1 to 15B12. On the other hand, multipliers 15B1 to 15B12
Are the outputs of the divider 11 and the switches 17AB1 to 17AB1
2 are output, and the adders 16A1 to 16A1
6A12 outputs an added value based on the outputs of the multipliers 15B1 to 15B12 and the outputs of the switches 17AB1 to 17AB12.

Thus, in the multiplication and addition unit MLT, these switches 17AB1 to 17AB12, 19A
By controlling the switching of 1 to 19A12 and 19B1 to 19B12, the registers 18A1 to 18A12 in column A and column B
Coefficients of two polynomials are set to 18B1 to 18B12, respectively, and the adders 16A1 to 16A12 and the multiplier 15B1 are used by using the set coefficients and the output of the divider 11.
To 15B12, and the resulting operation results are stored in registers 18A1 to 18A1
18A12, 18B1 to 18B12, and furthermore, the result of this operation is stored in registers 18A1 to 18A
12 can be set.

On the other hand, in the division unit DIV, the switching unit 14A0 in column A includes the corresponding output from the SYN block 2, the output of the register 13A0, the output of the adder 16A9 of the subsequent multiplication and addition unit MLT, and the logic. 0
Are stored in the registers 18A1 to 18A12 in column A.
And a switch 1 for row B
4B0 is the output of the switch 12, the preset value of logic 1,
The output of the register 18A7 and the output of the register 13B0 in the multiplication and addition unit MLT can be selectively output to the register 13B0. On the other hand, the switch 12
Is configured to switch the selected output of the registers 13A0 and 13B0 to the denominator-side input and the numerator-side input of the divider 11, respectively, and output the result. The divider 11 switches the division result to the switch of the multiplication and addition unit MLT. 19B1 to 19B12.

Thus, also in the division unit DIV, the most significant coefficients are set in the columns A and B, and the intermediate output in the division unit DIV is set in the registers 13A0 and 13A.
B0 can be set, a division process is performed using the set coefficient, and the operation result obtained as a result can be set in the register of column B of the division unit DIV. By these, EUC
The block 3 is configured to calculate a coefficient of a desired polynomial from two polynomials under the control of the switch by a predetermined control mechanism.

Thus, the EUC block 2 has one divider 11 and 2 × p (p: number of parity) multipliers 15B
1 to 15B12, 2 × p adders 16A1 to 16A1
2. 4 × p + 2 registers 1 for storing polynomial coefficients
8A1 to 18A12, 18B1 to 18B12 and the like. In the configurations shown in FIGS. 50 to 53, the number of parities p is six.

In such an erasure correction circuit, a configuration has been proposed in which one arithmetic unit is used in a time-division manner to reduce the circuit configuration. That is, in the case of this configuration, for example, when the multiplicity by such time division is set to L, the number of multipliers and the number of multipliers are respectively (2 ×
p) / L. In this case,
For a register that stores the coefficients of a polynomial, 2 × L ×
(2 × p) / L + 3.

FIGS. 54 to 59 show E at multiplicity L = 3.
It is a connection diagram showing a UC block. 54 to 59, the same components as those of the above-described EUC block 3 in FIGS. 48 to 53 are denoted by the corresponding reference numerals, and redundant description will be omitted. In the multiplication and addition unit MLT of the EUC block 23 (FIGS. 56 to 59), the registers 18A1 to 18A12 and 18B1 / 18B12 in the A and B columns with the number of stages twice the number of parities p can hold coefficients and the like. It is composed of The multiplication / addition unit MLT includes the registers 18A1
18A12 and 18B1 / 18B12 are grouped in units of three, and columns A and B arranged at the head of each group
As with the EUC block 3 described above, adders 16A1 to 16A10 and multipliers 15B1 to
15B10 and switches 17AB1 to 17AB10 are arranged. Rows A and B located at the end of each group
Similarly to the EUC block 3 described above, the switches in the columns are also provided with the switches 19A3 to 19A12, 19B.
3 to 19B12 are arranged. The switch 19A3-1
In 9A12 and 19B3 to 19B12, the register output arranged at the head of each group is supplied instead of the register supplying the selected output.

In each group, in the B series, each register is connected in series. On the other hand, the A-series has switches 24A1 to 24A10, 25A2, and 25A11, respectively.
Are interposed therebetween, and the registers are connected in series. Here, the switches 24A1 to 24A10 are configured to be able to output the input of the coefficient and the selected output of the register output at the subsequent stage to the subsequent register. On the other hand, the switches 25A2, 25A
11 is a coefficient input, a register output at the subsequent stage, and a logical 0
And the output of the adder 16A1 to 16A10 assigned to each group.

Thus, the multiplication and addition unit MLT
, The switches 19A3 to 19A12, 24A1
24A10, 25A2, 25A11, after setting the coefficients of the polynomial in the registers of column A constituting each group, these coefficients can be transferred within each group and set in the registers of the B sequence. Adder 1
6A1 to 16A10 and the operation results of the multipliers 15B1 to 15B10 are stored in registers 18A1 to 18A12 and 18B1.
To 18B12 so that the adders 16A1 to 16A10 and the multipliers 15B1 to 15B10 can be shared by each group.

The division unit DIV (FIG. 55) outputs the output of the divider 11 via the switch 27 to the multiplication and addition unit MLT so as to correspond to the processing of the multiplication and addition unit MLT for each group. To be output to Here, the switch 27 outputs the output of the divider 11 to the multiplication / addition unit MLT, and also holds the output of the divider 11 by the register 28 to hold the output of the multiplication / addition unit MLT.
And a reset value of logic 0 can be output instead.

In the EUC block, in the ELL unit (FIG. 54), the output of the register 13A0, which is the highest order of the multiplication and addition unit MLT, is received by the 0 detection circuit 29, and a logic 0 is generated in the output of the register 13A0. Detect timing. The values of the two registers DR and Dg corresponding to the columns A and B are switched by the switch 30, and the values of the registers DR and Dg and the status by the 0 detection circuit 29 are determined by the controller 25 and multiplied and added. The operation of each switch arranged in the unit MLT is controlled. In the switch 30, a predetermined set value p, a register Dg,
, The output value of the register DR whose polarity is determined via the polarity determiner (-1), or the output value of the register Dg whose polarity is determined via the polarity determiner (-1). It is configured to be able to set. For a register Dg corresponding to column B, a predetermined set value p + 1 and a register DR
And the output value of the register Dg can be set.

[0057]

In recent years, various digital devices have been developed. In such digital devices, error correction is generally performed by repeating normal correction and erasure correction. However, systems that only perform erasure correction have been proposed in recent years. In such a system, only erasure correction is performed using an erasure correction circuit capable of performing both normal correction and erasure correction. Had been done.

However, when only the erasure correction is performed by using the erasure correction circuit capable of performing both the normal correction and the erasure correction in this manner, functions that are originally unnecessary are wastefully included. The circuit scale is unnecessarily increased, and it is considered that there is still room for improvement in devices that require miniaturization.

The present invention has been made in view of the above points. An erasure correction method, an erasure correction method program, and an erasure correction method program capable of performing erasure correction specialized for erasure correction with a simple configuration are provided. It is intended to propose a recorded recording medium and an erasure correction circuit.

[0060]

According to the first aspect of the present invention, an error evaluation polynomial and an error location polynomial are obtained from a modified syndrome polynomial and an erasure location polynomial by applying the erasure only correction method. And a fifth step of obtaining an error position and an error value from the error position polynomial and the error evaluation polynomial.

According to the third aspect of the present invention, a fourth step of obtaining an error evaluation polynomial and an error location polynomial from the modified syndrome polynomial and the erasure location polynomial by applying the program to the erasure only correction method, Fifth Finding Error Position and Error Value from Error Evaluation Polynomial
And the following steps.

According to the fourth aspect of the present invention, the present invention is applied to a recording medium on which a program for the erasure-only correction method is recorded.
This erasure-only correction method includes a fourth step of obtaining an error evaluation polynomial and an error locator polynomial from the corrected syndrome polynomial and the erasure position polynomial, and a fifth step of obtaining an error position and an error value from the error locator polynomial and the error evaluation polynomial. To have.

According to the fifth aspect of the present invention, there is provided a fourth arithmetic means for obtaining an error evaluation polynomial and an error locator polynomial from a corrected syndrome polynomial and an erasure locator polynomial by applying to an erasure correction dedicated circuit; Fifth calculating means for obtaining an error position and an error value from the evaluation polynomial is provided.

According to the first aspect of the present invention, the fourth step of applying the erasure-only correction method to obtain the error evaluation polynomial and the error locator polynomial from the modified syndrome polynomial and the erasure locator polynomial; By having a fifth step of obtaining an error position and an error value from a polynomial, an error evaluation polynomial and an error position polynomial can be obtained directly from the modified syndrome polynomial and the erasure position polynomial. Erasure correction can be performed specifically for erasure correction.

Accordingly, claims 3, 4, and 5 are provided.
According to the configuration, it is possible to provide a program of the erasure-only correction method, a recording medium on which the program of the erasure-only correction method is recorded, and a circuit dedicated to the erasure correction, which can perform the erasure correction specialized for the erasure correction with a simple configuration. it can.

[0066]

Embodiments of the present invention will be described below in detail with reference to the drawings as appropriate.

(1) First Embodiment (1-1) Configuration of First Embodiment FIG. 1 shows a processing procedure of only erasure correction according to an embodiment of the present invention in comparison with FIG. It is a flowchart shown. In this embodiment, the Euclidean algorithm operation processing is omitted, and after the modified syndrome polynomial calculation processing, the error position detection processing is executed. Further, in this error position detection processing, only erasure correction is performed, and erasure correction specialized for erasure correction can be performed by simple processing.

In the following description, a finite field defined on a Galois field GF (2 ^m ) whose element is 2 ^m is used, and an RS code of code length n to which p parities are added is used. The following shows the decryption procedure in the case where there is an error. It is also assumed that ε erasure symbols (erasure errors) exist in the entire code. Here, ε satisfies the following relational expression.

[0069]

[Equation 19]

The erasure position counted from the head of the code is U _i (1 ≦ i ≦ ε), and the erasure pattern at this erasure position is V _i (1 ≦ i ≦ ε). Further, the coefficients of the syndrome polynomial are set by setting the highest-order coefficient S _p-1 of the syndrome polynomial S (x) to the lowest-order coefficient, and thereafter, sequentially until the lowest-order coefficient S ₀ becomes the highest-order coefficient. Inverse syndrome polynomial (Equation (22)) obtained by changing the order of coefficients
Will be used for decoding. The inverse syndrome polynomial is a polynomial having the reciprocal of the root of the original syndrome polynomial S (x) as a root, and is hereinafter simply referred to as a syndrome polynomial as appropriate.

Under such a premise, in the error correction processing, steps SP11 to SP11 in FIG.
Then, the process proceeds to step S12, where a syndrome calculation process and a disappearance position polynomial calculation process are performed.

(Calculation of Syndrome) In the syndrome calculation processing, the received data r
And the parity check matrix H, p syndromes S _j (0 ≦ j ≦ p−1) are obtained by the following equation. Here, S is a syndrome, c is transmission data,
e is error data.

[0073]

(Equation 20)

When the error data e is 0, the syndrome S becomes 0. A parity check matrix H for a code length n and a parity number p is expressed by the following equation.

[0075]

(Equation 21) A polynomial of degree p-1 having the syndrome S _j as a coefficient obtained in this manner is a syndrome polynomial, and is represented by the following equation.

[0076]

(Equation 22)

Here, from the equation (21), when the erasure position U _i is α ^m , the error position j in the parity check matrix H is j.
Since the element in the row is represented by (α ^m ) ^j = U _i ^j , each coefficient S _j of the syndrome polynomial is represented by the following equation using the disappearance position U _i and the disappearance pattern V _i .

[0078]

(Equation 23)

Therefore, the syndrome polynomial is represented by (Equation 2)
From equation (2) and equation (23), the following equation can be used. In error correction, a syndrome polynomial is calculated from input data.

[0080]

(Equation 24)

(Calculation of erasure position polynomial) In the process of calculating the erasure position polynomial, an ε-order erasure position polynomial is defined from the known ε erasure positions U _k defined in the same manner as described above. . The vanishing position polynomial is x = U
_{In k} (1 ≦ k ≦ ε), a polynomial whose value is 0 can be set as in the following equation, whereby the erasure position polynomial is obtained from the erasure flag corresponding to the input data.

[0082]

(Equation 25)

(Calculation of Corrected Syndrome Polynomial) In the error correction processing, when the syndrome polynomial and the erasure position polynomial are calculated in this manner, the following step SP1 is performed.
In step 3, a process for calculating a modified syndrome polynomial is executed. Wherein calculation of the modified syndrome polynomial is a remainder for x ^p of the product of the erasure position polynomial and syndrome polynomial, which defines the modified syndrome polynomial by the following equation.

[0084]

(Equation 26)

Here, j− of the syndrome polynomial S (x)
Since the k-th order coefficient is represented by S _{pj-1 + k} , in this modified syndrome polynomial, the coefficient T of each order
_j (0 ≦ j ≦ p−1) can be expressed by the following equation.

[0086]

[Equation 27]

[0087]

[Equation 28]

Therefore, it can be understood from these that it is difficult to decode unless the term T _j (ε ≦ j) of the modified syndrome polynomial equal to or higher than ε is 0. From the coefficients of these modified syndrome polynomials, the modified syndrome polynomial can be expressed by the following equation.

[0089]

(Equation 29)

Thus, in the error correction processing according to the present embodiment, a corrected syndrome polynomial is calculated from the syndrome polynomial and the erasure position polynomial by this arithmetic processing.

(Derivation of Error Evaluation Polynomial) In this embodiment, in the following step SP14, an error evaluation polynomial is derived and an error pattern V is detected. Here, the error evaluation polynomial can be represented by a p-1 degree polynomial expressed by the following equation using the key equation. Here, since the processing is only for the erasure error, the value of the error locator polynomial is set to 1 in the error locator polynomial. By this arithmetic processing, in this embodiment, the error evaluation polynomial is derived from the corrected syndrome polynomial.
The error locator polynomial is determined from the erasure locator polynomial.

[0092]

[Equation 30]

(Calculation of Erasure Pattern) When the erasure position polynomial and the error evaluation polynomial are obtained in this manner, Forne
The disappearance pattern V _i (1 ≦ 1)
i ≦ ν). That is, the error evaluation polynomial by the equation (30) can be modified as shown in the following equation.

[0094]

(Equation 31)

[0095] When the hand (number 25) erasure position polynomial and first derivative of the by equation substituting erasure position U _i of the lost pattern V _i to be obtained, it is possible to obtain the following relational expression.

[0096]

(Equation 32)

[0097]

[Equation 33]

Further, the erasure position polynomial has the erasure position U _k
Any two disappearance positions U _i and U of (1 ≦ k ≦ ε)
_{When l} (i ≠ l) is substituted, the following relational expression holds.

[0099]

(Equation 34)

Further, the following relational expression can be obtained from Expression (34).

[0101]

(Equation 35)

Therefore, when U _i ≠ U _l , the following relational expression can be obtained.

[0103]

[Equation 36]

By these, x = U _i is substituted into the error evaluation polynomial by the equation (31), and the equation (33) and the equation (36) are obtained.
By transforming the equation, the following relational expression can be obtained.

[0105]

(37)

[0106] Thus when determining the disappearance pattern V _i from the equation (37) below, it is possible to determine the loss pattern V _i by the following equation.

[0107]

(38)

Thus, in this embodiment, the error position and error value are obtained from the error position polynomial and the error evaluation polynomial in step SP14.

[0109] (correction data) In this way, obtaining the lost pattern V _i, to correct the data in the subsequent step SP15, and then outputs the corrected data in step SP16. In this data correction, the received signal r is corrected by adding an erasure pattern V _i (1 ≦ i ≦ ε) at the erasure position U _i to the received signal r.

FIG. 2 is a block diagram showing an erasure correction dedicated circuit according to this erasure correction processing procedure in comparison with FIG. This erasure correction dedicated circuit 31 is used for the EUC block 3
3 and the configuration of the CHS block 34 are different,
The configuration is the same as the erasure correction circuit 1. Thereby, in this embodiment, the SYN block 2 constitutes a first calculating means for obtaining a syndrome polynomial from input data and a second calculating means for obtaining a lost position polynomial from a lost flag corresponding to the input data. For EUC block 3
3 constitutes a third calculating means for obtaining a corrected syndrome polynomial from the syndrome polynomial and the erasure position polynomial, and a fourth calculating means for obtaining an error evaluation polynomial and an error position polynomial from the corrected syndrome polynomial and the erasure position polynomial. Further, the subsequent CHS block 34 includes fifth arithmetic means for calculating an error position and an error value from the error position polynomial and the error evaluation polynomial, and sixth arithmetic means for correcting an error in the input data using the error position and the error value. It is made up of:

FIG. 3 is a chart showing the processing procedure according to this embodiment in comparison with the processing procedure described above with reference to FIG. In the erasure-only correction processing procedure, unlike the erasure correction processing, the modified syndrome polynomial is equal to the error evaluation polynomial, and the erasure position polynomial is equal to the error position polynomial, so that it is not necessary to perform the Euclidean mutual operation. As a result, in this embodiment, the structure of the EUC block in the erasure correction dedicated circuit can be simplified, and erasure correction can be performed specifically for erasure correction by simple processing.

FIGS. 4 to 8 are connection diagrams showing the EUC block 33 of the erasure correction dedicated circuit according to this embodiment. The EUC block 33 includes a one-column shift register, a Galois field divider, a Galois field multiplier, a Galois field adder, and the like, for calculating the modified syndrome polynomial and the erasure position polynomial.

Among them, the Galois field divider is provided for obtaining the reciprocal U _i ^-1 of the erasure position. Therefore, only one Galois field divider is arranged inside the EUC block 33 and the division unit DI
V (FIG. 4). That is, as shown in FIG. 9, the position information of the erasure flag is input in the order from the tail α ^n-1 of the code to the head α ⁰ of the code at the time of input. As a result, the erasure position detected here is not the original erasure position _Ui , but a value obtained by counting the codes in reverse order. Thus, when applied to the erasure position polynomial represented by the expression (25), the reciprocal U _i ^{-1 of the} original erasure position U _i is required.

Therefore, in the division unit DIV,
The position information of the erasure flag is set in the registers 37 and 38 via the switches 35 and 36, and the data stored in the registers 37 and 38 is divided by the divider 39. _The erasure position according to _i ^-1 is calculated.

[0115]

[Equation 39]

Multiplication and addition unit MLT (FIGS. 5 to 8)
Is configured by cascading a predetermined number of units each including a register, a Galois field multiplier, and a Galois field adder in accordance with the number of parities. Here, as shown in FIG. 10, one unit is configured such that coefficients and the like can be set by a switch 40 in a register 41 constituting a one-column shift register in the multiplying and adding unit MLT. This unit multiplies the selected output of the switch 42 and the output of the register 41 arranged in the subsequent unit by a multiplier (Galois field multiplier) 43, and
The multiplication result of 3 and the output of the register 41 are added by an adder 44.

Switching device 4 for switching the input of register 41
At 0, control is performed so that the contact point is switched according to the mode of the multiplying and adding unit MLT. That is, when the contents of the register 41 are cleared, as shown in FIG. 11, a reset input of logic 0 is selected. On the other hand, when loading coefficients into registers,
As shown in FIG. 12, the contact is switched to the corresponding output of the SYN block 2. As shown in FIG. 13, when the output value of the subsequent unit is shifted, the output of the register 41 in the subsequent unit is controlled to be selected. When the output value of the subsequent unit is shifted, control is performed to select the output of the register 41 in the corresponding subsequent unit (the contact point indicated by reference numeral 3).

On the other hand, in the processing such as the calculation, the output of the adder 44 is selected. That is, as shown in FIG. 14, a switch 42 for switching the input of the multiplier 43 selects the set value of the value 0, sets the output of the multiplier 43 to the value 0, and changes the output of the adder 44 by the switch 40. By making the selection, the output of the register 41 is reset in the register 41 as it is, thereby executing the hold process. In setting the hold, as shown in FIG.
By selecting the output of the division unit DIV by the switch 42, the operation result is stored in the register 41, and can be output to the subsequent unit.

In FIGS. 5 to 8, each unit in FIG. 10 is indicated by a suffix to show the corresponding configuration of each unit. In each unit, the input in the switch 40 is omitted and the multiplier 43 and the adder 44 are omitted from the basic configuration shown in FIG. 10 according to the required operation. .

In this embodiment, the modified syndrome polynomial has a maximum of p coefficients and the erasure position polynomial has a maximum of p + 1 coefficients, whereas the zeroth order coefficient of the erasure position polynomial always has Becomes 1. Thereby, in the multiplication-addition unit MLT, the cascade connection is constituted by a total of 2 × p units, which are p units, respectively, for the modified syndrome polynomial and the erasure position polynomial. 2 steps
Xp stage. Thus, in this embodiment, the number of stages of the shift register is reduced by effectively utilizing that the zero-order coefficient of the erasure position polynomial is always 1.

As a result, in the EUC block 33, 2 × p registers for storing the modified syndrome polynomial and the erasure position polynomial are required, and in the entire EUC block 33, one Galois field divider, 2 × p p Galois field multipliers, 2 × p Galois field adders, 2 × p +
Two registers are required. Thus, in this embodiment, the register is 2 × p compared to the conventional erasure correction circuit.
The number of devices is reduced, and the configuration of the control circuit can be simplified accordingly.

More specifically, when the number of parities is six (see FIG. 4).
8), one Galois field divider, Galois field multiplier 12
, 12 Galois field adders, and 14 registers for storing the operation results.

FIG. 16 is a table showing the modes of the EUC block 33. The operation of the EUC block 33 is divided into modes according to this chart. Here, the PI mode is a mode in which the coefficients of the syndrome and the erasure position are loaded into the corresponding registers, and the PM mode is a mode in which an operation for obtaining the corrected syndrome polynomial and the erasure position polynomial is executed. The SI mode is a mode in which the 0th order coefficient is set to a value of 1 and the operation result held in the register is shifted up. The SM mode is a mode in which the least significant register is set to 0.
In this mode, the operation result held in the register is shifted up.

FIG. 17 is a flowchart showing the mode switching in the EUC block 33.
As shown in (1), the EUC block 33 executes a series of processes by sequentially switching the mode from the PI mode to the PM mode, the SI mode, and the SM mode.

[0125] That EUC block 33, as shown in FIG. 18, at stage = 0, is set to the PI mode, first as an initial value, the syndrome S ₀ to S _p-1 to the registers of the A ₁ to A _p Are stored, and A _{p + 1 to} A _2p
Erasure position U ₁ ~U _p is stored for the register.
In the following, the respective registers constituting the shift register, sequentially shown by the sign of A ₀ to A _2p from division unit DIV.

A further following stage (0 <STAGE ≦
In ε), the PM mode is set and the disappearance position U _{1 is set.}
While shifting up the ~U _p, syndromes S ₀ ~S
The coefficient T of the modified syndrome polynomial is obtained by sequentially multiplying _p-1 by the erasure position (1-U _i ^-1 x) [1 ≦ i ≦ ε].
obtaining coefficients Yuipushiron～u ₁ of _p-1 through T ₀ and the erasure position polynomial.

The following stage (ε <STAGE ≦ P)
In, the mode is set to the SI mode or the SM mode, and each coefficient is shifted up by p−ε times and output. At this time, it is checked whether the value of the register A ₁ is 0, and A ₁ = 0
If A ₁ ≠ 0, decode fail
r (signal error) is notified to the host controller. In the SI mode, U ₀ = 1 is set to A _2P in advance.

More specifically, in comparison with FIGS.
As shown in FIGS. 19 and 20, when p = 6 and ε = 6,
In this case, the EUC block 33
Star A ₀ ~ A₆ Syndrome S₀ ~ S₆ Is stored,
Register A₇ ~ A₁₂Disappearing position U₁ ~ U₆ Is stored
It is. Furthermore, the highest register A₀ And register A₇ ~
A₁₂The shift process is performed between
Register A₁₂Is reset to the value 0, the state of stage 1
Is formed. In PM mode, the same cash register
Star A₀ And A₇ ~ A₁₂Shift processing is performed between
With register A₁ ~ A_Five In the lower register
TA A_Two ~ A₆ Galois operation with the contents of
By resetting, the state of stage 2 is formed
You. Here, Syndrome S₆ A that holds
₆ Is held in the hold state, and the lowest register A₁₂
Sets the operation result of the Galois divider (DIV)
You.

Subsequently, similarly, the registers A ₀ and A ₇
Treatment shifted between to A ₁₁ are executed, also register A
In ₁ to A _5, by re-setting the Galois operation on the operation result between the contents of register A ₂ to A ₆ of the lower side, the state of the stage 3 is formed. Here, the register A ₆ holding the syndrome S ₆ is held in a hold state, and the lowest register A ₁₂ is a Galois divider (D
Operation results, followed by the register A ₁₁ of IV) are Galois operation result between the lowest register A ₁₂ is set.

As described above, the registers are sequentially switched, and the processing of hold, shift, and operation is repeated, so that the EUC block 33 sequentially switches the stages. Note that FIGS. 22 and 23 correspond to FIG.
21 is a state transition in the case of p = 6 and ε = 2 shown by comparison with FIG.

[0131] The correction syndrome
The coefficients of the phase polynomial T and the erasure position polynomial are shown in FIG.
It is expressed as follows. The highest of the modified syndrome polynomial
Coefficient is always in register A₁ And also vanishing position polynomial
The highest order coefficient of the equation is always in register A_{P + 1} Be stored in
become. However, when p = ε, the vanishing position polynomial
The zero-order coefficient is omitted, and the ε-order to first-order of the erasure position polynomial
Only coefficient is register A _{P + 1} ~ A_2PIs stored in to this
Therefore, even if the register is composed of 2p stages, p ≦ ε
Under the condition, decoding can be performed.

(1-2) Effects of the First Embodiment According to the above configuration, the Euclidean arithmetic function that is unnecessary when only erasure correction is performed is deleted, and a configuration corresponding to this deletion is provided. Thus, the erasure correction can be specialized for the erasure correction with a simple configuration.

That is, by using a Galois field adder, a Galois field multiplier, and a cascade connection of units by registers, an error evaluation polynomial and an error locator polynomial are obtained from a corrected syndrome polynomial and an erasure locator polynomial. An error evaluation polynomial and an error locator polynomial can be obtained, and erasure correction can be performed specifically for erasure correction with a simple configuration.

At this time, the zeroth-order term of the erasure position polynomial is set to be always 1, and the number of units is set to 2 × p for the maximum value p + 1 of the coefficients of the erasure position polynomial. This can simplify the overall configuration.

The number of disappearances ε of the modified syndrome polynomial
If the coefficient equal to or greater than the next is other than 0, the overall configuration can also be simplified by outputting that it is a decode failer.

(2) Second Embodiment In this embodiment, a so-called multiplexing configuration is applied to an EUC block. That is, in the EUC block, one Galois field arithmetic unit is used in time division for calculating a plurality of coefficients, so that the Galois field arithmetic unit is shared for the calculation of the plurality of coefficients, and the circuit configuration of the EUC block is accordingly reduced. Simplify.

That is, if the multiplicity by time division is set to L, in the configuration by multiplexing, one Galois field divider, (2 × p) / L Galois field multipliers, (2 × p) /
L Galois field adders, ((L + 1) × (2 × p) /
L) +3 registers can form an EUC block, and the circuit configuration can be simplified accordingly. Thus, by comparison with the conventional erasure correction, ((L
-1) × (2 × p) / L) registers can be reduced, and the configuration of the control circuit can be simplified accordingly.

FIGS. 24 to 28 are connection diagrams showing EUC blocks applied to the erasure correction dedicated circuit according to this embodiment. In this embodiment, the division unit D
The IV is configured such that a predetermined register output (FIG. 27) or an output of the register 37 assigned to the multiplication and addition unit MLT by the switch 54 can be selectively set in the register 37. Further, a register 38 is controlled by the switch 36.
, And a reset value of logic 1 can be selectively set in the register 38. The output of the divider 39 can be output to the multiplication and addition unit MLT via the switch 55 and the register 56, and the output can be held.

On the other hand, the multiplication / addition unit MLT
It is formed by cascade connection of units having the basic configuration shown in FIG. Here, in this unit, three stages of registers 57, 58, 59 corresponding to the multiplicity L are arranged in series with switches 60, 61, 62 on the input side. In this unit, the output of the division unit DIV, the reset value of the logic 0, and the reset value of the logic 1 are selected by the switch 63 and input to the multiplier 64. The output of the arranged register 58 is multiplied. The output of the register 57 at the uppermost stage and the reset value of logic 0 are selected by the switch 66 and input to the adder 67. The adder 67 multiplies the output of the multiplier 64 by the selector 67 and outputs the result to the switch 62 at the lowermost stage. input.

Switch 6 of each register 57, 58, 59
Reference numerals 0, 61, and 62 are configured to select the corresponding polynomial coefficient and the register output at the subsequent stage. In the last switch 62, the reset value of the logic 1 and the adder 6
7 can be selected. The switch 60 at the uppermost stage is capable of selecting the output of the adder 67 via the switch 73 and the register 74, and the value held by this output.

With these, in the unit, FIG.
By setting the switches 60 to 62 as shown in
The coefficient of the syndrome polynomial and the coefficient of the erasure position polynomial can be set in corresponding registers. EU
The C block 53 is configured to operate by switching the same mode as described above in the first embodiment, and the setting shown in FIG. 30 is set in the load mode in the PI mode and the like described in the first embodiment. Is made to correspond to the processing.

In the hold processing corresponding to the SI and SM modes, data is transferred between the registers 57 to 59 and 74 of each unit as shown in FIG. The settings of the switches 60 to 62, 63, and 73 corresponding to each cycle SYC in FIG. 31 are shown in FIGS. The shift in the PI mode is executed by the repetitive processing shown in FIG. The settings of the switches 60 to 62, 63, and 73 corresponding to each cycle SYC in FIG. 36 are shown in FIGS.

The calculation process in the PM mode is performed by the repetitive process shown in FIG.
The settings of the switches 60 to 62, 63 and 73 corresponding to each cycle SYC in FIG. 41 are shown in FIGS. In addition, the shift processing involving the arithmetic processing is performed by the repetitive processing shown in FIG.

According to this embodiment, one Galois field arithmetic unit is used in a time division manner for the operation of a plurality of coefficients, and is shared by the operation of a plurality of coefficients. It can be simplified.

(3) Other Embodiments In the above embodiment, the number of parities p = 6
However, the present invention is not limited to this and can be widely applied to various parity numbers.

Further, in the above-described embodiment, the case where the multiplicity is set to 3 has been described. However, the present invention is not limited to this, and can be widely applied to various multiplicity.

[0147]

As described above, according to the present invention, the Euclidean arithmetic function that is unnecessary when only erasure correction is performed is deleted, and a configuration corresponding to this deletion is provided.
With a simple configuration, erasure correction can be performed specifically for erasure correction.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an erasure correction processing procedure according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an erasure correction dedicated circuit according to the processing procedure of FIG. 1;

FIG. 3 is a time chart showing the processing procedure of FIG. 1 in comparison with a conventional processing procedure.

FIG. 4 is a connection diagram illustrating an EUC block in the erasure correction dedicated circuit of FIG. 2;

FIG. 5 is a connection diagram showing a continuation of FIG. 4;

FIG. 6 is a connection diagram showing a continuation of FIG. 5;

FIG. 7 is a connection diagram showing a continuation of FIG. 6;

FIG. 8 is a connection diagram showing a continuation of FIG. 7;

FIG. 9 is a table provided for explaining a lost position in the EUC block in FIG. 4;

FIG. 10 is a connection diagram showing a basic configuration of a unit in the EUC block in FIG. 3;

11 is a diagram showing a connection in a unit clearing process of FIG. 10;

12 is a diagram showing connections in processing for loading a unit in FIG. 10;

FIG. 13 is a diagram showing connections in a shift process of the unit in FIG. 10;

FIG. 14 is a diagram illustrating connections in a hold process of the unit in FIG. 10;

FIG. 15 is a diagram showing connections in the arithmetic processing of the units in FIG. 10;

FIG. 16 is a table provided for describing modes in the EUC block in FIG. 4;

17 is a flowchart for explaining a mode transition in the EUC block in FIG. 4;

FIG. 18 is a schematic diagram for explaining a transition of the mode in FIG. 17;

FIG. 19 is a schematic diagram showing register changes corresponding to the mode transitions in FIG. 17;

FIG. 20 is a schematic diagram showing a continuation of FIG. 19;

FIG. 21 is a schematic diagram showing a case where ε = 2 in comparison with FIG. 19;

FIG. 22 is a schematic diagram showing a continuation of FIG. 21;

FIG. 23 is a table showing the contents of registers in the EUC block of FIG. 4;

FIG. 24 is a connection diagram showing an EUC block applied to the erasure correction dedicated circuit according to the second embodiment of the present invention.

FIG. 25 is a connection diagram showing a continuation of FIG. 24;

FIG. 26 is a connection diagram showing a continuation of FIG. 25;

FIG. 27 is a connection diagram showing a continuation of FIG. 26;

FIG. 28 is a connection diagram showing a continuation of FIG. 27;

FIG. 29 is a connection diagram showing a basic configuration of a unit in the EUC block in FIG. 24;

FIG. 30 is a diagram showing connections in processing for loading a unit in FIG. 29;

FIG. 31 is a diagram showing a change in the contents of a register in the hold processing of the unit shown in FIG. 29;

FIG. 32 is a diagram showing connections in hold processing of the unit in FIG. 29;

FIG. 33 is a connection diagram showing a continuation of FIG. 32;

FIG. 34 is a connection diagram showing a continuation of FIG. 33.

FIG. 35 is a connection diagram showing a continuation of FIG. 34;

36 is a diagram illustrating a change in the contents of a register in the shift processing of the unit in FIG. 29.

FIG. 37 is a diagram showing connections in the processing of shifting the units in FIG. 29;

FIG. 38 is a connection diagram illustrating a continuation of FIG. 37;

FIG. 39 is a connection diagram showing a continuation of FIG. 38;

FIG. 40 is a connection diagram showing a continuation of FIG. 39.

FIG. 41 is a diagram showing changes in the contents of registers in the arithmetic processing of the unit shown in FIG. 29;

FIG. 42 is a diagram showing connections in the arithmetic processing of the units in FIG. 29;

FIG. 43 is a connection diagram showing a continuation of FIG. 42;

FIG. 44 is a connection diagram showing a continuation of FIG. 43.

FIG. 45 is a connection diagram showing a continuation of FIG. 44;

FIG. 46 is a diagram showing a change in the contents of a register in an arithmetic process involving a shift process of the unit in FIG.

FIG. 47 is a flowchart showing a processing procedure of a conventional erasure correction process.

48 is a block diagram illustrating an erasure correction circuit according to the processing procedure of FIG. 47.

FIG. 49 is a connection diagram showing an EUC block applied to the erasure correction circuit of FIG. 48;

FIG. 50 is a connection diagram showing a continuation of FIG. 49;

FIG. 51 is a connection diagram illustrating a sequel to FIG. 50;

FIG. 52 is a connection diagram showing a continuation of FIG. 51.

FIG. 53 is a connection diagram showing a continuation of FIG. 52;

FIG. 54 is a connection diagram showing EUC blocks related to multiplexing.

FIG. 55 is a connection diagram showing a sequel to FIG. 54;

FIG. 56 is a connection diagram showing a continuation of FIG. 55;

FIG. 57 is a connection diagram showing a continuation of FIG. 56.

FIG. 58 is a connection diagram showing a continuation of FIG. 57;

FIG. 59 is a connection diagram showing a continuation of FIG. 58;

[Explanation of symbols]

1 ... Erasure correction circuit, 2 ... SYN block, 3, 3
3, 53 ... EUC block, 4, 34 ... CHS block

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5B001 AB02 AC01 AD03 AD06 AE02 5J065 AC02 AC03 AD01 AG01 AG02 AH02 AH03 AH05

Claims (9)

[Claims] A first step of obtaining a syndrome polynomial from input data; a second step of obtaining an erasure position polynomial from an erasure flag corresponding to the input data; and a modified syndrome polynomial from the syndrome polynomial and the erasure position polynomial. A third step of obtaining an error evaluation polynomial and an error locator polynomial from the modified syndrome polynomial and the erasure position polynomial; a fifth step of obtaining an error position and an error value from the error locator polynomial and the error evaluation polynomial And a sixth step of correcting an error of the input data using the error position and the error value. 2. The erasure-only correction according to claim 1, wherein the fifth step outputs a decoding failure when a coefficient equal to or more than the number of erasures ε of the modified syndrome polynomial is other than 0. Method. 3. A first step of obtaining a syndrome polynomial from input data; a second step of obtaining an erasure position polynomial from an erasure flag corresponding to the input data; and a modified syndrome polynomial from the syndrome polynomial and the erasure position polynomial. A third step of obtaining an error evaluation polynomial and an error locator polynomial from the modified syndrome polynomial and the erasure position polynomial; a fifth step of obtaining an error position and an error value from the error locator polynomial and the error evaluation polynomial And a sixth step of correcting an error in the input data using the error position and the error value. 4. A first step of obtaining a syndrome polynomial from input data; a second step of obtaining an erasure position polynomial from an erasure flag corresponding to the input data; and a modified syndrome polynomial from the syndrome polynomial and the erasure position polynomial. A third step of obtaining an error evaluation polynomial and an error locator polynomial from the modified syndrome polynomial and the erasure position polynomial; a fifth step of obtaining an error position and an error value from the error locator polynomial and the error evaluation polynomial And a sixth step of correcting an error in the input data by using the error position and the error value. 5. A first calculating means for obtaining a syndrome polynomial from input data; a second calculating means for obtaining a erasure position polynomial from an erasure flag corresponding to the input data; and a correction syndrome from the syndrome polynomial and the erasure position polynomial. Third operation means for obtaining a polynomial; fourth operation means for obtaining an error evaluation polynomial and an error position polynomial from the modified syndrome polynomial and the erasure position polynomial; and error position and error value from the error position polynomial and the error evaluation polynomial. A circuit dedicated to erasure correction, comprising: fifth calculating means for determining; and sixth calculating means for correcting an error in the input data using the error position and the error value. 6. The erasure correction circuit according to claim 5, wherein said fourth arithmetic means is formed by a cascade connection of units by a Galois field adder, a Galois field multiplier, and a register. 7. The fourth calculating means sets the zero-order term of the erasure position polynomial to be always one, and sets the unit to the maximum value p + 1 of coefficients of the erasure position polynomial. 7. The erasure correction dedicated circuit according to claim 6, wherein the number is set to 2 × p. 8. The erasure correction according to claim 5, wherein said fifth arithmetic means outputs a decoding failure when a coefficient equal to or larger than the number of erasures ε of the modified syndrome polynomial is not 0. Dedicated circuit. 9. The method according to claim 5, wherein said fourth arithmetic means uses one Galois field arithmetic unit in a time-division manner for calculating a plurality of coefficients and shares the calculation with the plurality of coefficients. The erasure correction dedicated circuit described.