JP2002329673A - Semiconductor crystal film, its manufacturing method, semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a polycrystalline film which acts as an SiGeC layer wherein a C atom is made to enter a lattice position in composition in which Ge composition ratio is high. SOLUTION: A multilayer film is formed wherein an Si1-x1-y1 Gex1 Cy1 layer (0<=x1<1, 0<y1<1) which has composition in which Ge composition ratio is small and an Si1-x2-y2 Gex2 Cy2 layer (0<x2<=1, 0<=y2<1) (x1<x2, y1>y2, x1 and x2 do not become 0 simultaneously) which has composition in which Ge composition ratio is large are laminated. As a result, a range in which function as an SiGeC layer is enabled in a condition that a C atom is made to enter a lattice position is enlarged as far as a range in which Ge composition ratio is high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor crystal film containing Si, C, and Ge and having high crystallinity, a method of manufacturing the same, a semiconductor device including the semiconductor crystal film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices using Si crystals have been successively realizing multifunctionality and high-speed performance mainly due to miniaturization of semiconductor elements such as transistors. In the future, of course, it is necessary to further reduce the size of semiconductor elements in order to improve the performance of semiconductor devices, but in order to achieve this goal, other than miniaturization of semiconductor devices, There are many other challenges that must be overcome technically.

For example, even if the miniaturization of a semiconductor element progresses, the highest performance of a semiconductor device is limited by physical properties (eg, mobility) of a material called Si. In other words, as long as a material called Si crystal is used,
It can be said that it is difficult to dramatically improve device performance.

In recent years, semiconductor devices capable of high-speed operation have been developed.
Semiconductor device using a mixed crystal semiconductor of group IV element
Attention has been focused on conductive devices. Among them, contains C
Group IV element Si_1-xy Ge_x C_y Crystal (0 <x <
1,0 <y <1 (hereinafter also referred to as SiGeC)
Research has recently been actively conducted. Si_1-
xy Ge_x C_y Crystals have recently been used as semiconductor device materials.
Practically used Si _1-x Ge_x Crystal (0 <x <1)
(Hereinafter also referred to as SiGe) as an improved material
Can be. And Si_1-xy Ge_x C_y The crystal is
It has been found that it has the following excellent properties
I have.

[0005] Si _1-x Ge _x crystals that have already been put to practical use are materials having a larger lattice constant than Si crystals. Therefore, to form a heterojunction formed by laminating a Si _1-x Ge _x crystal layer on the Si crystal layer, Si _1-x Ge _x extremely large compressive strain in the crystal layer is generated. When the compressive strain exceeds a limit of a film thickness called a critical film thickness (an upper limit value of a film thickness that can be deposited without generating a transition), Si _1-x Ge _x
A phenomenon occurs in which stress is relaxed while dislocation occurs in the crystal layer. Further, when the thickness is close to the critical thickness, stress relaxation accompanied by dislocation may occur when heat treatment is performed, even though the critical thickness is not exceeded. Also, the Si crystal layer and S
When the i _1-x Ge _x crystal layer paying attention to the band structure of the heterojunction formed by laminating the band offset (hetero barrier)
Is generated only at the valence band edge of the Si _{1- x} Ge _x crystal layer. This is because when a high-speed MIS transistor using a Si _1-x Ge _x crystal layer as a channel is manufactured, a p-channel type M
This means that only IS transistors can be manufactured.

However, when C is added to this Si _1-x Ge _x crystal, since C is an element having a smaller atomic radius than Si and Ge, it is necessary to reduce the lattice constant of the crystal and reduce the strain. Can be. Then, Si _{1-x- y} Ge _x C _y to which C is added in an amount of about ８ of the Ge composition ratio is substantially lattice-matched to the Si crystal. In addition, since the strain accumulated in the Si _1-x Ge _x crystal can be reduced, the thermal resistance also increases. Moreover, Si _{1-in xy} Ge _x C _y crystal layer and the Si crystal layer and the heterojunction structure formed by laminating the composition Ge composition ratio and the C composition ratio is high (Ge composition ratio of several tens atm.%, C
In the composition ratio is one having atm.% Or more), Si _1-xy G
e _x C both _y valence band edge and the conduction band edge of the crystal is reported that the band offset occurs in the (K.Brunner et a
l., J. Vac. Sci. Technol. B16, 1701 (1998)). In this case, the confinement of carriers occurs at both the conduction band edge and the valence band edge, so that not only a p-channel transistor but also an n-channel transistor can be manufactured. In addition to the above, it is known that C also has a boron (B) diffusion suppressing effect. This property functions very effectively in manufacturing a semiconductor device in which the boron profile needs to be appropriately controlled, and is also useful in stabilizing the manufacturing process of the semiconductor device. For example, in manufacturing ultra-high speed npn bipolar transistors having a narrow base region (ie, a thin layer) or field effect transistors having a δ-doped layer, by using a semiconductor layer containing C in the boron-doped region, The diffusion of boron due to the heat treatment is prevented, and a device having a doping profile as designed can be manufactured.

[0007]

As described above, Si _1-xy Ge _x C _y , which is a group IV crystal containing C, is composed of Si or S
It is a material having properties superior to i _1-x Ge _x . However, since C has unique properties as described below, the production of high-quality Si _1-xy Ge _x C _y crystal, S
Harder than i _1-x Ge _x crystals. First, since the solid solubility of C atoms with Si and Ge is very low (in a thermal equilibrium state, about 10 ¹⁷ atm.cm ^-3 in Si crystal and about 10 ⁸ in Ge crystal).
Atm.Cm ^-3), Preparation of Si _1-xy Ge _x C _y crystal containing C of high composition ratio (atm.% order) is difficult by the thermal equilibrium state, such as melting method. Further, C atoms have a property that they can easily enter not only at the lattice position of the crystal but also between the lattices, so that the crystallinity is easily broken. Furthermore, C
Tend to selectively bond with Si, so that Si _1-xy
In the Ge _x C _y crystal, a structure close to crystalline silicon carbide or amorphous silicon carbide is likely to be generated. As a result, such a local structure causes Si _1-xy Ge _x C
_The crystallinity of the _y crystal tends to deteriorate.

Therefore, conventionally, MBE (Molecular Be
am Epitaxy) and CVD (Chemical Vapor Depositi)
on) method, the Si _1-xy Ge _x C _y
Crystals have been produced. Recently, studies using the CVD method have become mainstream because the MBE method is not suitable for mass production.

The CVD method is a method of heating a Si substrate in a vacuum vessel, introducing a source gas in that state, and thermally decomposing the source gas to grow crystals on the substrate. Si
When making a _1-xy Ge _x C _y crystal, a Si raw material as monosilane (SiH ₄₎ or disilane (Si ₂ H ₆₎ silane gas such as (typically one gas), germane as Ge raw material (GeH ₄ ) and a gas containing C (generally, one kind of gas) such as monomethylsilane (SiH ₃ CH ₃ ) or acetylene (C ₂ H ₂ ) as a C raw material is simultaneously supplied into a vacuum vessel. However, even when such a method is used, at any composition ratio of C, C becomes S
It does not necessarily enter the lattice position of the i _1-xy Ge _x C _y crystal, but there is a certain limit value for the composition ratio of C in the lattice position. Beyond this limit, an attempt to incorporation of C in Si _1-xy Ge _x C _y crystal, crystalline Si _1-xy Ge _x C _y crystal is significantly reduced. In particular, Si with high defect-free high crystallinity that can be applied to semiconductor devices
_1-xy Ge _x C _y crystal, at present, that C composition ratio can not be realized unless less about 2 atm.%.

The present inventors have been conducting research for grasping the upper limit of the C composition ratio, and at present the following facts have been clarified.

From the research of the present inventors, it has been found that Si _1-xy Ge
the maximum value of the C composition ratio entering the grid position _x C _y in the crystal, G
It has been clarified by the inventors' studies that it changes depending on the e composition ratio (Kanzawa et al., Appl. phys.
Lett. 77, 3962 (2000)).

FIG. 1 is a graph showing the dependency of the maximum value (upper limit) of the C composition ratio at the lattice position in a single-layer SiGeC crystal on the Ge composition ratio. In the figure, the horizontal axis is SiGe
The vertical axis represents the maximum value (upper limit) of the C composition ratio that can be placed in the crystal lattice position. This data is based on the ultra-high vacuum chemical vapor deposition (UHV-
This shows the result when a single-layer SiGeC crystal is deposited on a Si substrate by a CVD method. Si ₂ H ₆ , GeH ₄ , and SiH ₃ CH ₃ were used as source gases.
The temperature of the substrate during growth is 490 ° C. As can be seen from this figure, for example, in a crystal having a Ge composition ratio of about 13 atm.%, C enters the lattice position up to about 1.9 atm.%, But when the Ge composition rate is about 35 atm.%, It can be seen that C can be contained only at about 0.8 atm.%. That is, it means that the higher the Ge composition ratio, the lower the upper limit of the C composition ratio. This is Ge
This is considered to be due to the incompatibility between the atom and the C atom, that is, the mutual exclusion of the two. Further, extrapolating the data of FIG. 1, when the Ge composition ratio exceeds about 50 atm.%, The C composition ratio in the lattice position of the crystal becomes almost 0%.
It is expected to be close to atm.%. That is, FIG.
By the CVD method under the conditions to obtain a result of the Si _1-xy Ge _x C _y crystal Ge composition ratio exceeds 50 atm.%,
C cannot be mixed. However, FIG.
Is only under a certain condition, and it is considered that C having a composition ratio of up to about 2.5 atm.% Almost enters the lattice position depending on the apparatus and process conditions.

An object of the present invention is to provide a high crystallinity and C
An object of the present invention is to provide a semiconductor crystal film functioning as a SiGeC layer having a high composition ratio, a method of manufacturing the same, a semiconductor device having the semiconductor crystal film, and a method of manufacturing the same.

[0014]

The semiconductor crystal film of the present invention is constituted by alternately laminating a plurality of semiconductor layers having mutually different compositions a plurality of times, and comprises a multilayer film functioning as a single SiGeC layer. In the semiconductor crystal film, the plurality of semiconductor layers are Si _1-x1-y1 Ge _{x1 Cy 1} layers (0 ≦ x1
<1, 0 <y1 ≦ 1) and a Si _1-x2-y2 Ge _{x2 Cy2} layer (0 <x2 ≦ 1, 0 ≦ y2 <1) (x1 <x2, y1>)
y2, x1 and y2 do not become 0 at the same time).

This makes it possible to include C having a high composition ratio in a lattice position in Ge having a high composition ratio as compared with the case of forming a single-layer SiGeC layer.
Therefore, the distortion can be adjusted by adding C,
A multilayer film functioning as a SiGeC layer containing Ge with a high composition ratio is obtained. That is, a semiconductor device such as a high-performance transistor utilizing a large band gap difference between the Si layer and the multilayer film can be formed.

Since each semiconductor layer in the multilayer film is thinner than a thickness at which discrete quantization levels are generated, the function as a single SiGeC layer of the multilayer film can be easily obtained.

The Si _1-x1-y1 Ge _x1 C _y1 layer is made of SiGe
When a C layer, said _{Si 1-x2 -y2 Ge x2 C} y2 layer may be a SiGe layer or the SiGeC layer.

When the Si _1-x1-y1 Ge _x1 C _y1 layer is a SiC layer, the Si _1-x2-y2 Ge _x2 C _y2 layer is Si
It is a GeC layer.

The multilayer film can contain more C than the upper limit of the C composition ratio at a certain Ge composition ratio determined by the device and process conditions in the single-layer SiGeC layer.

The Si _1-x1-y1 Ge _{x1 Cy 1} layer and the S
The thickness of the _{i 1-x2-y2 Ge x2} C y2 layers, are all preferably 3nm or less.

The Si _1-x1-y1 Ge _x1 C _y1 layer and the S
The thickness of the _{i 1-x2-y2 Ge x2} C y2 layers are all 1.5nm
It is more preferred that:

The multilayer film has a Si composition having a Ge composition ratio of 30 atm.% Or more and a C composition ratio of 1.2 atm.% Or more.
It can function as a GeC layer.

The semiconductor device according to the present invention is constituted by alternately laminating a base semiconductor layer containing at least Si and a plurality of semiconductor layers formed on the base semiconductor layer and having mutually different compositions a plurality of times, A multi-layer film serving as an active region functioning as a single SiGeC layer, wherein the multi-layer film is a Si _1-x1-y1 Ge _{x1 Cy 1} layer (0 ≦ x1 <1,0 < y1 ≦ 1) and Si _1-x2-y2 Ge
_x2 C _y2 layer (0 <x2 ≦ 1, 0 ≦ y2 <1) (x1 <x
2, y1> y2, and x1 and y2 do not become 0 at the same time).

This makes it possible to include C having a high composition ratio in a lattice position in Ge having a high composition ratio as compared with the case of forming a single-layer SiGeC layer.
Therefore, the distortion can be adjusted by adding C,
A multilayer film functioning as a SiGeC layer containing Ge with a high composition ratio is obtained. That is, a semiconductor device such as a high-performance transistor utilizing a large band gap difference between the Si layer and the multilayer film can be obtained.

Each semiconductor layer in the above multilayer film is thinner than a thickness at which discrete quantization levels are generated, so that a single Si layer is formed.
A semiconductor device having a multilayer film having a function as a GeC layer as an active region can be easily obtained.

The Si _1-x1-y1 Ge _x1 C _y1 layer and the S
The thickness of the _{i 1-x2-y2 Ge x2} C y2 layers, are all preferably 3nm or less.

The Si _1-x1-y1 Ge _x1 C _y1 layer and the S 1
The thickness of the _{i 1-x2-y2 Ge x2} C y2 layers are all 1.5nm
It is more preferred that:

The multilayer film has a Si composition having a Ge composition ratio of 30 atm.% Or more and a C composition ratio of 1.2 atm.% Or more.
It can function as a GeC layer.

The semiconductor device of the present invention can be a MISFET in which the above-mentioned multilayer film functions as a channel or a bipolar transistor in which the above-mentioned multilayer film functions as a base layer.

According to the method of manufacturing a semiconductor crystal film of the present invention, a plurality of semiconductor layers having mutually different compositions are alternately laminated a plurality of times, and the semiconductor crystal film comprises a multilayer film functioning as a single SiGeC layer. The method of claim ₁ , wherein a Si _{1-x1-y 1} Ge _{x1 Cy 1} layer (0 ≦ x1
<1,0 <y1 ≦ 1) and a Si _1-x2-y2 Ge _{x2 Cy2} layer (0 <x2 ≦ 1,0 ≦ y2 <1) (x1 <x2, y1>)
ya, x1 and y2 do not simultaneously become 0), and (a) epitaxially growing one of the semiconductor layers; and forming the Si layer on the one semiconductor layer.
Step (b) of epitaxially growing the other of the _1-x1-y1 Ge _x1 C _y1 layer and the Si _1-x2-y2 Ge _x2 C _y2 layer
And contains multiple times.

According to this method, a semiconductor crystal film which is a multilayer film having the above-described functions can be easily formed.

In the steps (a) and (b), it is preferable that each semiconductor layer in the multilayer film is epitaxially grown to be thinner than a thickness at which discrete quantized levels are generated.

In the steps (a) and (b), at least one of the semiconductor layers in the multilayer film is epitaxially grown to a thickness exceeding 1.5 nm, and the step of heat-treating the multilayer film is further performed. By including, even when one of the semiconductor layers in the multilayer film has a thickness that causes discrete quantization levels during the deposition of the multilayer film, the entire multilayer film can function as a single SiGeC layer by heat treatment. Can be.

In the above steps (a) and (b), Si, G
In the step of epitaxially growing a semiconductor layer containing e and C, it is preferable to thermally decompose a disilane gas or a monosilane gas, a germane gas, and a monomethylsilane gas.

According to the method of manufacturing a semiconductor device of the present invention, an underlying semiconductor layer containing at least Si and a plurality of semiconductor layers formed on the underlying semiconductor layer and having mutually different compositions are alternately laminated a plurality of times. Composed of a single SiGeC
A method for manufacturing a semiconductor device comprising a multilayer film serving as an active region functioning as a layer,
Si _1-x1-y1 Ge _x1 C _y1 layer (0 ≦ x1 <1, 0 <y1 ≦
1) and a Si _1-x2-y2 Ge _x2 C _y2 layer (0 <x2 ≦ 1,0
.Ltoreq.y2 <1) (x1 <x2, y1> y2, x1 and y2 do not simultaneously become 0), and (a) epitaxially growing one of the semiconductor layers; And a step (b) of epitaxially growing the other of the Si _1-x1-y1 Ge _{x1 Cy 1} layer and the Si _1-x2-y2 Ge _{x2 Cy 2} layer.

According to this method, a semiconductor device having a semiconductor crystal film, which is a multilayer film having the above functions, as an active region can be easily formed.

In the steps (a) and (b), it is preferable that each semiconductor layer in the multilayer film is epitaxially grown thinner than a thickness at which discrete quantized levels are generated.

In the steps (a) and (b), at least one of the semiconductor layers in the multilayer film is epitaxially grown to a thickness exceeding 1.5 nm, and a step of heat-treating the multilayer film is further performed. By including, even when one of the semiconductor layers in the multilayer film has a thickness that causes discrete quantization levels during the deposition of the multilayer film, the entire multilayer film can function as a single SiGeC layer by heat treatment. Can be.

In the above steps (a) and (b), Si, G
In the step of epitaxially growing a semiconductor layer containing e and C, it is preferable to thermally decompose a disilane gas or a monosilane gas, a germane gas, and a monomethylsilane gas.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
It is sectional drawing which shows schematically the structure of the multilayer film (semiconductor crystal film) which concerns on embodiment. In the present embodiment, on the Si substrate 11, a thickness of about 1 having a larger lattice constant than that of the Si crystal is used.
nm of Si _0.2 Ge _0.8 layer 12 and about 1 nm thick Si
_A thickness of about 100 n is formed by alternately depositing a _0.785 Ge _0.2 C _0.015 layer 13 a plurality of times (50 periods in the present embodiment).
A multilayer film 10A (semiconductor crystal film) functioning as a m-SiGeC layer is formed. Multilayer film 10A of the present embodiment
Is considered to be a superlattice structure with few discrete quantization levels. Hereinafter, a method for forming the multilayer film 10A will be described. FIGS. 3A to 3E are cross-sectional views illustrating steps of manufacturing a semiconductor crystal film according to the first embodiment of the present invention.

The Si _0.2 Ge _0.8 layer 12 and the Si _0.785 Ge
_In this embodiment, the UHV-CVD method is used for the deposition with the _0.2 C _0.015 layer 13. Generally, UHV-CV
When a crystal is epitaxially grown on a substrate by the D method, pretreatment of the substrate is very important. Therefore, the pretreatment of the Si substrate 11 will be described first.

First, in the step shown in FIG. 3A, a pre-cleaned Si substrate 11 is prepared. In the pretreatment of the Si substrate 11, the Si substrate 11 is washed with a mixed solution of sulfuric acid and hydrogen peroxide to remove organic substances and metal contaminants on the surface of the Si substrate 11. Next, the Si substrate 11 is washed with an ammonia-hydrogen peroxide aqueous solution to remove deposits on the surface of the Si substrate 11. Further, the natural oxide film on the surface of the Si substrate 11 is removed by cleaning using a hydrofluoric acid solution. At this time, foreign substances other than the oxide film in the natural oxide film on the surface of the Si substrate 11 are also removed.

Next, in the step shown in FIG. 3B, the Si substrate 11 is immersed again in an ammonia-hydrogen peroxide aqueous solution, and a thin protective oxide film 21 is formed on the surface of the Si substrate 11. Since the protective oxide film 21 covers the Si substrate 11 with a relatively uniform thickness, the protective oxide film 21 has a function of preventing foreign substances other than the oxide film from adhering to Si atoms of the Si substrate 11. Therefore, the protection oxide film 21 can facilitate exposing a clean surface of the Si substrate 11 before epitaxial growth.

Next, in the step shown in FIG.
The Si substrate 11 is placed in a chamber (not shown) of a crystal growth apparatus.
Zu). And once inside the chamber is 2 ×
10 ^-9Torr (≒ 2.7 × 10^-7Vacuum to about Pa)
And the Si substrate 11 is heated to 850 ° C. in a hydrogen gas atmosphere.
Heated every time. Thereby, the shape is formed on the surface of the Si substrate 11.
The formed protective oxide film is removed and a clean surface of the Si substrate 11 is removed.
The surface is exposed.

Next, the temperature of the Si substrate 11 is lowered to about 490 ° C., a source gas is introduced into the chamber, and crystal growth is started. In the present embodiment, first, a Si _0.2 Ge _0.8 layer 12 having a composition that can be sufficiently grown is epitaxially grown on a Si substrate 11 by a known method. At this time, in the chamber, the partial pressure of the Si ₂ H ₆ gas is about 7 × 10 ⁻⁵ Torr (≒ 9.3 × 10 ⁻³ Pa), and G
The partial pressure of eH ₄ gas is about 2.8 × 10 ⁻³ Torr (≒ 0.37
Pa), the flow rate of each gas is adjusted. By performing this process for about 5 seconds, a 1-nm-thick Si _0.2 Ge _0.8 layer 12 is formed.

Next, in the step shown in FIG. 3 (d), Si _0.2
On the Ge _0.8 layer 12, an epitaxial growth of the Si _0.785 Ge _0.2 C _0.015 layer 13 having a composition which can be sufficiently grown is performed by a known method. At this time, in the chamber, the partial pressure of the Si ₂ H ₆ gas is about 7 × 10 ⁻⁵ Torr (≒
9.3 × 10 ⁻³ Pa) and the partial pressure of GeH ₄ gas is about 1.
When the partial pressure of the SiH ₃ CH ₃ gas is about 1.3 × 10 ⁻⁵ Torr (≒ 1.7 × 10 ⁻² P) at 7 × 10 ⁻⁴ Torr (≒ 2.7 Pa).
The flow rate of each raw material gas is adjusted so as to become a). By performing this process for about 17 seconds, a 1 nm thick Si _0.785 Ge _0.2 C _0.015
Layer 13 is formed.

Next, in the step shown in FIG.
Under the same conditions as in (c) and (d), Si
Epitaxial growth of _0.2 Ge _0.8 layer 12 and Si
_0.785 Ge and a _0.2 C _0.015 layer 13 epitaxially grown alternately _{repeated, Si 0.2 Ge 0. 8 / Si} 0.785
A multilayer film 10A having a superlattice structure having a Ge _0.2 C _0.015 stacked structure as one cycle is formed. In the present embodiment, for example, 50 cycles of Si _0.2 Ge _0.8 / Si _0.785 G
A multilayer film 10A having a laminated structure of e _0.2 C _0.015 is formed.

By adopting such a laminated structure,
The following advantages are obtained. Past literature on superlattice structures
(Semiconductor and Semimetals Vol.24 (ACADEMIC PR
ESS, INC) p.29 Volume Editor RAYMOND DINGLE)
In the superlattice structure, the thickness of each layer forming the superlattice structure is
At 1.5 nm or less, there are no discrete quantization levels.
It is shown to function as one crystal. I
Therefore, as in the present embodiment, Si_0.2 Ge_0.8 Layer 1
2 and Si_0.785 Ge_0.2 C_0.015 Thickness of layer 13
Since the shift is also 1 nm, Si_0.4925Ge_0.5 
C_0.0075A multilayer film 10A functioning as a layer is obtained. One
That is, the composition of the multilayer film 10A is Si_0.2 Ge _0.8 Layer 12
And Si_0.785 Ge_0.2 C_0.015 Si, Ge with layer 13
Which is the average value of the respective composition ratios of C and C_0.4925Ge_0.5 
C_0.0075Becomes

As described above, the Ge composition ratio in the multilayer film 10A of the present embodiment is 35 atm.%, Which is the limit shown in FIG.
Is 50 atm. As described above, a single layer of S
Depending on the iGeC layer, almost no C enters the lattice position in the SiGeC crystal containing about 50 atm.% of Ge, but according to the present invention, the Ge composition ratio of 50 atm. % Of crystals can be produced.

Next, the concept of the present invention will be described.
As shown in FIG. 1, looking at the dependency of the upper limit value of the C composition ratio that can be formed as a single crystal on the Ge composition ratio, the higher the Ge content ratio, the lower the upper limit value is. Therefore, in the present invention, SiG having a relatively low Ge content is used.
The e-layer contains as much C as possible, and the SiGe layer having a relatively high Ge composition ratio contains as little C as possible or does not contain C. in _1-xy Ge _x C _y crystal is became possible to produce a multilayer film (semiconductor crystal film) having a composition difficult areas produced.

However, the Si _0.2 Ge _0.8 layer 12 and the Si _0.2 Ge _0.8 layer 12
_0.785 Ge _0.2 C _0.015 The thickness ratio with the layer 13 is 1: 1.
However, the thickness ratio between the two can be any value.

FIG. 4 is a sectional view schematically showing the structure of a multilayer film according to a modification of the first embodiment. In this modification, an Si _0.2 G layer having a thickness of about 1 nm
and e _{0. 8} layers 12, having a thickness of about 1.5 nm Si _0.785 Ge
_0.2 C _0.015 layer 13 alternately multiple times (in this modification,
40 cycles) SiGe deposited about 100 nm thick
A multilayer film 10B (semiconductor crystal film) functioning as a C layer is formed. The procedure for fabricating the multilayer film 10B of this modification is basically the same as the procedure for fabricating the first embodiment, and a description thereof will be omitted.

FIG. 5 is a diagram showing a composition range in which a single crystal can be formed by a conventional single-layer SiGeC layer, and a composition range of a multilayer film functioning as a SiGeC layer which can be formed by the present invention. As shown in the figure, Si _0.2 Ge _0.8
When the layer 12 and the Si _0.785 Ge _0.2 C _0.015 layer 13 are alternately laminated, the Si _0.2 Ge _0.8 layer 12 and the Si _0.785 G
e _0.2 C _{0.015 In} accordance with the thickness ratio with the layer 13, a straight line L1
A multilayer film functioning as a SiGeC layer having a composition ratio in any of the above points is obtained. For example, Si _0.2 G
_Assuming that the thickness ratio between the e _0.8 layer 12 and the Si _0.785 Ge _0.2 C _0.015 layer 13 is 1: 1, the multilayer film 10A functioning as a SiGeC layer having the composition at the point P11 shown in FIG.
(First embodiment) is obtained, Si _0.2 Ge _0.8 layer 12
The ratio of the thickness of the Si _{0. 785} Ge _0.2 C _0.015 layer 13 and 1: multilayered film 10B (first functioning as SiGeC layer having a composition in P15 points shown in FIG. 5 When 1.5
Modification of the embodiment) is obtained.

Then, for example, Si_0.965 Ge_0.01C
_0.025 It has a composition with an extremely small Ge composition like a layer
Si_1-x1-y1 Ge_x1C_y1Layer (0 ≦ x1 <1, 0 <y1
<1) and Si_0.01Ge_0.99Almost as close to Ge layer as layer
Si with high composition_1-x2-y2 Ge _x2C_y2Layer (0 <x2 ≦
1,0 ≦ y2 <1) (x1 <x2, y1> y2, x1
and y2 do not become 0 at the same time).
In accordance with the ratio of the thickness of the person on the straight line L2 shown in FIG.
As a SiGeC layer having a composition expressed by these points,
A functional multilayer film is obtained. That is, in the present invention
With the C atoms in the lattice position, the SiGeC layer
The range that can function as an enlarged area like the region R2 shown in FIG.
It will be done. However, a single SiGeC layer or Si
C composition in a state where C atoms in the C layer enter lattice positions
The upper limit of the rate is greater than the upper limit shown in FIG.
It is considered to be about 2.5 atm.%. In contrast, 1.5
Si with a thickness of less than nm_0.965 Ge_0.01C_0.025 layer
In the case of C composition ratio higher than 2.5 atm.
It is believed that C atoms can enter lattice positions. Accordingly
As shown by the broken line L3 in FIG.
Functions as a SiGeC layer with a growth rate exceeding 2.5 atm.%
It is considered that a multilayer film can be formed.

The Si _1-x1-y1 Ge _x1 C _y1 layer (0 ≦ x
1 <1, 0 <y1 ≦ 1) and a Si _{1- x2-y2} Ge _{x2 Cy2} layer (0 <x2 ≦ 1, 0 ≦ y2 <1) (x1 <x2, y1>)
y2, x1 and y2 do not become 0 at the same time), which may be in the lowermost layer and may be in any of the uppermost layers.

It is also possible to form a multilayer film functioning as a SiGeC layer by laminating a Si _1-y C _y layer (hereinafter also referred to as SiC) and a SiGe layer. However, when two layers having different compositions are stacked, the following advantages can be obtained by making one layer a SiGeC layer without fail as in the present invention. That is, the SiC layer and the SiC
In a multilayer film with a Ge layer, defects are likely to occur because crystal layers having greatly different lattice constants are alternately deposited. That is, since the SiC layer has a smaller lattice constant than Si, the SiC layer epitaxially grown on Si receives tensile strain. On the other hand, since the SiGe layer has a larger lattice constant than Si, the SiGe layer epitaxially grown on the Si substrate receives compressive strain. Moreover, the SiGe layer epitaxially grown on the SiC layer will receive even greater compressive strain than on the Si substrate. Therefore, when two crystals that are subjected to strains having different directions of tension and compression with respect to the Si layer are alternately deposited,
It is in a state where defects are likely to occur.

On the other hand, by forming at least one of the SiGeC layers as in the present invention, the compressive strain or the tensile strain can be reduced, so that a multilayer film (semiconductor crystal film) with few defects can be obtained. Become.

The growth rate of the SiC layer is low,
Since the growth rate of the eC layer can be higher than that of the SiC layer, in consideration of practical mass production, when two semiconductor layers are stacked, a combination of a SiGeC layer and a SiGe layer, or a SiGeC layer The combination is also preferable.

(Second Embodiment) In the first embodiment, the multilayer film of the present invention obtained by alternately epitaxially growing two crystal films having different compositions and the method of manufacturing the same have been described. In the embodiment, a multilayer film of the present invention obtained by alternately epitaxially growing three crystal films having different compositions will be described.

FIG. 6 is a sectional view schematically showing the structure of a multilayer film (semiconductor crystal film) according to the second embodiment. In this embodiment, the Si _0.2 Ge _0.8 layer 1 having a lattice constant larger than that of the Si crystal and having a thickness of about 1 nm is formed on the Si substrate 11.
2, a thickness of about 1nm Si _{0. 785} Ge _0.2 C _0.015 layer 1
3 and about _0.8 nm thick Si _0.832 Ge _0.15 C _0.018 layer 14
Are alternately deposited a plurality of times (in this embodiment, 33 periods) to form a multilayer film 10C (semiconductor crystal film) having a thickness of about 99 nm and functioning as a SiGeC layer. The multilayer film 10C of the present embodiment is also considered to have a superlattice structure having almost no discrete quantization levels. Hereinafter, a method for forming the multilayer film 10C will be described. However, also in the present embodiment, the manufacturing procedure of the multilayer film is almost the same as that of the first embodiment, so that the illustration of the steps is omitted.

In the present embodiment, also in front of the Si substrate 11
The processing is performed in the same procedure as in the first embodiment.
It is. Then, the temperature of the Si substrate 11 is reduced to about 490 ° C.
And introduce a source gas into the chamber to increase crystal growth.
Start. First, as in the first embodiment, a thickness of about 1 n
m Si_0.2 Ge_0.8 Layer 12 and about 1 nm thick Si
_0.785 Ge_0.2 C_0.015 Layer 13 and epitaxial growth
Is done.

Next, the Si_0.785 Ge_0.2 C_0.015 Layer 13
Has a composition that can be sufficiently grown by a known method.
Si_0.832 Ge_0.15C_0.018 Epitaxial growth of layer 14
Length is done. At this time, in the chamber, Si_Two 
H₆ Gas partial pressure is about 7 × 10 ^-FiveTorr (≒ 9.3 × 10^-3
Pa), GeH_Four Gas partial pressure is about 8.3 × 10^-FiveTorr
(≒ 1.1 × 10^-FourPa), SiH_Three CH_Three Minute of gas
Pressure is about 1.8 × 10^-FiveTorr (≒ 2.4 × 10^-2Pa)
Thus, the flow rate of each source gas is adjusted. And
This process is performed for about 35 seconds.
Is a 1 nm thick Si_0.832 Ge_0.15C_0.018 Layer 14
Is formed.

Thereafter, under the same conditions as those described above, S
i_0.2 Ge_0.8 Epitaxial growth of layer 12 and Si
_0.785 Ge_0.2 C_0.015 Epitaxial growth of layer 13
And Si _0.832 Ge_0.15C_0.018 Layer 14 epitaxy
Is alternately repeated to form Si_0.2 Ge_0.8 / S
i_0.785 Ge_0.2 C_0.015 / Si_0.832 Ge_0.15C
_0.018Multilayer with superlattice structure, with one cycle of laminated structure
The film 10C is formed. In the present embodiment, for example,
33 cycles of Si_0.2 Ge_0.8 / Si_0.785 Ge_0.2 C_0.
015 / Si_0.832 Ge_0.15C_0.018 Multi-layer structure
The layer film 10C is formed.

According to the present embodiment, S having a thickness of 99 nm
i _0.606 Ge _0.383 C Multilayer film 1 functioning as _0.011 layer
0C is obtained. That is, as can be seen from FIG. 5, in the single-layer SiGeC layer, the Ge composition ratio is about 38 atm.%.
In the SiGeC layer, only about 0.6 atm.% Of C atoms could enter the lattice position,
In the present embodiment, by combining three types of crystal layers, a multilayer film 10C (semiconductor crystal film) functioning as a SiGeC layer containing about 1.1 atm.% Of C atoms at lattice positions is obtained.

In each of the above embodiments, an example has been described in which two or three types of crystal layers having different compositions are formed as each crystal layer forming one period of the superlattice structure. It is not limited to such an embodiment. Therefore, the multilayer film of the present invention can be obtained by alternately laminating four or more types of crystal layers. However,
In that case, any one of the three or more crystal layers may be used.
One of the crystal _{layer, Si 1-x1 -y1 Ge x1} C y1 layer (0 ≦ x1 <
1,0 <y1 <1) and the Si _1-x2-y2 Ge _x2 C _y2 layer (0
<X2 ≦ 1, 0 ≦ y2 <1) (x1 <x2, y1> y
2) and Si _1-x1-y1 Ge _x1 C _y1 layer (0 ≦ x1 <1,0 <
y1 <1).

Note that three or more types of crystal layers are stacked to form Si
Even when a multilayer film functioning as a GeC layer is formed, the order of depositing the respective crystal layers is not limited, and the same effect can be obtained by depositing in any order.

Although not disclosed in each of the above embodiments, a Si buffer layer may be epitaxially grown between the multilayer film 10A, 10B or 10C and the Si substrate 11, or the multilayer film 10A, 10B or S above 10C
An i-cap layer may be deposited.

(Third Embodiment) Next, the multilayer film 10A functioning as the SiGeC film described in each of the above embodiments,
An example of a hetero bipolar transistor having 10B or 10C will be described.

FIG. 7 is a sectional view schematically showing the structure of an npn-type heterojunction bipolar transistor (HBT) according to the present embodiment. As shown in the figure, the HBT of the present embodiment is formed on an n ⁺ layer 31 containing a high concentration of an n-type dopant (for example, phosphorus) formed in a Si substrate 30 and epitaxially grown on the n ⁺ layer 31. A collector layer 33 made of a Si film containing a low-concentration n-type dopant (for example, phosphorus); a separation layer 32 made of a thermal oxide film for partitioning the collector layer 33; and a first deposited oxide formed on the separation layer 32 By filling the film 35 and the opening (base opening) of the separation layer 32 and the first deposited oxide film 35, the first deposited oxide film 35 is formed.
Film 36 that functions as a SiGeC layer and extends over
And the second deposited oxide film 37 formed on the multilayer film 36
And the opening (emitter opening) of the second deposited oxide film 37
An emitter layer 38 made of a Si film epitaxially grown on the multilayer film 36 and a polysilicon film formed on the emitter layer 38 and filling the opening (emitter opening) of the second deposited oxide film 37. An emitter extraction electrode 9a and a collector extraction electrode 9b formed on a region (collector extraction layer) of the collector layer 33 separated by the separation layer 32 and formed of a polysilicon film common to the emitter extraction electrode 9a. , An interlayer insulating film 41 made of a silicon oxide film formed on a substrate
And the emitter extraction electrode 3 penetrating through the interlayer insulating film 41.
9a, the multilayer film 36 and the plug 42 contacting the collector lead-out electrode 39b, and the interlayer insulating film 4
1, an emitter electrode 43e, a base electrode 43b, and a collector electrode 43c connected to the emitter lead electrode 39a, the multilayer film 36, and the collector lead electrode 39b via the plug 42, respectively.

FIG. 8 is an enlarged sectional view showing the structure of the emitter-base-collector junction shown in FIG. As shown in the figure, a multilayer film 36 functioning as a SiGeC layer formed on a collector layer 33 which is a Si layer.
Is formed by alternately depositing a Si _0.2 Ge _0.8 layer 36 a having a thickness of about 1 nm and a Si _0.785 Ge _0.2 C _0.015 layer 36 b having a thickness of about 1 nm a plurality of times (in this embodiment, 25 periods). Is about 50 nm. That is, the multilayer film 36 functions as a Si _0.4925 Ge _0.5 C _0.0075 layer. Further, the multilayer film 36 contains boron (B) which is a p-type dopant, and functions as a base layer. The emitter layer 38 formed on the multilayer film 36 has n
It contains arsenic (As) as a type dopant.

In the manufacturing process of the HBT of this embodiment, in the formation process of the multilayer film 36, the epitaxial growth of the Si _0.2 Ge _0.8 layer 36a and the Si _0.785 Ge _0.2 C _0.015 layer 36b according to the procedure described in the first embodiment.
In any of the epitaxial growths, diborane (B ₂ H ₆ ) is added. The other steps can be formed by using a known technique, and thus the description is omitted.

According to the HBT of this embodiment, the multilayer film 36 functioning as a base functions as a Si _0.4925 Ge _0.5 C _0.0075 layer containing a high Ge composition ratio of about 50 atm. A high hetero barrier is formed at the valence band edge and the conduction band edge.

FIG. 9 is an energy band diagram schematically showing a band structure when no bias is applied, in a cross section passing through the emitter layer 38, the multilayer film 36 functioning as a base layer, and the collector layer 33. As shown in the figure,
Since the multilayer film 36 functions as a SiGeC layer having a high Ge composition ratio, a large band gap difference between the multilayer film 36 and the emitter layer 38 and the collector layer, which are the Si layers on both sides, can be ensured. At the junction between the emitter layer 38 containing the n-type dopant and the base layer (multilayer film 36) containing the p-type dopant, the band offset ΔEc at the conduction band edge is set small, and the band offset ΔEv at the valence band edge is set large. can do. That is, even if the bias between the emitter and the base is low, a sufficiently large current due to electrons can be obtained, and the current due to holes flowing backward from the base to the emitter can be reduced. HBT is obtained. According to the simulations of the present inventors, the HBT based on the multilayer film of the present invention is 0.4
It can be driven at a low voltage of about 5V.

Considering that the driving voltage of the bipolar transistor having the Si base layer is about 0.7 V, it can be understood that the effect of reducing the driving voltage of the bipolar transistor is large.

According to the HBT of the present invention, since the multilayer film 36 functioning as the base layer contains about 0.75 atm.% Of C, the distortion of the entire multilayer film 36 functioning as the base layer is small. As a result, generation of crystal defects due to heat treatment during the process can be reduced. on the other hand,
Even if a single-layer SiGeC layer is to be formed, when the Ge composition ratio is about 50 atm.%, C can hardly be allowed to enter the crystal lattice position, so that defects are likely to occur and device characteristics deteriorate.

Further, since C is contained in the entire multilayer film 36, the diffusion of boron (B) can be effectively suppressed. It becomes easy to hold the profile as designed. And, since the base traveling time is shortened by thinning the multilayer film as the base layer,
A device that can operate at high speed is obtained. That is, by using the multilayer film of the present invention for an HBT, a high-speed transistor that can be driven at a low voltage and has a thin base can be manufactured.

Fourth Embodiment FIG. 10 shows a heterojunction MISFET using a multilayer film functioning as a SiGeC layer as a p-channel according to a fourth embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a structure of (HMISFET).

As shown in the figure, the HMIS of this embodiment
The FET has an n-well 61 formed on a Si substrate 50.
It is provided above.

Then, a silicon layer is formed on the n-well 61.
62 and 1 nm thick Si_0.2 Ge _0.8 Layer and thickness 1nm
Si_0.785 Ge_0.2 C_0.015 And stack the layers for 10 cycles
20 nm thick multilayer film 63 and silicon cap layer
64 are sequentially laminated by the UHV-CVD method.
Then, the multilayer film 63 is formed from a film common to the multilayer film 53.
And the overall Si_0.4925Ge_0.5 C_0.0075layer
Functioning as a channel region where holes travel
Function. In addition, a silicon cap layer 64 has a silicon
Silicon formed by thermal oxidation of the reconcap layer 64
A gate insulating film composed of a silicon oxide film is provided.
And a gate electrode 66 is further formed thereon.
You. On both sides of the gate electrode 66, a source made of ap + layer is formed.
-Drain regions 67 and 68 are formed, and a source
And drain electrodes 69 and 70 are formed respectively.
You.

FIG. 11 is a diagram conceptually showing a band state of a structure in which a silicon layer, a multilayer film, and a silicon layer are stacked in the HMISFET of this embodiment. In FIG. 11, the conductivity type of the dopant is ignored.

As shown in the figure, in the present embodiment, Si
Since the Ge composition ratio of the multilayer film functioning as a GeC layer is high, a large hetero-barrier for confining carriers at the valence band edge is utilized by utilizing a large band gap difference between two silicon layers sandwiching the multilayer film. Is formed. Therefore, a p-channel region having high hole confinement efficiency can be formed.

As described above, since the adjustment range of the composition ratio of Ge and C is expanded to a high range, the height of the hetero barrier formed at the conduction band edge and the hetero barrier formed at the valence band edge are increased. The ratio to the height of the barrier can be adjusted to a desired value. Therefore, also in the n-MISFET, the p-MISFE
By using a multilayer film formed of a film common to the T multilayer film as an n-channel, a CMIS device exhibiting high confinement efficiency for both electrons and holes can be formed.

(Other Embodiments) In each of the above embodiments, each semiconductor film (Si _1-x1-y1 Ge _x1 C
_y1 layers and _{Si 1-x2-y2 Ge x2} C y2 layer) is a thin layer to the extent that discrete quantum ranking is not formed (e.g., 1.5
(about nm or less), but even if discrete quantum orders are formed to some extent, the effects of the present invention can be exerted as long as the entire multilayer film functions as a SiGeC layer. Further, for example, Si _1-x1-y1 Ge of 2~3nm a thickness of about _x1 C _y1 layers and _{Si 1-x2-y2 Ge x2} C y2
After the layers are stacked, a heat treatment at about 900 ° C. is performed to make the boundaries between the layers unclear.
The function as an eC layer is easily generated.

In the case of HBT, it is also possible to provide the base layer with a gradient composition such that the band gap decreases from the emitter layer to the collector layer.

In each of the above embodiments, the multilayer film is made of HB
Although the application example using the base layer of T and each channel region of the CMIS device has been described, the multilayer film of the present invention is applicable to other heterojunction devices such as a resonant tunneling diode (RTD).

[0086]

According to the present invention, it is possible to provide a semiconductor crystal film which is a multilayer film functioning as a SiGeC layer having a high Ge composition ratio and a high C composition ratio, a manufacturing method thereof, a semiconductor device or a manufacturing method thereof. Can be.

The semiconductor crystal film of the present invention can be incorporated in various electronic devices such as information communication devices and computers by using it as a channel region of a heterojunction bipolar transistor or a CMIS device.

[Brief description of the drawings]

FIG. 1 is a diagram showing the dependency of the maximum value (upper limit) of the C composition ratio at a lattice position in a single-layer SiGeC crystal on the Ge composition ratio.

FIG. 2 is a sectional view schematically showing a structure of a multilayer film (semiconductor crystal film) according to the first embodiment of the present invention.

FIGS. 3A to 3E are cross-sectional views illustrating steps of manufacturing a semiconductor crystal film according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view schematically illustrating a structure of a multilayer film according to a modification of the first embodiment.

FIG. 5 shows a composition range in which a single crystal can be formed by a conventional single-layer SiGeC layer, and SiG that can be formed by the present invention.
FIG. 3 is a diagram showing a composition range of a multilayer film functioning as an eC layer.

FIG. 6 is a cross-sectional view schematically illustrating a structure of a multilayer film according to a second embodiment.

FIG. 7 is a cross-sectional view schematically showing a structure of an npn-type heterojunction bipolar transistor (HBT) according to a third embodiment.

FIG. 8 is an enlarged sectional view showing a structure of an emitter-base-collector junction shown in FIG. 7;

FIG. 9 is an energy band diagram schematically showing a band structure when no bias is applied in a cross section passing through an emitter layer, a base layer, and a collector layer in the third embodiment.

FIG. 10 shows a heterojunction type CMIS device (HCMI) using a multilayer film functioning as a SiGeC layer as an n-channel and a p-channel according to a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a structure of an (S device).

FIG. 11 is a diagram conceptually showing a band state of a structure in which a silicon layer, a multilayer film, and a silicon layer are stacked in the HCMIS device of the fourth embodiment.

[Explanation of symbols]

_{Reference Signs List} 10 multilayer film 11 Si substrate 12 Si _0.2 Ge _0.8 layer 13 Si _0.785 Ge _0.2 C _0.015 layer 14 Si _0.832 Ge _0.15 C _0.018 layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 (72) Inventor Katsuya No. 1006 Ojidoma, Kadoma, Osaka Matsushita Electric Industrial Co., Ltd. ( 72) Inventor Minoru Kubo 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yoshihiro Hara 1006 Okadoma Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 1006 Kadoma Kadoma Matsushita Electric Industrial Co., Ltd. (72) Takahiro Kawashima, inventor 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd.F-term (reference) TA04 TA07 TB02 TC14 TC19 TF01 TK10 5F003 BB04 BC08 BE07 BE08 BF06 BG06 BG10 BM01 BN09 5F045 AA07 AB01 AC01 AC07 AD10 AF03 CA02 CA05 DA5 4 5F140 AA00 AB03 BA01 BA05 BA09 BB18 BC12 BE07 CB08

Claims (23)

[Claims] 1. A single SiGe structure in which a plurality of semiconductor layers having mutually different compositions are alternately stacked a plurality of times.
A semiconductor crystal film composed of a multilayer film functioning as a C layer, wherein the plurality of semiconductor layers are Si _1-x1-y1 Ge _{x1 Cy 1} layers (0 ≦ x1 <1, 0 <y1 ≦
1) and a Si _1-x2-y2 Ge _x2 C _y2 layer (0 <x2 ≦ 1, 0 ≦ y2 <
1) (x1 <x2, y1> y2, x1 and y2 do not become 0 at the same time). 2. The semiconductor crystal film according to claim 1, wherein each semiconductor layer in said multilayer film is thinner than a thickness at which discrete quantization levels occur. 3. The semiconductor crystal film according to claim 1, wherein the Si _1-x1-y1 Ge _x1 Cy ₁ layer is a SiGeC layer, and the Si _1-x2-y2 Ge _{x2 Cy 2} layer is SiGe layer or Si
A semiconductor crystal film, which is a GeC layer. 4. The semiconductor crystal film according to claim 1, wherein the Si _1-x1-y1 Ge _{x1 Cy 1} layer is a SiC layer, and the Si _1-x2-y2 Ge _{x2 Cy 2} layer is A semiconductor crystal film, which is a SiGeC layer. 5. The semiconductor crystal film according to claim 1, wherein the multilayer film has a C composition ratio at a certain Ge composition ratio determined by a device and a process condition in a single SiGeC layer. A semiconductor crystal film containing more C than the upper limit. 6. The semiconductor crystal film according to claim 1, wherein the Si _1-x1-y1 Ge _{x1 Cy 1} layer and the Si _1-x2-y2 G
The thickness of e _x2 C _y2 layer, a semiconductor crystal film, characterized in that both at 3nm or less. 7. The semiconductor crystal film according to claim 6, wherein said Si _1-x1-y1 Ge _x1 C _y1 layer and said Si _1-x2-y2 G
The thickness of e _x2 C _y2 layer, a semiconductor crystal film, characterized in that both at 1.5nm or less. 8. The semiconductor crystal film according to claim 1, wherein the multilayer film has a Ge composition ratio of 30 atm.% Or more and a C composition ratio of 1.2 atm.% Or more. A semiconductor crystal film which functions as a SiGeC layer having a composition. 9. A single SiGeC layer comprising a base semiconductor layer containing at least Si and a plurality of semiconductor layers formed on the base semiconductor layer and having different compositions alternately stacked a plurality of times. A multi-layer film serving as an active region functioning as a semiconductor device, wherein the multi-layer film includes a Si _1-x1-y1 Ge _{x1 Cy 1} layer (0 ≦ x1 <1, 0 <y1 ≦
1) and a Si _1-x2-y2 Ge _x2 C _y2 layer (0 <x2 ≦ 1, 0 ≦ y2 <
1) (x1 <x2, y1> y2, x1 and y2 do not become 0 at the same time). 10. The semiconductor device according to claim 9, wherein each semiconductor layer in the multilayer film is thinner than a thickness at which discrete quantized levels are generated. 11. The semiconductor device according to claim 9, wherein the Si _1-x1-y1 Ge _x1 C _y1 layer and the Si _1-x2-y2 G
The thickness of e _x2 C _y2 layer, wherein a both is 3nm or less. 12. The semiconductor device according to claim 11, wherein said Si _1-x1-y1 Ge _x1 C _y1 layer and said Si _1-x2-y2 G
The thickness of e _x2 C _y2 layer, wherein a both is 1.5nm or less. 13. The semiconductor device according to claim 9, wherein said multilayer film has a Ge composition ratio of 30 atm.% Or more and a C composition ratio of 1.2 atm.% Or more. A semiconductor device functioning as a SiGeC layer having: 14. The semiconductor device according to claim 9, wherein said multilayer film is a MISFET functioning as a channel. 15. The semiconductor device according to claim 9, wherein said multilayer film is a bipolar transistor functioning as a base layer. 16. A single SiG layer formed by alternately laminating a plurality of semiconductor layers having different compositions from each other a plurality of times.
A method for manufacturing a semiconductor crystal film comprising a multilayer film functioning as an eC layer, wherein a Si _1-x1-y1 Ge _{x1 Cy 1} layer (0 ≦
x1 <1, 0 <y1 ≦ 1) and Si _1-x2-y2 Ge _x2 C _y2
Layer (0 <x2 ≦ 1, 0 ≦ y2 <1) (x1 <x2, y1
> Y2, x1 and y2 do not become 0 at the same time), and (a) epitaxially growing one of the semiconductor layers; and, on the one semiconductor layer, the Si _1-x1-y1 Ge _x1 C
a step (b) of epitaxially growing the other of the _y1 layer and the Si _{1-x2-y 2} Ge _x2 C _y2 layer a plurality of times. 17. The method for manufacturing a semiconductor crystal film according to claim 16, wherein in the steps (a) and (b), each semiconductor layer in the multilayer film is thinner than a thickness at which discrete quantization levels occur. A method for producing a semiconductor crystal film, comprising epitaxially growing. 18. The method of manufacturing a semiconductor crystal film according to claim 16, wherein in the steps (a) and (b), at least one of the semiconductor layers in the multilayer film exceeds 1.5 nm. A method of manufacturing a semiconductor crystal film, further comprising the step of: epitaxially growing the multilayer film with a thickness; and heat-treating the multilayer film. 19. The method for manufacturing a semiconductor crystal film according to claim 16, wherein the step of epitaxially growing a semiconductor layer containing Si, Ge and C in the steps (a) and (b). Then, disilane gas or monosilane gas, germane gas,
A method for producing a semiconductor crystal film, comprising thermally decomposing monomethylsilane gas. 20. A single SiGeC layer formed by alternately laminating a base semiconductor layer containing at least Si and a plurality of semiconductor layers formed on the base semiconductor layer and having mutually different compositions a plurality of times. A multi-layer film serving as an active region functioning as a semiconductor device, comprising: a Si _1-x1-y1 Ge _{x1 Cy 1} layer (0 ≦
x1 <1, 0 <y1 ≦ 1) and Si _1-x2-y2 Ge _x2 C _y2
Layer (0 <x2 ≦ 1, 0 ≦ y2 <1) (x1 <x2, y1
> Y2, x1 and y2 do not become 0 at the same time), and (a) epitaxially growing any one of the semiconductor layers; and forming the Si _1-x1-y1 Ge _x1 on the one semiconductor layer. C
_A method for manufacturing a semiconductor device, comprising a step (b) of epitaxially growing the other of the _y1 layer and the Si _{1-x2-y 2} Ge _x2 C _y2 layer a plurality of times. 21. The method of manufacturing a semiconductor device according to claim 20, wherein in the steps (a) and (b), each semiconductor layer in the multilayer film is epitaxially grown to be thinner than a thickness at which discrete quantization levels occur. A method of manufacturing a semiconductor device. 22. The method of manufacturing a semiconductor device according to claim 20, wherein in the steps (a) and (b), at least one of the semiconductor layers in the multilayer film has a thickness exceeding 1.5 nm. A method of manufacturing a semiconductor device, further comprising the step of: epitaxially growing the multilayer film; 23. The method of manufacturing a semiconductor device according to claim 20, wherein in the steps (a) and (b), the step of epitaxially growing a semiconductor layer containing Si, Ge and C is performed. , Disilane gas or monosilane gas, and germane gas,
A method for manufacturing a semiconductor device, comprising thermally decomposing monomethylsilane gas.