JP3516623B2 - Manufacturing method of semiconductor crystal - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the manufacture of semiconductor crystals.
About the method.

[0002]

2. Description of the Related Art In recent years, attempts have been made to fabricate a semiconductor device utilizing a heterojunction on a Si substrate to manufacture a device that operates at a higher speed than a conventional homojunction Si device. As a material for forming the heterojunction, SiGe and SiGeC, which are mixed crystal semiconductors using Ge and C which are the same group IV elements as Si, are considered to be promising.

Particularly in a SiGeC mixed crystal semiconductor composed of three kinds of elements, by changing the composition ratio of the three kinds of elements,
Since the band gap and the lattice constant can be controlled independently of each other, the device design has a high degree of freedom and the lattice matching with Si is possible, and therefore, it is receiving much attention. For example, Japanese Patent Laid-Open No. 10-116919
As disclosed in Japanese Patent Publication (Kokai) No. Hei 11 (1999) -53242, by utilizing the conduction band discontinuity generated at the hetero interface between the Si layer and the SiGeC layer, the two-dimensional electron gas formed at the interface is used as a carrier, and It is said that a field-effect transistor capable of high-speed operation is possible.

At present, a method of adding a source gas of C during the epitaxial growth of the SiGe layer or a method of adding C by performing ion implantation into the SiGe layer is used for producing the SiGeC mixed crystal. There is.

[0005]

However, for example,
As described in Applied Physics Letters Vol. 65 (1994) p. 2559, there is a solid solution limit in the addition of C to the SiGe layer, and the crystallinity can be improved by adding about 4% or more of C atoms. Is significantly deteriorated and becomes amorphous. Further, according to the experiments conducted by the present inventors, it was found that crystallinity deteriorates when the SiGeC layer is heat-treated (annealed) at various temperatures. In particular, as the C concentration was increased, the crystallinity tended to deteriorate significantly.

FIG. 8 is data obtained by the experiments of the present inventors and is a diagram showing changes in the X-ray diffraction spectrum of a sample obtained by annealing (annealing) the SiGe _0.31 C _0.0012 crystal layer at various temperatures. As shown in the figure, the position of the diffraction peak of the sample heat-treated at a temperature of 800 ° C. or lower is almost the same as the position of the diffraction peak of the as-grown sample. However, the position of the diffraction peak of the sample heat-treated at 900 ° C is
A slight shift has started from the position of the diffraction peak of the as-grown sample. Then, the position of the diffraction peak of the sample heat-treated at a temperature of 950 ° C. or higher begins to largely shift from the position of the diffraction peak of the as-grown sample. Further, the diffraction peak of the sample heat-treated at a temperature of 1000 ° C. or higher has a wide half-value width, and almost no fringe observed in as-grown disappears. From this experimental data, it is found that when heat treatment at a temperature of about 950 ° C or higher is performed, SiGe _0.31
It can be seen that the crystallinity of the C _0.0012 crystal layer is deteriorated.

Therefore, the present inventors have made such SiG
The experiments for investigating the cause of the crystallinity deterioration of the eC crystal layer were conducted, and the deterioration of the SiGeC crystal layer due to the heat treatment was mainly due to the remarkable instability of the Ge—C bond as compared with the Si—C bond in the mixed crystal. It was found to be due to something.

FIGS. 7A and 7B show Ge on a Ge substrate.
_0.98 C _0.02 crystal layer, X when subjected to heat treatment Si _0.98 C _0.02 crystal layer to samples respectively grown on a Si substrate
It is a figure which shows the change of a line diffraction spectrum. However, Ge
_{The 0.98} C _0.02 crystal layer is formed by ion implantation of C into a Ge substrate and heat treatment, and the Si _0.98 C _0.02 crystal layer is epitaxially grown on a Si substrate using Si and a gas as a raw material of C.

As shown in FIG. 7A, G on the Ge substrate is
e_0.98C_0.02In the case of a crystal layer, at a temperature of 475 to 550 ° C
The diffraction peaks from the heat-treated sample were observed at almost the same position.
Although it is measured, it is heat treated at a temperature below 450 ° C.
No diffraction peak from the sample was observed. On the other hand, 6
Ge heat-treated at a temperature of 00 ° C or higher_0.98C_0.02Crystal layer
The diffraction peak position of is shifted, especially at temperatures above 700 ° C.
Heat treated in degrees _0.98C_0.02The peak from the crystal layer is
It has disappeared. This result shows that heat treatment is performed at a temperature of 600 ° C or higher.
If the GeC crystal undergoes a
And especially that the Ge-C bond is dissociated
There is.

On the other hand, as shown in FIG. 7B, in the case of the Si _0.98 C _0.02 crystal layer on the Si substrate, the diffraction peak from the Si _0.98 C _0.02 crystal layer was clearly observed during the heat treatment up to 1000 ° C. There is.

[0012] In summary of the above results, instability of Ge-C bond is one of the causes of crystal deterioration in SiGeC crystal, and suppressing the formation of Ge-C bond is the key to the improvement of crystallinity. Can be said.

The object of the present invention is to pay attention to the cause of the instability of the SiGeC layer, and to form a short-period superlattice layer that does not contain a Ge—C bond and can be regarded as a SiGeC crystal layer, thereby providing good crystallinity. and to provide a manufacturing how a stable semiconductor crystal <br/> thermally.

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

Means for Solving the Problems The method of the present onset Ming semiconductor crystal, epitaxial growth of Si _1-x Ge _x layer mainly composed of Si and Ge (0 <x <1) , the Si A step (a) of alternately repeating the epitaxial growth of the Si layer as a main component twice or more to form a Si _1-x Ge _x / Si superlattice body ; and the above _- mentioned Si _1-x Ge _x / Si superlattice. C in the body
Ion implantation is performed to process and (b), C is to facilities heat treatment to the Si _1-x Ge _x / Si superlattice material introduced, the
C atoms contained in the Si _1-x Ge _x layer are transferred to the Si layer.
Allowed by _{Si 1-x Ge x / Si} 1-y C y superlattice material (0 <y <1)
And a step (c) of forming Si, wherein Si _1-x Ge _x / Si
_1-y C _y consists superlattice material, machine as a single SiGeC layer
It is a method of forming a semiconductor crystal that can function .

According to this method, by utilizing the phenomenon that C atoms move to the Si layer due to the breakage of the Ge—C bond due to the heat treatment, the gas for doping C is not required during the epitaxial growth, and the clean substrate surface is obtained. While maintaining
It is possible to obtain a Si _1-x Ge _x / Si _1-y C _y laminated body which can be applied in various ways.

In the step (a), the Si _1-x Ge _x /
_{Si 1-y C y Si 1} -x Ge x layer and the Si _1-y C _y layer and the Si _1-x Ge _x layer so as to have a thickness of discrete quantization levels occurs superlattice material in By forming the Si layer and the Si layer, a semiconductor crystal functioning as a multiple quantum barrier layer useful for forming a quantum device can be obtained.

In the step (a), the Si _1-x Ge _x /
_{Si 1-y C y Si 1} -x superlattice body in Ge _x layer and the Si _1-y C _y layer and has to have a thickness less than the thickness discrete quantized levels occurs Si _1- by forming a _x Ge _x layer and the Si layer, the semiconductor crystal <br/> is obtained which can function as a single SiGeC layer useful for forming the hetero junction type semiconductor device.

In that case, the heat treatment temperature in the step (c) is preferably higher than 700 ° C.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor crystal and a method of manufacturing the same according to the present invention and embodiments of application to a semiconductor device will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B.
Is a SiGeC mixed crystal (Si _1-x ) according to the first embodiment.
FIG. 3 is a diagram schematically showing a macroscopic laminated structure of Ge _x / Si _1-y C _y short-period superlattice) and a microscopic laminated structure (atomic arrangement) of the short-period superlattice.

As shown in FIG. 1A, S of the present embodiment is
The iGeC mixed crystal is composed of Si _0.68 G on the Si substrate 101.
e _0.32 layer 102 and Si _0.96 C _0.04 layer 103 to 200
It is constituted by alternately laminating for a period. As shown in FIG. 1B, each of the layers 102 and 103 has a triatomic layer.

The formation of the SiGeC mixed crystal is performed by using Si (00
1) Ultra high vacuum chemical vapor deposition (U
HV-CVD method) (Ultra High Vacuum Chemical Vapor
Deposition) method to form Si _0.68 G consisting of 3 atomic layers
e _0.96 C _0.04 layer 1 consisting of _0.32 layer 102 and 3 atomic layers
And 03 are alternately epitaxially grown to obtain 200
It repeats the cycle. The film thickness of the entire SiGeC mixed crystal is about 160 nm. The source gases for Si, Ge, and C are Si ₂ H ₆ , GeH ₄ , and SiH ₃ CH ₃ , respectively.
And the growth temperature is about 550 ° C.

The actual atomic arrangement in the formed short-period superlattice forms a diamond structure.
In (b), in order to explain the concept of the invention in an easy-to-understand manner, tetragonal crystals are used to indicate stacking of atoms. Thus, G
Since the e atom and the C atom do not exist in the layer common to each other, there is almost no formation of Ge—C bond. Moreover, as explained below, this short period superlattice
It functions as one SiGeC crystal.

FIG. 2 shows a document (Semiconductor and Semime).
tals Vol.24 (ACADEMIC PRESS, INC.) p.29 Volume Editor
It is a figure which shows the change of an energy band structure when changing the thickness of the well layer of a certain laminated body and the barrier layer described in FIG. 18 of RAYMOND DINGLE) (written by C. Weisbuch). In the figure, the horizontal axis represents the thickness (nm) of the well layer and the barrier layer, and the vertical axis represents the potential energy (eV). As shown in the figure, in this laminated body, the well layer,
When the thickness of the barrier layer is about 10 nm, the discrete quantization levels are formed, whereas when the thickness of the well layer and the barrier layer is about 1.5 nm or less, the discrete quantization levels are formed. It disappears and changes into one bulk band. That is, since the quantum effect is eliminated, the carriers operate by recognizing the entire short period superlattice layer as one layer. Similarly, in the short-period superlattice body shown in FIGS. 1A and 1B, when the thickness of each layer reaches the level of about 1 nm, the discrete quantization levels disappear, and the short-period superlattice functions as a single SiGeC layer. Will be done.

Therefore, the Si _1-x Ge _x / S of this embodiment is
Since the average thickness of each layer of the i _1-y C _y short-period superlattice (0 <x, y <1) is about 0.8 nm, the crystallinity due to almost no Ge—C bond is included. The function as the SiGeC layer can be exhibited while maintaining the stability.

That is, the manufacturing method of the present embodiment focuses on the fact that the cause of the problem in the conventional SiGeC layer is the instability of the Ge—C bond, and does not include this Ge—C bond, and the SiGeC layer is not included. That can function as Si _1-x Ge
_It can be said that this is a method of forming a _x / Si _1-y C _y short-period superlattice body.

(Second Embodiment) In the present embodiment, Si
Of Si _1-x Ge _x / Si _1-y C by implanting C ions into the / Si _1-x Ge _x laminated film (0 <x <1) and heat treatment.
_A method of manufacturing a Si _1-x Ge _x / Si _1-y C _y laminated body that can be used for forming a _y short-period superlattice (0 <y <1) will be described. 3A and 3B are cross-sectional views showing a manufacturing process of the Si _1-x Ge _x / Si _1-y C _y laminated body in the present embodiment.

First, in the step shown in FIG. 3A, Si (0
01) Si layer 105 having a thickness of 10 nm and Si having a thickness of 10 nm are formed on the substrate 101 by the UHV-CVD method.
_{The 0.8} Ge _0.2 layers 106 are alternately epitaxially grown to form a total of 10 periods of Si / Si _0.8 Ge _0.2 superlattice bodies.

Next, in the step shown in FIG. 3 (b), the ion implantation of C into this superlattice body has an acceleration energy of about 45 ke.
V and dose amount is about 1 × 10 ¹⁵ cm ^-2 . After that, heat treatment is performed at 950 ° C. for 15 seconds.

FIGS. 4A, 4B and 4C respectively show concentration distributions of Ge atoms and C atoms before and after heat treatment in the superlattice, and C atoms in the superlattice immediately after C ion implantation. It is a figure which shows a distribution state and the distribution state of C atom in the superlattice body after heat processing.

In FIG. 4A, the horizontal axis represents the depth in the superlattice and the vertical axis represents the concentration. Also, the curve Ger
Represents the Ge concentration, the curve Cimpl represents the C concentration immediately after the ion implantation and before the heat treatment, and the curve Canea represents the C concentration after the heat treatment. As shown by the curve Cimpl in the figure, before the heat treatment, the Si layer 105 and the Si _0.8 Ge _0.2 layer 1 are formed.
At 06, C is distributed almost uniformly at a concentration of about 1 × 10 ²⁰ cm ^-3 . On the other hand, as shown by the curve Canea in the same figure, after the heat treatment, the Si layer 105 has C
It can be seen that the concentration becomes higher and the C concentration becomes lower in the Si _0.8 Ge _0.2 layer 106. This is shown in FIG.
As shown in (c), it is shown that the C atoms in the Si _0.8 Ge _0.2 layer moved to the adjacent Si layer during the heat treatment.

Therefore, by using C ion implantation and heat treatment to the Si / Si _0.8 Ge _0.2 superlattice, Si _1-y can be obtained even if C is not doped during epitaxial growth.
It can be seen that a C _y / Si _0.8 Ge _0.2 superlattice body can be formed.

FIG. 5 is a diagram showing the difference in the C concentration distribution when the superlattice body subjected to the steps shown in FIGS. 3A and 3B is annealed at different heat treatment temperatures. In the figure, the curve Ger represents the Ge concentration in the superlattice, and the curve Cas
im is the C concentration in the superlattice body not subjected to the heat treatment immediately after the ion implantation, curve C700 is the C concentration in the superlattice body subjected to the heat treatment at 700 ° C., and curve C950 is the superconducting heat treatment at the temperature of 950 ° C. The C concentration in the grid is 1000 ° C for the curve C1000.
The respective C concentrations in the superlattice body subjected to the heat treatment of are shown. The heat treatment time is 15 seconds in each case. As can be seen from the figure, the C atoms did not move sufficiently by the heat treatment at 700 ° C., and the C atoms at 950 ° C. and 1000 ° C.
A sufficient transfer effect of atoms is obtained, and the distribution of C concentration is almost the same in both cases. Therefore, the structure of the SiC / SiGe interface formed by this method is presumed to be stable.

According to the manufacturing method of the present embodiment, Si _1-x
The following advantages can be obtained as compared with the method of forming a Si _1-x Ge _x / Si _1-y C _y laminate by alternately epitaxially growing a Ge _x layer and a Si _1-y C _y layer.

Si_1-x Ge_x Layers and Si_1-y C_y Intersect layers
When forming with each other, Si_1-y C _y After forming the layers
Clean substrate surface due to C raw material remaining in the growth chamber
May lead to problems such as not being obtained. On the other hand,
When C is added by using ON implantation, a laminated body is formed.
Selectively dope C in only one of the two layers
It was considered impossible. In contrast, this embodiment
State Si_1-x Ge_x / Si_1-y C_y With the manufacturing method of the laminated body
First, Si / Si_1-x Ge_x Form a laminate
This Si / Si_1-x Ge_x Ion implantation of C into the laminate
After that, the transfer of C atoms generated in the heat treatment to the Si layer
By utilizing the phenomenon, Si_1-x Ge_x / Si
_1-y C_y Laminates can be formed.

That is, in the manufacturing method of this embodiment,
Is the cause of the defect in the conventional SiGeC layer is Ge-
Focusing on the instability of the C bond,
By utilizing the movement of C atoms due to the instability of
, Si_1-x Ge_x / Si_1-y C _y Forming a laminate
You can

This Si _1-x Ge _x / Si _1-y C
and _y Si _1-x Ge x layer of the laminate in the Si _1-y C _y layer is,
When the thickness is such that discrete quantization levels occur (such as in the case of this embodiment), the multiple quantization barrier layer (M
Si _1-x Ge _x / Si _1-y that can function as QB)
A C _y superlattice can be obtained.

On the other hand, this Si_1-x Ge_x / Si_1-y C_y 
Si in the laminate_1-x Ge_x Layers and Si _1-y C_y Layers and
Has a thickness less than the thickness at which the scattered quantization levels occur
In this case, a single SiG is used as in the first embodiment.
Si that can function as an eC layer _1-x Ge_x / Si_1-y C_y 
Short period superlattice (0 <x, y <1) can be obtained
It The reason will be described below.

The C atom migration phenomenon described in the present embodiment similarly occurs even when using a Si layer having a thickness of 1 nm level and a Si _0.8 Ge _0.2 layer having a thickness of 1 nm level.
Confirmed qualitatively. Further, it has been confirmed that the C atom transfer action by the heat treatment is performed with respect to an arbitrary Ge content ratio in the SiGe layer and an arbitrary C ion implantation condition.

Therefore, by applying the method of this embodiment, the Si layer initially having a thickness of 1 nm level and the Si _1-x Ge _{x are formed.}
After the layer is formed, the ion implantation of C and the heat treatment are sequentially performed to obtain the same as in the first embodiment.
Si _0.8 Ge _0.2 / which functions as one SiGeC layer
A SiC short period superlattice body can be formed.

When the manufacturing method of the first embodiment is used,
The Si _1-x Ge _x layer and the Si _1-y C _y layer are formed alternately, but as described above, the C raw material remains clean in the growth chamber after the Si _1-y C _y layer is formed. There is a problem such as not obtaining a good substrate surface. On the other hand, first, Si
/ Si _1-x Ge _x superlattice is formed in advance, and this Si /
Si _1-x Ge _x superlattice body the C after ion implantation, using the transfer phenomenon of the Si layer of the C atoms generated during the heat _{treatment, Si 1-x Ge x /} Si 1-y C y Si that can function as a SiGeC layer by forming a short-period superlattice
_{A 1-x} Ge _x / Si _1-y C _y short-period superlattice body can be easily and quickly manufactured.

(Third Embodiment) FIG. 6 is a sectional view showing the structure of a heterojunction field effect transistor (HMOSFET) which is a semiconductor device utilizing the short period superlattice body of the third embodiment. The short period superlattice body of this embodiment is
It is formed by one of the methods of the first and second embodiments. Further, in the present embodiment, the application to the n-channel type HMOSFET will be described, but it goes without saying that it can also be applied to the p-channel type HMOSFET.

As shown in the figure, the HMOS of this embodiment is
The FET includes a Si substrate 111 and a p-type well 11 formed on the Si substrate and made of Si containing high-concentration p-type impurities.
2 and the i-Si layer 11 formed on the p-type well 112
3, a δ-doped layer 114 obtained by doping a region near the surface in the i-Si layer 112 and a region spaced apart from the surface with a high concentration of n-type impurities (arsenic, etc.); Layer 1
Si _0.68 Ge _0.32 / Si _0.96 C formed on 14
_0.04 SiGeC layer 116 consisting of a short-period superlattice and Si
Intrinsic Si formed on GeC layer 116
Si cap layer 117 and Si cap layer 11
7 is provided with a gate insulating film 118 made of a silicon oxide film, and a gate electrode 119 made of polysilicon provided on the gate insulating film 118. A source formed by doping the region extending over the i-Si layer 114, the SiGeC layer 116, and the Si cap layer 117 with high-concentration n-type impurities (arsenic etc.) by ion implantation using the gate electrode 119 as a mask. A region 120 and a drain region 121 are provided.

On the left side of FIG. 6, the energy level Ec at the conduction band edge in each of the layers 113, 114, 116 and 117 below the gate electrode of this HMOSFET is displayed. That is, the SiGeC layer 116 made of the Si _0.68 Ge _0.32 / Si _0.96 C _0.04 short period superlattice and the i-Si layer 113.
A so-called hetero barrier is formed by the band discontinuity at the conduction band edge existing between and, and electrons are confined in the region of the SiGeC layer 116 in contact with the Si / SiGeC heterobarrier. Then, an n-channel is formed by the two-dimensional electron gas in this region, and electrons can travel through the n-channel at high speed.

That is, according to the HMOSFET of this embodiment, the n-channel 115 is formed along the Si / SiGeC hetero barrier, and electrons can travel through the n-channel 115 at high speed. In that case, the SiGeC layer has a higher electron mobility than the Si layer, and since it is not necessary to perform impurity doping on the n-channel, ionized impurity scattering is suppressed and high-speed operation is possible.

Next, the SiGeC layer 116 of the present embodiment.
Is the Si _{1-x as in the first} embodiment already described.
By alternately epitaxially growing the Ge _x layer and the Si _1-y C _y layer (0 <x, y <1), the Si _1-x Ge layer is formed.
_x / Si _1-y C _y may be formed by a method of forming a short-period superlattice, or as in the second embodiment, Si _1-x Ge _x
Layer (0 <x <1) and Si layer are alternately epitaxially grown to form a Si / Si _1-x Ge _x short-period superlattice, and then C ion implantation is performed, followed by heat treatment. , Si _1-x Ge _x / Si _1-y C _y
A method of forming a short period superlattice (0 <y <1) may be used.

The semiconductor layer for forming a heterojunction with the SiGeC layer composed of the Si _1-x Ge _x / Si _1-y C _y short-period superlattice is not limited to the Si layer in this embodiment, There are layers containing Si such as a SiGe layer and a SiC layer, and any of them may be used.

Even if the Si _1-x Ge _x / Si _1-y C _y short-period superlattice is doped with n-type or p-type impurities, Si _1-x Ge _x / Si _1-y C _y The function of the short period superlattice as a single SiGeC layer is not impaired.

In the characteristics shown in FIG. 2, Si _1-x
Ge _x / Si _1-y C _{y Even} if a few discrete quantized levels occur in the short-period superlattice, SiGeC as a whole
It only needs to have an energy range that can function as a layer.

[0057]

According to the present invention, the remarkable effect that the crystallinity of the SiGeC-based semiconductor crystal and the speedup of the device using the SiGeC-based semiconductor crystal can be improved can be obtained.

[Brief description of drawings]

1A and 1B are Si according to a first embodiment.
FIG. 1 is a diagram schematically showing a macroscopic laminated structure of a _1-x Ge _x / Si _1-y C _y short-period superlattice and a microscopic laminated structure of the short-period superlattice.

FIG. 2 is a diagram showing changes in the energy band structure when the thicknesses of the well layer and the barrier layer of the laminated body are changed.

3A and 3B are S in the second embodiment.
i is a cross-sectional view showing the manufacturing process of the _{1-x Ge x / Si 1} -y C y multilayer body.

4 (a), (b), and (c) are, respectively, the concentration distribution of Ge atoms and C atoms before and after heat treatment in the superlattice, and the distribution of C atoms in the superlattice immediately after C ion implantation. FIG. 3 is a diagram showing a state and a distribution state of C atoms in a superlattice body after heat treatment.

FIG. 5 is a C of a superlattice body that has undergone the steps shown in FIGS. 3A and 3B when annealed at different heat treatment temperatures.
It is a figure which shows the difference of distribution of density.

FIG. 6 is a heterojunction field effect transistor (H which is a semiconductor device using the short period superlattice body of the third embodiment.
It is a sectional view showing the structure of (MOSFET).

7 (a) and (b) show Ge on a Ge substrate._0.98C
_0.02The crystal layer is formed on the Si substrate by Si _0.98C_0.02Remove the crystal layer
X-ray diffraction when heat-treated each grown sample
It is a figure which shows the change of a spectrum.

FIG. 8 is a diagram showing a change in X-ray diffraction spectrum of a sample in which a SiGe _0.31 C _0.0012 crystal layer is heat-treated (annealed) at various temperatures.

[Explanation of symbols]

101 Si substrate 102 Si _0.68 Ge _0.32 layer 103 Si _0.96 C _0.04 layer 105 Si layer 106 Si _0.8 Ge _0.2 layer 111 Si substrate 112 p-type well 113 i-Si layer 114 δ-doped layer 115 n-channel 116 SiGeC layer 117 Si cap layer 118 gate insulating film 119 gate electrode 120 source region 121 drain region

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsuya Nozawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Takeshi Sugawara 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. Company (72) Inventor Minoru Kubo 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-9-278597 (JP, A) JP-A-5-102177 (JP, A ) JP-A-61-230374 (JP, A) Perez-Rodriguez, A et. al. , Ion beams synthesis and recovery stallization of am orthomorphic SiGe / SiC structures, Nuclear Instruments and verses December, 1996, 2nd year of Esb. 120, pp. 151-155 P. Zaumsel et. a. , Comparison of the thermal stability of Si0.603Ge0.397 / Si and Si0.597Ge0.391C0.012 / Si superlattice, Journal of April, 1997 April. 81 no. 9, pp. 6134-6140 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/06 601 H01L 21/205 H01L 21/363 H01L 21/265 602 H01L 29/78 C30B 29/68 Web of Science (IS I) Science Direct (Els avier)

Claims (4)

(57) [Claims] 1. Si _1-x G containing Si and Ge as main components
2 and the epitaxial growth of e _x layer (0 <x <1), the epitaxial growth of the Si layer containing Si as the main component alternately
(A) forming a one by more repeating Si _1-x Ge _x / Si superlattice material times, the Si _1-x Ge _x / Si step of performing C ion implantation in the superlattice body and (b) , C is to facilities heat treatment to the Si _1-x Ge _x / Si superlattice material introduced, on the C atoms contained in the Si _1-x Ge _x layer
It is moved to the serial Si layer _{Si 1-x Ge x / Si} 1-y C y superlattice
Body and a step (c) to form a (0 <y <1), made from the _{Si 1-x Ge x / Si} 1-y C y superlattice material, single
A method of manufacturing a semiconductor crystal that functions as a SiGeC layer . 2. The method for producing a semiconductor crystal according to claim 1, wherein in the step (a), the content of Si _1-x Ge _x / Si _1-y C _{y is larger} than that.
Si _1-x G so as to have a thickness of Si _1-x Ge _x layers and Si _1-y C _y layer and has discrete quantization levels in the grid in the results
forming a e _x layer and the Si layer, the manufacturing method of the semiconductor crystal. 3. The method for producing a semiconductor crystal according to claim 1, wherein in the step (a), the content of Si _1-x Ge _x / Si _1-y C _{y is larger} than that.
Si _1-x Ge _x layer and the Si layer so as to have a thickness less than the thickness of _the Si _1-x Ge _x layer and the Si _1-y C _y layer and has discrete quantization levels in the grid in the results And a method of manufacturing a semiconductor crystal, the method comprising: 4. A method for producing a semiconductor crystal according to claims 1 to 3, the temperature at which the heat treatment temperature in the step (c) exceeds 700 ° C., the manufacturing method of the semiconductor crystal.